mirror of
https://git.savannah.gnu.org/git/emacs.git
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* verilog-mode.el (verilog-library-extensions): Enable .sv
filename extensions to call verilog-mode. (verilog-auto, verilog-auto-inst, verilog-faq) (verilog-submit-bug-report): Update author support URLs. (verilog-delete-auto, verilog-auto-inout-module) (verilog-auto-inout-comp, verilog-auto): Add AUTOINOUTCOMP for creating complemented testbench modules. Suggested by Yishay Belkind. (verilog-auto-inst-port, verilog-simplify-range-expression): When verilog-auto-inst-param-value is set, don't require a AUTO_TEMPLATE to expand parameter substitutions. Suggested by Yishay Belkind. (verilog-auto-inst-param-value): Add safe variable. (verilog-re-search-forward, verilog-re-search-backward): Fix returning wrong search results on Emacs 22.1. (verilog-modi-cache-results, verilog-auto): Fix warning message about "toggling font-lock-mode." (verilog-auto): Fix loosing font-lock on errors. (verilog-auto-inst-param-value, verilog-mode-version) (verilog-mode-version-date, verilog-read-inst-param-value) (verilog-auto-inst, verilog-auto-inst-param) (verilog-auto-inst-port, verilog-simplify-range-expression): Allow parameters to be replaced with their values, on the expansion of an AUTOINST with Verilog 2001 style parameter settings. Suggested by David Rogoff. * verilog-mode.el (verilog-beg-block-re-ordered, verilog-calc-1): Better support for the property statement. Sometimes this keyword introduces a statement which requires an endproperty keyword, and sometimes it doesn't, dependening on the work before the property word. If property is prefixed with assert, assume or cover keyword, then the statement is ended with a ';' Otherwise, property is like task or specify, and is followed by some number of statements, which are ended with an endproperty keyword. (electric-verilog-tab): Support Emacs 22.2 style handling of tab in a highlighted region: indent each line in region according to mode. Supply this so it works in XEmacs and older Emacs.
This commit is contained in:
Dan Nicolaescu
parent
5e94230e84
commit
7cb1c4d754
@ -1,3 +1,45 @@
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2008-09-05 Wilson Snyder <wsnyder@wsnyder.org>
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* verilog-mode.el (verilog-library-extensions): Enable .sv
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filename extensions to call verilog-mode.
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(verilog-auto, verilog-auto-inst, verilog-faq)
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(verilog-submit-bug-report): Update author support URLs.
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(verilog-delete-auto, verilog-auto-inout-module)
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(verilog-auto-inout-comp, verilog-auto): Add AUTOINOUTCOMP for
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creating complemented testbench modules. Suggested by Yishay
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Belkind.
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(verilog-auto-inst-port, verilog-simplify-range-expression): When
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verilog-auto-inst-param-value is set, don't require a
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AUTO_TEMPLATE to expand parameter substitutions. Suggested by
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Yishay Belkind.
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(verilog-auto-inst-param-value): Add safe variable.
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(verilog-re-search-forward, verilog-re-search-backward): Fix
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returning wrong search results on Emacs 22.1.
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(verilog-modi-cache-results, verilog-auto): Fix warning message
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about "toggling font-lock-mode."
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(verilog-auto): Fix loosing font-lock on errors.
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(verilog-auto-inst-param-value, verilog-mode-version)
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(verilog-mode-version-date, verilog-read-inst-param-value)
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(verilog-auto-inst, verilog-auto-inst-param)
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(verilog-auto-inst-port, verilog-simplify-range-expression): Allow
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parameters to be replaced with their values, on the expansion of
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an AUTOINST with Verilog 2001 style parameter settings. Suggested
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by David Rogoff.
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2008-09-05 Michael McNamara <mac@mail.brushroad.com>
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* verilog-mode.el (verilog-beg-block-re-ordered, verilog-calc-1):
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Better support for the property statement. Sometimes this keyword
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introduces a statement which requires an endproperty keyword, and
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sometimes it doesn't, dependening on the work before the property
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word. If property is prefixed with assert, assume or cover
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keyword, then the statement is ended with a ';' Otherwise,
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property is like task or specify, and is followed by some number
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of statements, which are ended with an endproperty keyword.
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(electric-verilog-tab): Support Emacs 22.2 style handling of tab
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in a highlighted region: indent each line in region according to
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mode. Supply this so it works in XEmacs and older Emacs.
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2008-09-05 Chong Yidong <cyd@stupidchicken.com>
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* international/quail.el: Require help-mode.
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@ -8,7 +8,7 @@
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;;
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;; AUTO features, signal, modsig; by: Wilson Snyder
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;; (wsnyder@wsnyder.org)
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;; http://www.veripool.com
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;; http://www.veripool.org
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;; Keywords: languages
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;; Yoni Rabkin <yoni@rabkins.net> contacted the maintainer of this
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@ -78,8 +78,7 @@
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;; .emacs, or in your site's site-load.el
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; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
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; (setq auto-mode-alist (cons '("\\.v\\'" . verilog-mode) auto-mode-alist))
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; (setq auto-mode-alist (cons '("\\.dv\\'" . verilog-mode) auto-mode-alist))
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; (add-to-list 'auto-mode-alist '("\\.[ds]?v\\'" . verilog-mode))
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;; If you want to customize Verilog mode to fit your needs better,
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;; you may add these lines (the values of the variables presented
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@ -112,15 +111,15 @@
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;;; History:
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;;
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;; See commit history at http://www.veripool.com/verilog-mode.html
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;; See commit history at http://www.veripool.org/verilog-mode.html
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;; (This section is required to appease checkdoc.)
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;;; Code:
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;; This variable will always hold the version number of the mode
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(defconst verilog-mode-version "429"
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(defconst verilog-mode-version "436"
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"Version of this Verilog mode.")
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(defconst verilog-mode-release-date "2008-06-23-GNU"
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(defconst verilog-mode-release-date "2008-09-02-GNU"
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"Release date of this Verilog mode.")
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(defconst verilog-mode-release-emacs t
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"If non-nil, this version of Verilog mode was released with Emacs itself.")
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@ -133,8 +132,7 @@
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;; Insure we have certain packages, and deal with it if we don't
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;; Be sure to note which Emacs flavor and version added each feature.
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(eval-when-compile
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;; The below were disabled when GNU Emacs 22 was released;
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;; perhaps some still need to be there to support Emacs 21.
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;; Provide stuff if we are XEmacs
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(when (featurep 'xemacs)
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(condition-case nil
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(require 'easymenu)
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@ -214,7 +212,13 @@ STRING should be given if the last search was by `string-match' on STRING."
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;; We have an intermediate custom-library, hack around it!
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(defmacro customize-group (var &rest args)
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`(customize ,var))
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)))
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))
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;; OK, do this stuff if we are NOT XEmacs:
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(unless (featurep 'xemacs)
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(unless (fboundp 'region-active-p)
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(defmacro region-active-p ()
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`(and transient-mark-mode mark-active))))
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)
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;; Provide a regular expression optimization routine, using regexp-opt
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;; if provided by the user's elisp libraries
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@ -782,7 +786,7 @@ See also `verilog-library-flags', `verilog-library-directories'."
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:type '(repeat directory))
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(put 'verilog-library-files 'safe-local-variable 'listp)
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(defcustom verilog-library-extensions '(".v")
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(defcustom verilog-library-extensions '(".v" ".sv")
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"*List of extensions to use when looking for files for /*AUTOINST*/.
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See also `verilog-library-flags', `verilog-library-directories'."
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:type '(repeat string)
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@ -865,7 +869,7 @@ instead expand to:
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.i (i[9:0]));"
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:group 'verilog-mode-auto
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:type 'boolean)
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(put 'verilog-auto-inst-vector 'safe-local-variable 'verilog-auto-inst-param-value)
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(put 'verilog-auto-inst-param-value 'safe-local-variable 'verilog-booleanp)
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(defcustom verilog-auto-inst-vector t
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"*If true, when creating default ports with AUTOINST, use bus subscripts.
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@ -1145,6 +1149,8 @@ If set will become buffer local.")
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:help "Help on AUTOARG - declaring module port list"]
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["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum)
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:help "Help on AUTOASCIIENUM - creating ASCII for enumerations"]
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["AUTOINOUTCOMP" (describe-function 'verilog-auto-inout-complement)
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:help "Help on AUTOINOUTCOMP - copying complemented i/o from another file"]
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["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module)
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:help "Help on AUTOINOUTMODULE - copying i/o from another file"]
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["AUTOINOUT" (describe-function 'verilog-auto-inout)
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@ -1278,30 +1284,34 @@ will break, as the o's continuously replace. xa -> x works ok though."
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(defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
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; checkdoc-params: (REGEXP BOUND NOERROR)
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"Like `re-search-forward', but skips over match in comments or strings."
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(store-match-data '(nil nil)) ;; So match-end will return nil if no matches found
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(while (and
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(re-search-forward REGEXP BOUND NOERROR)
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(and (verilog-skip-forward-comment-or-string)
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(progn
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(store-match-data '(nil nil))
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(if BOUND
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(< (point) BOUND)
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t)))))
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(match-end 0))
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(let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
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(while (and
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(re-search-forward REGEXP BOUND NOERROR)
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(setq mdata (match-data))
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(and (verilog-skip-forward-comment-or-string)
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(progn
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(setq mdata '(nil nil))
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(if BOUND
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(< (point) BOUND)
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t)))))
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(store-match-data mdata)
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(match-end 0)))
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(defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
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; checkdoc-params: (REGEXP BOUND NOERROR)
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"Like `re-search-backward', but skips over match in comments or strings."
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(store-match-data '(nil nil)) ;; So match-end will return nil if no matches found
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(while (and
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(re-search-backward REGEXP BOUND NOERROR)
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(and (verilog-skip-backward-comment-or-string)
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(progn
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(store-match-data '(nil nil))
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(if BOUND
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(> (point) BOUND)
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t)))))
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(match-end 0))
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(let ((mdata '(nil nil))) ;; So match-end will return nil if no matches found
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(while (and
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(re-search-backward REGEXP BOUND NOERROR)
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(setq mdata (match-data))
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(and (verilog-skip-backward-comment-or-string)
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(progn
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(setq mdata '(nil nil))
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(if BOUND
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(> (point) BOUND)
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t)))))
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(store-match-data mdata)
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(match-end 0)))
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(defsubst verilog-re-search-forward-quick (regexp bound noerror)
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"Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
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@ -1606,9 +1616,9 @@ find the errors."
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"\\|\\(\\(\\(\\<virtual\\>\\s-+\\)\\|\\(\\<protected\\>\\s-+\\)\\)*\\<task\\>\\)" ;11
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"\\|\\(\\<generate\\>\\)" ;15
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"\\|\\(\\<covergroup\\>\\)" ;16
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"\\|\\(\\<property\\>\\)" ;17
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"\\|\\(\\<\\(rand\\)?sequence\\>\\)" ;18
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"\\|\\(\\<clocking\\>\\)" ;19
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"\\|\\(\\(\\(\\<cover\\>\\s-+\\)\\|\\(\\<assert\\>\\s-+\\)\\)*\\<property\\>\\)" ;17
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"\\|\\(\\<\\(rand\\)?sequence\\>\\)" ;21
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"\\|\\(\\<clocking\\>\\)" ;22
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))
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(defconst verilog-end-block-ordered-rry
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@ -2716,34 +2726,39 @@ With optional ARG, remove existing end of line comments."
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"Function called when TAB is pressed in Verilog mode."
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(interactive)
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;; If verilog-tab-always-indent, indent the beginning of the line.
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(if (or verilog-tab-always-indent
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(save-excursion
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(skip-chars-backward " \t")
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(bolp)))
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(let* ((oldpnt (point))
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(boi-point
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(save-excursion
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(beginning-of-line)
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(skip-chars-forward " \t")
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(verilog-indent-line)
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(back-to-indentation)
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(point))))
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(if (< (point) boi-point)
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(back-to-indentation)
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(cond ((not verilog-tab-to-comment))
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((not (eolp))
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(end-of-line))
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(t
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(indent-for-comment)
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(when (and (eolp) (= oldpnt (point)))
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(cond
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;; The region is active, indent it.
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((and (region-active-p)
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(not (eq (region-beginning) (region-end))))
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(indent-region (region-beginning) (region-end) nil))
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((or verilog-tab-always-indent
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(save-excursion
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(skip-chars-backward " \t")
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(bolp)))
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(let* ((oldpnt (point))
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(boi-point
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(save-excursion
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(beginning-of-line)
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(skip-chars-forward " \t")
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(verilog-indent-line)
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(back-to-indentation)
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(point))))
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(if (< (point) boi-point)
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(back-to-indentation)
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(cond ((not verilog-tab-to-comment))
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((not (eolp))
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(end-of-line))
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(t
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(indent-for-comment)
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(when (and (eolp) (= oldpnt (point)))
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; kill existing comment
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(beginning-of-line)
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(re-search-forward comment-start-skip oldpnt 'move)
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(goto-char (match-beginning 0))
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(skip-chars-backward " \t")
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(kill-region (point) oldpnt))))))
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(progn (insert "\t"))))
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(beginning-of-line)
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(re-search-forward comment-start-skip oldpnt 'move)
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(goto-char (match-beginning 0))
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(skip-chars-backward " \t")
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(kill-region (point) oldpnt)))))))
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(t (progn (insert "\t")))))
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;;
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@ -4166,10 +4181,9 @@ Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
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;; need to consider typedef struct here...
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((looking-at "\\<class\\|struct\\|function\\|task\\|property\\>")
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((looking-at "\\<class\\|struct\\|function\\|task\\>")
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; *sigh* These words have an optional prefix:
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; extern {virtual|protected}? function a();
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; assert property (p_1);
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; typedef class foo;
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; and we don't want to confuse this with
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; function a();
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@ -4180,7 +4194,18 @@ Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
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(if (looking-at verilog-beg-block-re-ordered)
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(throw 'nesting 'block)
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(throw 'nesting 'defun)))
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((looking-at "\\<property\\>")
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; *sigh*
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; {assert|assume|cover} property (); are complete
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; but
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; property ID () ... needs end_property
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(verilog-beg-of-statement)
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(if (looking-at "\\(assert\\|assume\\|cover\\)\\s-+property\\>")
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(throw 'nesting 'statement) ; We don't need an endproperty for these
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(throw 'nesting 'block) ;We still need a endproperty
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))
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(t (throw 'nesting 'block))))
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((looking-at verilog-end-block-re)
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@ -7481,7 +7506,7 @@ Cache the output of function so next call may have faster access."
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;; Clear then restore any hilighting to make emacs19 happy
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(let ((fontlocked (when (and (boundp 'font-lock-mode)
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font-lock-mode)
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(font-lock-mode nil)
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(font-lock-mode 0)
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t))
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func-returns)
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(setq func-returns (funcall function))
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@ -7726,7 +7751,7 @@ This repairs those mis-inserted by a AUTOARG."
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(last-pass ""))
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(while (not (equal last-pass out))
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(setq last-pass out)
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(while (string-match "(\\<\\([0-9]+\\)\\>)" out)
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(while (string-match "(\\<\\([0-9A-Z-az_]+\\)\\>)" out)
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(setq out (replace-match "\\1" nil nil out)))
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(while (string-match "\\<\\([0-9]+\\)\\>\\s *\\+\\s *\\<\\([0-9]+\\)\\>" out)
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(setq out (replace-match
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@ -7875,13 +7900,13 @@ called before and after this function, respectively."
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(run-hooks 'verilog-before-delete-auto-hook)
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;; Remove those that have multi-line insertions, possibly with parameters
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(verilog-auto-re-search-do
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(verilog-auto-re-search-do
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(concat "/\\*"
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(eval-when-compile
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(verilog-regexp-words
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`("AUTOASCIIENUM" "AUTOCONCATCOMMENT" "AUTODEFINEVALUE"
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"AUTOINOUT" "AUTOINOUTMODULE" "AUTOINPUT" "AUTOOUTPUT"
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"AUTOOUTPUTEVERY"
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"AUTOINOUT" "AUTOINOUTCOMP" "AUTOINOUTMODULE"
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"AUTOINPUT" "AUTOOUTPUT" "AUTOOUTPUTEVERY"
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"AUTOREG" "AUTOREGINPUT" "AUTORESET" "AUTOTIEOFF"
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"AUTOUNUSED" "AUTOWIRE")))
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"\\(\\|([^)]*)\\|(\"[^\"]*\")\\)" ; Optional parens or quoted parameter
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@ -8193,13 +8218,9 @@ If PAR-VALUES replace final strings with these parameter values."
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(verilog-sig-bits (assoc port vector-skip-list)))))
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(or (verilog-sig-bits port-st) "")
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""))
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;; Default if not found
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(tpl-net (if (verilog-sig-multidim port-st)
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(concat port "/*" (verilog-sig-multidim-string port-st)
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vl-bits "*/")
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(concat port vl-bits)))
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(case-fold-search nil)
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(check-values par-values))
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(check-values par-values)
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tpl-net)
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;; Replace parameters in bit-width
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(when (and check-values
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(not (equal vl-bits "")))
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@ -8210,6 +8231,11 @@ If PAR-VALUES replace final strings with these parameter values."
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t t vl-bits)
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check-values (cdr check-values)))
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(setq vl-bits (verilog-simplify-range-expression vl-bits))) ; Not in the loop for speed
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;; Default net value if not found
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(setq tpl-net (if (verilog-sig-multidim port-st)
|
||||
(concat port "/*" (verilog-sig-multidim-string port-st)
|
||||
vl-bits "*/")
|
||||
(concat port vl-bits)))
|
||||
;; Find template
|
||||
(cond (tpl-ass ; Template of exact port name
|
||||
(setq tpl-net (nth 1 tpl-ass)))
|
||||
@ -8359,7 +8385,7 @@ Exceptions:
|
||||
Unless you are instantiating a module multiple times, or the module is
|
||||
something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
|
||||
It just makes for unmaintainable code. To sanitize signal names, try
|
||||
vrename from http://www.veripool.com.
|
||||
vrename from http://www.veripool.org.
|
||||
|
||||
When you need to violate this suggestion there are two ways to list
|
||||
exceptions, placing them before the AUTOINST, or using templates.
|
||||
@ -9212,7 +9238,7 @@ same expansion will result from only extracting inouts starting with i:
|
||||
(verilog-insert-indent "// End of automatics\n"))
|
||||
(when v2k (verilog-repair-close-comma)))))
|
||||
|
||||
(defun verilog-auto-inout-module ()
|
||||
(defun verilog-auto-inout-module (&optional complement)
|
||||
"Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto].
|
||||
Take input/output/inout statements from the specified module and insert
|
||||
into the current module. This is useful for making null templates and
|
||||
@ -9248,9 +9274,9 @@ Typing \\[verilog-auto] will make this into:
|
||||
module ExampShell (/*AUTOARG*/i,o,io)
|
||||
/*AUTOINOUTMODULE(\"ExampMain\")*/
|
||||
// Beginning of automatic in/out/inouts (from specific module)
|
||||
input i;
|
||||
output o;
|
||||
inout io;
|
||||
input i;
|
||||
// End of automatics
|
||||
endmodule
|
||||
|
||||
@ -9273,10 +9299,14 @@ same expansion will result from only extracting signals starting with i:
|
||||
(moddecls (verilog-modi-get-decls modi))
|
||||
(submoddecls (verilog-modi-get-decls submodi))
|
||||
(sig-list-i (verilog-signals-not-in
|
||||
(verilog-decls-get-inputs submoddecls)
|
||||
(if complement
|
||||
(verilog-decls-get-outputs submoddecls)
|
||||
(verilog-decls-get-inputs submoddecls))
|
||||
(append (verilog-decls-get-inputs moddecls))))
|
||||
(sig-list-o (verilog-signals-not-in
|
||||
(verilog-decls-get-outputs submoddecls)
|
||||
(if complement
|
||||
(verilog-decls-get-inputs submoddecls)
|
||||
(verilog-decls-get-outputs submoddecls))
|
||||
(append (verilog-decls-get-outputs moddecls))))
|
||||
(sig-list-io (verilog-signals-not-in
|
||||
(verilog-decls-get-inouts submoddecls)
|
||||
@ -9302,6 +9332,57 @@ same expansion will result from only extracting signals starting with i:
|
||||
(verilog-insert-indent "// End of automatics\n"))
|
||||
(when v2k (verilog-repair-close-comma)))))))
|
||||
|
||||
(defun verilog-auto-inout-comp ()
|
||||
"Expand AUTOINOUTCOMP statements, as part of \\[verilog-auto].
|
||||
Take input/output/inout statements from the specified module and
|
||||
insert the inverse into the current module (inputs become outputs
|
||||
and vice-versa.) This is useful for making test and stimulus
|
||||
modules which need to have complementing I/O with another module.
|
||||
Any I/O which are already defined in this module will not be
|
||||
redefined.
|
||||
|
||||
Limitations:
|
||||
If placed inside the parenthesis of a module declaration, it creates
|
||||
Verilog 2001 style, else uses Verilog 1995 style.
|
||||
|
||||
Concatenation and outputting partial busses is not supported.
|
||||
|
||||
Module names must be resolvable to filenames. See `verilog-auto-inst'.
|
||||
|
||||
Signals are not inserted in the same order as in the original module,
|
||||
though they will appear to be in the same order to a AUTOINST
|
||||
instantiating either module.
|
||||
|
||||
An example:
|
||||
|
||||
module ExampShell (/*AUTOARG*/)
|
||||
/*AUTOINOUTCOMP(\"ExampMain\")*/
|
||||
endmodule
|
||||
|
||||
module ExampMain (i,o,io)
|
||||
input i;
|
||||
output o;
|
||||
inout io;
|
||||
endmodule
|
||||
|
||||
Typing \\[verilog-auto] will make this into:
|
||||
|
||||
module ExampShell (/*AUTOARG*/i,o,io)
|
||||
/*AUTOINOUTCOMP(\"ExampMain\")*/
|
||||
// Beginning of automatic in/out/inouts (from specific module)
|
||||
output i;
|
||||
inout io;
|
||||
input o;
|
||||
// End of automatics
|
||||
endmodule
|
||||
|
||||
You may also provide an optional regular expression, in which case only
|
||||
signals matching the regular expression will be included. For example the
|
||||
same expansion will result from only extracting signals starting with i:
|
||||
|
||||
/*AUTOINOUTCOMP(\"ExampMain\",\"^i\")*/"
|
||||
(verilog-auto-inout-module t))
|
||||
|
||||
(defun verilog-auto-sense-sigs (moddecls presense-sigs)
|
||||
"Return list of signals for current AUTOSENSE block."
|
||||
(let* ((sigss (verilog-read-always-signals))
|
||||
@ -9852,6 +9933,7 @@ Likewise, you can delete or inject AUTOs with:
|
||||
Using \\[describe-function], see also:
|
||||
`verilog-auto-arg' for AUTOARG module instantiations
|
||||
`verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
|
||||
`verilog-auto-inout-comp' for AUTOINOUTCOMP copy complemented i/o
|
||||
`verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
|
||||
`verilog-auto-inout' for AUTOINOUT making hierarchy inouts
|
||||
`verilog-auto-input' for AUTOINPUT making hierarchy inputs
|
||||
@ -9872,7 +9954,7 @@ Using \\[describe-function], see also:
|
||||
`verilog-read-includes' for reading `includes
|
||||
|
||||
If you have bugs with these autos, try contacting the AUTOAUTHOR
|
||||
Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.com."
|
||||
Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.org."
|
||||
(interactive)
|
||||
(unless noninteractive (message "Updating AUTOs..."))
|
||||
(if (fboundp 'dinotrace-unannotate-all)
|
||||
@ -9884,7 +9966,7 @@ Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.com."
|
||||
;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
|
||||
(fontlocked (when (and (boundp 'font-lock-mode)
|
||||
font-lock-mode)
|
||||
(font-lock-mode nil)
|
||||
(font-lock-mode 0)
|
||||
t))
|
||||
;; Cache directories; we don't write new files, so can't change
|
||||
(verilog-dir-cache-preserving t))
|
||||
@ -9926,6 +10008,7 @@ Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.com."
|
||||
;;
|
||||
;; first in/outs from other files
|
||||
(verilog-auto-re-search-do "/\\*AUTOINOUTMODULE([^)]*)\\*/" 'verilog-auto-inout-module)
|
||||
(verilog-auto-re-search-do "/\\*AUTOINOUTCOMP([^)]*)\\*/" 'verilog-auto-inout-comp)
|
||||
;; next in/outs which need previous sucked inputs first
|
||||
(verilog-auto-re-search-do "/\\*AUTOOUTPUT\\((\"[^\"]*\")\\)\\*/"
|
||||
'(lambda () (verilog-auto-output t)))
|
||||
@ -9959,11 +10042,11 @@ Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.com."
|
||||
(cond ((and oldbuf (equal oldbuf (buffer-string)))
|
||||
(set-buffer-modified-p nil)
|
||||
(unless noninteractive (message "Updating AUTOs...done (no changes)")))
|
||||
(t (unless noninteractive (message "Updating AUTOs...done"))))))
|
||||
(t (unless noninteractive (message "Updating AUTOs...done")))))
|
||||
;; Unwind forms
|
||||
(progn
|
||||
;; Restore font-lock
|
||||
(when fontlocked (font-lock-mode t)))))
|
||||
(when fontlocked (font-lock-mode t))))))
|
||||
|
||||
|
||||
;;
|
||||
@ -10453,7 +10536,7 @@ Files are checked based on `verilog-library-directories'."
|
||||
(princ "\n")
|
||||
(princ "For new releases, see http://www.verilog.com\n")
|
||||
(princ "\n")
|
||||
(princ "For frequently asked questions, see http://www.veripool.com/verilog-mode-faq.html\n")
|
||||
(princ "For frequently asked questions, see http://www.veripool.org/verilog-mode-faq.html\n")
|
||||
(princ "\n")
|
||||
(princ "To submit a bug, use M-x verilog-submit-bug-report\n")
|
||||
(princ "\n")))
|
||||
@ -10520,9 +10603,9 @@ my coding ability... until now. I'd really appreciate anything you
|
||||
could do to help me out with this minor deficiency in the product.
|
||||
|
||||
If you have bugs with the AUTO functions, please CC the AUTOAUTHOR Wilson
|
||||
Snyder (wsnyder@wsnyder.org) and/or see http://www.veripool.com.
|
||||
Snyder (wsnyder@wsnyder.org) and/or see http://www.veripool.org.
|
||||
You may also want to look at the Verilog-Mode FAQ, see
|
||||
http://www.veripool.com/verilog-mode-faq.html.
|
||||
http://www.veripool.org/verilog-mode-faq.html.
|
||||
|
||||
To reproduce the bug, start a fresh Emacs via " invocation-name "
|
||||
-no-init-file -no-site-file'. In a new buffer, in Verilog mode, type
|
||||
|
||||
Loading…
Reference in New Issue
Block a user