mirror of
https://git.FreeBSD.org/ports.git
synced 2024-12-11 02:50:24 +00:00
231 lines
7.7 KiB
Plaintext
231 lines
7.7 KiB
Plaintext
bin/yosys
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bin/yosys-config
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bin/yosys-filterlib
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bin/yosys-smtbmc
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%%DATADIR%%/abc9_map.v
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%%DATADIR%%/abc9_model.v
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%%DATADIR%%/abc9_unmap.v
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%%DATADIR%%/achronix/speedster22i/cells_map.v
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%%DATADIR%%/achronix/speedster22i/cells_sim.v
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%%DATADIR%%/adff2dff.v
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%%DATADIR%%/anlogic/arith_map.v
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%%DATADIR%%/anlogic/cells_map.v
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%%DATADIR%%/anlogic/cells_sim.v
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%%DATADIR%%/anlogic/eagle_bb.v
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%%DATADIR%%/anlogic/lutram_init_16x4.vh
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%%DATADIR%%/anlogic/lutrams.txt
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%%DATADIR%%/anlogic/lutrams_map.v
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%%DATADIR%%/cells.lib
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%%DATADIR%%/cmp2lcu.v
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%%DATADIR%%/cmp2lut.v
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%%DATADIR%%/coolrunner2/cells_counter_map.v
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%%DATADIR%%/coolrunner2/cells_latch.v
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%%DATADIR%%/coolrunner2/cells_sim.v
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%%DATADIR%%/coolrunner2/tff_extract.v
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%%DATADIR%%/coolrunner2/xc2_dff.lib
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%%DATADIR%%/dff2ff.v
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%%DATADIR%%/ecp5/arith_map.v
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%%DATADIR%%/ecp5/bram_conn_1.vh
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%%DATADIR%%/ecp5/bram_conn_18.vh
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%%DATADIR%%/ecp5/bram_conn_2.vh
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%%DATADIR%%/ecp5/bram_conn_36.vh
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%%DATADIR%%/ecp5/bram_conn_4.vh
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%%DATADIR%%/ecp5/bram_conn_9.vh
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%%DATADIR%%/ecp5/bram_init_1_2_4.vh
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%%DATADIR%%/ecp5/bram_init_9_18_36.vh
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%%DATADIR%%/ecp5/brams.txt
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%%DATADIR%%/ecp5/brams_map.v
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%%DATADIR%%/ecp5/cells_bb.v
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%%DATADIR%%/ecp5/cells_ff.vh
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%%DATADIR%%/ecp5/cells_io.vh
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%%DATADIR%%/ecp5/cells_map.v
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%%DATADIR%%/ecp5/cells_sim.v
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%%DATADIR%%/ecp5/dsp_map.v
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%%DATADIR%%/ecp5/latches_map.v
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%%DATADIR%%/ecp5/lutrams.txt
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%%DATADIR%%/ecp5/lutrams_map.v
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%%DATADIR%%/efinix/arith_map.v
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%%DATADIR%%/efinix/brams.txt
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%%DATADIR%%/efinix/brams_map.v
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%%DATADIR%%/efinix/cells_map.v
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%%DATADIR%%/efinix/cells_sim.v
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%%DATADIR%%/efinix/gbuf_map.v
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%%DATADIR%%/gate2lut.v
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%%DATADIR%%/gatemate/arith_map.v
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%%DATADIR%%/gatemate/brams.txt
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%%DATADIR%%/gatemate/brams_init_20.vh
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%%DATADIR%%/gatemate/brams_init_40.vh
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%%DATADIR%%/gatemate/brams_map.v
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%%DATADIR%%/gatemate/cells_bb.v
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%%DATADIR%%/gatemate/cells_sim.v
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%%DATADIR%%/gatemate/lut_map.v
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%%DATADIR%%/gatemate/mul_map.v
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%%DATADIR%%/gatemate/mux_map.v
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%%DATADIR%%/gatemate/reg_map.v
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%%DATADIR%%/gowin/arith_map.v
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%%DATADIR%%/gowin/bram_init_16.vh
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%%DATADIR%%/gowin/brams.txt
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%%DATADIR%%/gowin/brams_init3.vh
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%%DATADIR%%/gowin/brams_map.v
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%%DATADIR%%/gowin/cells_map.v
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%%DATADIR%%/gowin/cells_sim.v
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%%DATADIR%%/gowin/lutrams.txt
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%%DATADIR%%/gowin/lutrams_map.v
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%%DATADIR%%/greenpak4/cells_blackbox.v
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%%DATADIR%%/greenpak4/cells_latch.v
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%%DATADIR%%/greenpak4/cells_map.v
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%%DATADIR%%/greenpak4/cells_sim.v
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%%DATADIR%%/greenpak4/cells_sim_ams.v
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%%DATADIR%%/greenpak4/cells_sim_digital.v
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%%DATADIR%%/greenpak4/cells_sim_wip.v
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%%DATADIR%%/greenpak4/gp_dff.lib
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%%DATADIR%%/ice40/abc9_model.v
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%%DATADIR%%/ice40/arith_map.v
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%%DATADIR%%/ice40/brams.txt
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%%DATADIR%%/ice40/brams_init1.vh
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%%DATADIR%%/ice40/brams_init2.vh
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%%DATADIR%%/ice40/brams_init3.vh
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%%DATADIR%%/ice40/brams_map.v
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%%DATADIR%%/ice40/cells_map.v
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%%DATADIR%%/ice40/cells_sim.v
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%%DATADIR%%/ice40/dsp_map.v
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%%DATADIR%%/ice40/ff_map.v
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%%DATADIR%%/ice40/latches_map.v
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%%DATADIR%%/include/backends/cxxrtl/cxxrtl.h
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%%DATADIR%%/include/backends/cxxrtl/cxxrtl_capi.cc
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%%DATADIR%%/include/backends/cxxrtl/cxxrtl_capi.h
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%%DATADIR%%/include/backends/cxxrtl/cxxrtl_vcd.h
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%%DATADIR%%/include/backends/cxxrtl/cxxrtl_vcd_capi.cc
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%%DATADIR%%/include/backends/cxxrtl/cxxrtl_vcd_capi.h
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%%DATADIR%%/include/backends/rtlil/rtlil_backend.h
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%%DATADIR%%/include/frontends/ast/ast.h
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%%DATADIR%%/include/frontends/ast/ast_binding.h
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%%DATADIR%%/include/frontends/blif/blifparse.h
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%%DATADIR%%/include/kernel/binding.h
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%%DATADIR%%/include/kernel/celledges.h
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%%DATADIR%%/include/kernel/celltypes.h
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%%DATADIR%%/include/kernel/consteval.h
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%%DATADIR%%/include/kernel/constids.inc
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%%DATADIR%%/include/kernel/ff.h
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%%DATADIR%%/include/kernel/ffinit.h
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%%DATADIR%%/include/kernel/hashlib.h
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%%DATADIR%%/include/kernel/log.h
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%%DATADIR%%/include/kernel/macc.h
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%%DATADIR%%/include/kernel/mem.h
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%%DATADIR%%/include/kernel/modtools.h
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%%DATADIR%%/include/kernel/qcsat.h
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%%DATADIR%%/include/kernel/register.h
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%%DATADIR%%/include/kernel/rtlil.h
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%%DATADIR%%/include/kernel/satgen.h
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%%DATADIR%%/include/kernel/sigtools.h
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%%DATADIR%%/include/kernel/utils.h
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%%DATADIR%%/include/kernel/yosys.h
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%%DATADIR%%/include/libs/ezsat/ezminisat.h
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%%DATADIR%%/include/libs/ezsat/ezsat.h
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%%DATADIR%%/include/libs/json11/json11.hpp
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%%DATADIR%%/include/libs/sha1/sha1.h
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%%DATADIR%%/include/passes/fsm/fsmdata.h
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%%DATADIR%%/intel/common/altpll_bb.v
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%%DATADIR%%/intel/common/brams_m9k.txt
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%%DATADIR%%/intel/common/brams_map_m9k.v
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%%DATADIR%%/intel/common/ff_map.v
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%%DATADIR%%/intel/common/m9k_bb.v
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%%DATADIR%%/intel/cyclone10lp/cells_map.v
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%%DATADIR%%/intel/cyclone10lp/cells_sim.v
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%%DATADIR%%/intel/cycloneiv/cells_map.v
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%%DATADIR%%/intel/cycloneiv/cells_sim.v
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%%DATADIR%%/intel/cycloneive/cells_map.v
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%%DATADIR%%/intel/cycloneive/cells_sim.v
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%%DATADIR%%/intel/max10/cells_map.v
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%%DATADIR%%/intel/max10/cells_sim.v
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%%DATADIR%%/intel_alm/common/abc9_map.v
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%%DATADIR%%/intel_alm/common/abc9_model.v
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%%DATADIR%%/intel_alm/common/abc9_unmap.v
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%%DATADIR%%/intel_alm/common/alm_map.v
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%%DATADIR%%/intel_alm/common/alm_sim.v
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%%DATADIR%%/intel_alm/common/arith_alm_map.v
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%%DATADIR%%/intel_alm/common/bram_m10k.txt
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%%DATADIR%%/intel_alm/common/bram_m20k.txt
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%%DATADIR%%/intel_alm/common/bram_m20k_map.v
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%%DATADIR%%/intel_alm/common/dff_map.v
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%%DATADIR%%/intel_alm/common/dff_sim.v
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%%DATADIR%%/intel_alm/common/dsp_map.v
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%%DATADIR%%/intel_alm/common/dsp_sim.v
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%%DATADIR%%/intel_alm/common/lutram_mlab.txt
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%%DATADIR%%/intel_alm/common/megafunction_bb.v
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%%DATADIR%%/intel_alm/common/mem_sim.v
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%%DATADIR%%/intel_alm/common/misc_sim.v
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%%DATADIR%%/intel_alm/common/quartus_rename.v
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%%DATADIR%%/intel_alm/cyclonev/cells_sim.v
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%%DATADIR%%/machxo2/cells_map.v
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%%DATADIR%%/machxo2/cells_sim.v
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%%DATADIR%%/mul2dsp.v
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%%DATADIR%%/nexus/arith_map.v
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%%DATADIR%%/nexus/brams.txt
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%%DATADIR%%/nexus/brams_init.vh
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%%DATADIR%%/nexus/brams_map.v
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%%DATADIR%%/nexus/cells_map.v
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%%DATADIR%%/nexus/cells_sim.v
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%%DATADIR%%/nexus/cells_xtra.v
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%%DATADIR%%/nexus/dsp_map.v
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%%DATADIR%%/nexus/latches_map.v
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%%DATADIR%%/nexus/lrams.txt
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%%DATADIR%%/nexus/lrams_init.vh
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%%DATADIR%%/nexus/lrams_map.v
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%%DATADIR%%/nexus/lutrams.txt
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%%DATADIR%%/nexus/lutrams_map.v
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%%DATADIR%%/nexus/parse_init.vh
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%%DATADIR%%/pmux2mux.v
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%%DATADIR%%/python3/smtio.py
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%%DATADIR%%/quicklogic/abc9_map.v
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%%DATADIR%%/quicklogic/abc9_model.v
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%%DATADIR%%/quicklogic/abc9_unmap.v
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%%DATADIR%%/quicklogic/cells_sim.v
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%%DATADIR%%/quicklogic/lut_sim.v
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%%DATADIR%%/quicklogic/pp3_cells_map.v
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%%DATADIR%%/quicklogic/pp3_cells_sim.v
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%%DATADIR%%/quicklogic/pp3_ffs_map.v
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%%DATADIR%%/quicklogic/pp3_latches_map.v
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%%DATADIR%%/quicklogic/pp3_lut_map.v
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%%DATADIR%%/sf2/arith_map.v
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%%DATADIR%%/sf2/cells_map.v
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%%DATADIR%%/sf2/cells_sim.v
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%%DATADIR%%/simcells.v
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%%DATADIR%%/simlib.v
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%%DATADIR%%/techmap.v
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%%DATADIR%%/xilinx/abc9_model.v
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%%DATADIR%%/xilinx/arith_map.v
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%%DATADIR%%/xilinx/brams_init_16.vh
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%%DATADIR%%/xilinx/brams_init_18.vh
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%%DATADIR%%/xilinx/brams_init_32.vh
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%%DATADIR%%/xilinx/brams_init_36.vh
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%%DATADIR%%/xilinx/brams_init_8.vh
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%%DATADIR%%/xilinx/brams_init_9.vh
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%%DATADIR%%/xilinx/cells_map.v
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%%DATADIR%%/xilinx/cells_sim.v
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%%DATADIR%%/xilinx/cells_xtra.v
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%%DATADIR%%/xilinx/ff_map.v
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%%DATADIR%%/xilinx/lut4_lutrams.txt
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%%DATADIR%%/xilinx/lut6_lutrams.txt
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%%DATADIR%%/xilinx/lut_map.v
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%%DATADIR%%/xilinx/lutrams_map.v
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%%DATADIR%%/xilinx/mux_map.v
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%%DATADIR%%/xilinx/xc2v_brams.txt
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%%DATADIR%%/xilinx/xc2v_brams_map.v
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%%DATADIR%%/xilinx/xc3s_mult_map.v
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%%DATADIR%%/xilinx/xc3sa_brams.txt
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%%DATADIR%%/xilinx/xc3sda_brams.txt
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%%DATADIR%%/xilinx/xc3sda_dsp_map.v
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%%DATADIR%%/xilinx/xc4v_dsp_map.v
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%%DATADIR%%/xilinx/xc5v_dsp_map.v
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%%DATADIR%%/xilinx/xc6s_brams.txt
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%%DATADIR%%/xilinx/xc6s_brams_map.v
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%%DATADIR%%/xilinx/xc6s_dsp_map.v
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%%DATADIR%%/xilinx/xc7_brams_map.v
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%%DATADIR%%/xilinx/xc7_dsp_map.v
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%%DATADIR%%/xilinx/xc7_xcu_brams.txt
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%%DATADIR%%/xilinx/xcu_brams_map.v
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%%DATADIR%%/xilinx/xcu_dsp_map.v
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%%DATADIR%%/xilinx/xcup_urams.txt
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%%DATADIR%%/xilinx/xcup_urams_map.v
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