1
0
mirror of https://git.FreeBSD.org/ports.git synced 2024-12-14 03:10:47 +00:00
freebsd-ports/cad/iverilog/pkg-descr
Dmitry Marakasov 1d1f878054 - Fix trailing whitespace in pkg-descrs, categories [a-f]*
Approved by:	portmgr blanket
2016-05-19 10:21:23 +00:00

16 lines
758 B
Plaintext

Icarus Verilog is a Verilog simulation and synthesis tool. It
operates as a compiler, compiling source code written in Verilog
(IEEE-1364) into some target format. For batch simulation, the
compiler can generate C++ code that is compiled and linked with
a run time library (called "vvm") then executed as a command to
run the simulation. For synthesis, the compiler generates netlists
in the desired format.
The compiler proper is intended to parse and elaborate design
descriptions written to the IEEE standard IEEE Std 1364-2000. The
standard proper is due to be release towards the middle of the
year 2000. This is a fairly large and complex standard, so it will
take some time for it to get there, but that's the goal.
WWW: http://iverilog.icarus.com/