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13 lines
817 B
Plaintext
13 lines
817 B
Plaintext
Netgen is a tool for comparing netlists, a process known as LVS, which stands
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for "Layout vs. Schematic". This is an important step in the integrated circuit
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design flow, ensuring that the geometry that has been laid out matches the
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expected circuit. Very small circuits can bypass this step by confirming circuit
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operation through extraction and simulation. Very large digital circuits are
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usually generated by tools from high-level descriptions, using compilers that
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ensure the correct layout geometry. The greatest need for LVS is in large analog
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or mixed-signal circuits that cannot be simulated in reasonable time. Even for
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small circuits, LVS can be done much faster than simulation, and provides
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feedback that makes it easier to find an error than does a simulation.
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WWW: http://opencircuitdesign.com/netgen/
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