1998-09-15 08:23:17 +00:00
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/*
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*
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* ===================================
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* HARP | Host ATM Research Platform
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* ===================================
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*
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*
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* This Host ATM Research Platform ("HARP") file (the "Software") is
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* made available by Network Computing Services, Inc. ("NetworkCS")
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* "AS IS". NetworkCS does not provide maintenance, improvements or
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* support of any kind.
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*
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* NETWORKCS MAKES NO WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED,
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* INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE, AS TO ANY ELEMENT OF THE
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* SOFTWARE OR ANY SUPPORT PROVIDED IN CONNECTION WITH THIS SOFTWARE.
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* In no event shall NetworkCS be responsible for any damages, including
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* but not limited to consequential damages, arising from or relating to
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* any use of the Software or related support.
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*
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* Copyright 1994-1998 Network Computing Services, Inc.
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*
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* Copies of this Software may be made, however, the above copyright
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* notice must be reproduced on all copies.
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*
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1999-08-28 01:08:13 +00:00
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* @(#) $FreeBSD$
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1998-09-15 08:23:17 +00:00
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*
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*/
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/*
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* Efficient ENI Adapter Support
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* -----------------------------
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*
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* Defines for SUNI chip
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*
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*/
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#ifndef _ENI_ENI_SUNI_H
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#define _ENI_ENI_SUNI_H
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/*
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* Interrupt bits in SUNI Master Interrupt Status Reg
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*/
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#define SUNI_RSOPI 0x01
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#define SUNI_RLOPI 0x02
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#define SUNI_RPOPI 0x04
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#define SUNI_RACPI 0x08
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#define SUNI_TACPI 0x10
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#define SUNI_RDOOLI 0x20
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#define SUNI_LCDI 0x40
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#define SUNI_TROOLI 0x80
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/*
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* SUNI Register numbers
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*/
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#define SUNI_MASTER_REG 0x00 /* Master reset and ID */
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#define SUNI_IS_REG 0x02 /* Master Interrupt Status */
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#define SUNI_CLOCK_REG 0x06 /* Clock synth/control/status */
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#define SUNI_RSOP_REG 0x10 /* RSOP control/Interrupt Status */
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#define SUNI_SECT_BIP_REG 0x12
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#define SUNI_RLOP_REG 0x18 /* RLOP control/Interrupt Status */
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#define SUNI_LINE_BIP_REG 0x1A
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#define SUNI_LINE_FEBE_REG 0x1D
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#define SUNI_RPOP_IS_REG 0x31 /* RPOP Interrupt Status */
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#define SUNI_PATH_BIP_REG 0x38
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#define SUNI_PATH_FEBE_REG 0x3A
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#define SUNI_RACP_REG 0x50 /* RACP control/status */
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#define SUNI_HECS_REG 0x54
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#define SUNI_UHECS_REG 0x55
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#define SUNI_TACP_REG 0x60 /* TACP control/status */
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/*
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* Delay timer to allow SUNI statistic registers to load
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*/
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#define SUNI_DELAY 10
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#endif /* _ENI_ENI_SUNI_H */
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