From 0dd873372aef629e0aaf085307efd6d182d28cc6 Mon Sep 17 00:00:00 2001 From: "Jayachandran C." Date: Thu, 13 Jan 2011 06:48:43 +0000 Subject: [PATCH] Cleanup physical address and PTE types on MIPS. 1. Use vm_paddr_t for physical addresses. There are a few places in the MIPS platform code where vm_offset_t is used for physical addresses, change these to use vm_paddr_t: - phys_avail[], physmem_desc[] arrays - pmap_mapdev(), page_is_managed(), is_cacheable_mem() pmap_map() args - local variables of various pmap functions 2. Change init_pte_prot() return from int to pt_entry_t, as this can be 64 bit when using 64 bit TLB entries. 3. Update printing of pt_entry_t and of vm_paddr_t to use 'j' format with uintmax_t. This will be useful later if we plan to use 64bit phsical addr on 32 bit n32 compilation. Reviewed by: imp --- sys/mips/include/md_var.h | 2 +- sys/mips/include/pmap.h | 8 +++---- sys/mips/mips/machdep.c | 8 +++---- sys/mips/mips/pmap.c | 50 +++++++++++++++++---------------------- sys/mips/mips/trap.c | 20 ++++++++-------- 5 files changed, 41 insertions(+), 47 deletions(-) diff --git a/sys/mips/include/md_var.h b/sys/mips/include/md_var.h index 3e46ad3831cc..c2a61559ff1a 100644 --- a/sys/mips/include/md_var.h +++ b/sys/mips/include/md_var.h @@ -54,7 +54,7 @@ void cpu_swapin(struct proc *); uintptr_t MipsEmulateBranch(struct trapframe *, uintptr_t, int, uintptr_t); void MipsSwitchFPState(struct thread *, struct trapframe *); u_long kvtop(void *addr); -int is_cacheable_mem(vm_offset_t addr); +int is_cacheable_mem(vm_paddr_t addr); void mips_generic_reset(void); #define MIPS_DEBUG 0 diff --git a/sys/mips/include/pmap.h b/sys/mips/include/pmap.h index cdbf9bcfa52f..795de44b9f46 100644 --- a/sys/mips/include/pmap.h +++ b/sys/mips/include/pmap.h @@ -138,8 +138,8 @@ typedef struct pv_entry { * regions. */ #define PHYS_AVAIL_ENTRIES 10 -extern vm_offset_t phys_avail[PHYS_AVAIL_ENTRIES + 2]; -extern vm_offset_t physmem_desc[PHYS_AVAIL_ENTRIES + 2]; +extern vm_paddr_t phys_avail[PHYS_AVAIL_ENTRIES + 2]; +extern vm_paddr_t physmem_desc[PHYS_AVAIL_ENTRIES + 2]; extern vm_offset_t virtual_avail; extern vm_offset_t virtual_end; @@ -151,10 +151,10 @@ extern vm_paddr_t dump_avail[PHYS_AVAIL_ENTRIES + 2]; #define pmap_page_set_memattr(m, ma) (void)0 void pmap_bootstrap(void); -void *pmap_mapdev(vm_offset_t, vm_size_t); +void *pmap_mapdev(vm_paddr_t, vm_size_t); void pmap_unmapdev(vm_offset_t, vm_size_t); vm_offset_t pmap_steal_memory(vm_size_t size); -int page_is_managed(vm_offset_t pa); +int page_is_managed(vm_paddr_t pa); void pmap_kenter(vm_offset_t va, vm_paddr_t pa); void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int attr); void pmap_kremove(vm_offset_t va); diff --git a/sys/mips/mips/machdep.c b/sys/mips/mips/machdep.c index a2c6b0f434a3..0b4468cba012 100644 --- a/sys/mips/mips/machdep.c +++ b/sys/mips/mips/machdep.c @@ -136,8 +136,8 @@ char pcpu_space[MAXCPU][PAGE_SIZE * 2] \ struct pcpu *pcpup = (struct pcpu *)pcpu_space; -vm_offset_t phys_avail[PHYS_AVAIL_ENTRIES + 2]; -vm_offset_t physmem_desc[PHYS_AVAIL_ENTRIES + 2]; +vm_paddr_t phys_avail[PHYS_AVAIL_ENTRIES + 2]; +vm_paddr_t physmem_desc[PHYS_AVAIL_ENTRIES + 2]; vm_paddr_t dump_avail[PHYS_AVAIL_ENTRIES + 2]; #ifdef UNIMPLEMENTED @@ -509,12 +509,12 @@ cpu_idle_wakeup(int cpu) } int -is_cacheable_mem(vm_offset_t addr) +is_cacheable_mem(vm_paddr_t pa) { int i; for (i = 0; physmem_desc[i + 1] != 0; i += 2) { - if (addr >= physmem_desc[i] && addr < physmem_desc[i + 1]) + if (pa >= physmem_desc[i] && pa < physmem_desc[i + 1]) return (1); } diff --git a/sys/mips/mips/pmap.c b/sys/mips/mips/pmap.c index 7b0d09b4d2cf..3cf8246a2433 100644 --- a/sys/mips/mips/pmap.c +++ b/sys/mips/mips/pmap.c @@ -119,12 +119,6 @@ __FBSDID("$FreeBSD$"); /* * Get PDEs and PTEs for user/kernel address space - * - * XXX The & for pmap_segshift() is wrong, as is the fact that it doesn't - * trim off gratuitous bits of the address space. By having the & - * there, we break defining NUSERPGTBLS below because the address space - * is defined such that it ends immediately after NPDEPG*NPTEPG*PAGE_SIZE, - * so we end up getting NUSERPGTBLS of 0. */ #define pmap_seg_index(v) (((v) >> SEGSHIFT) & (NPDEPG - 1)) #define pmap_pde_index(v) (((v) >> PDRSHIFT) & (NPDEPG - 1)) @@ -184,7 +178,7 @@ static int _pmap_unwire_pte_hold(pmap_t pmap, vm_offset_t va, vm_page_t m); static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t); -static int init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot); +static pt_entry_t init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot); #ifdef SMP static void pmap_invalidate_page_action(void *arg); @@ -888,7 +882,7 @@ pmap_kremove(vm_offset_t va) * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit. */ vm_offset_t -pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) +pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) { vm_offset_t va, sva; @@ -1562,7 +1556,7 @@ pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va) { pt_entry_t oldpte; vm_page_t m; - vm_offset_t pa; + vm_paddr_t pa; mtx_assert(&vm_page_queue_mtx, MA_OWNED); PMAP_LOCK_ASSERT(pmap, MA_OWNED); @@ -1583,8 +1577,8 @@ pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va) m = PHYS_TO_VM_PAGE(pa); if (pte_test(&oldpte, PTE_D)) { KASSERT(!pte_test(&oldpte, PTE_RO), - ("%s: modified page not writable: va: %p, pte: 0x%x", - __func__, (void *)va, oldpte)); + ("%s: modified page not writable: va: %p, pte: %#jx", + __func__, (void *)va, (uintmax_t)oldpte)); vm_page_dirty(m); } if (m->md.pv_flags & PV_TABLE_REF) @@ -1742,8 +1736,8 @@ pmap_remove_all(vm_page_t m) */ if (pte_test(&tpte, PTE_D)) { KASSERT(!pte_test(&tpte, PTE_RO), - ("%s: modified page not writable: va: %p, pte: 0x%x", - __func__, (void *)pv->pv_va, tpte)); + ("%s: modified page not writable: va: %p, pte: %#jx", + __func__, (void *)pv->pv_va, (uintmax_t)tpte)); vm_page_dirty(m); } pmap_invalidate_page(pv->pv_pmap, pv->pv_va); @@ -1850,12 +1844,12 @@ void pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, vm_prot_t prot, boolean_t wired) { - vm_offset_t pa, opa; + vm_paddr_t pa, opa; pt_entry_t *pte; pt_entry_t origpte, newpte; pv_entry_t pv; vm_page_t mpte, om; - int rw = 0; + pt_entry_t rw = 0; if (pmap == NULL) return; @@ -1908,8 +1902,8 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, pmap->pm_stats.wired_count--; KASSERT(!pte_test(&origpte, PTE_D | PTE_RO), - ("%s: modified page not writable: va: %p, pte: 0x%x", - __func__, (void *)va, origpte)); + ("%s: modified page not writable: va: %p, pte: %#jx", + __func__, (void *)va, (uintmax_t)origpte)); /* * Remove extra pte reference @@ -2011,7 +2005,7 @@ pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, if (pte_test(&origpte, PTE_D)) { KASSERT(!pte_test(&origpte, PTE_RO), ("pmap_enter: modified page not writable:" - " va: %p, pte: 0x%x", (void *)va, origpte)); + " va: %p, pte: %#jx", (void *)va, (uintmax_t)origpte)); if (page_is_managed(opa)) vm_page_dirty(om); } @@ -2063,7 +2057,7 @@ pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot, vm_page_t mpte) { pt_entry_t *pte; - vm_offset_t pa; + vm_paddr_t pa; KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, @@ -2519,7 +2513,7 @@ pmap_remove_pages(pmap_t pmap) m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(tpte)); KASSERT(m != NULL, - ("pmap_remove_pages: bad tpte %x", tpte)); + ("pmap_remove_pages: bad tpte %#jx", (uintmax_t)tpte)); pv->pv_pmap->pm_stats.resident_count--; @@ -2848,7 +2842,7 @@ pmap_clear_reference(vm_page_t m) * Use XKPHYS uncached for 64 bit, and KSEG1 where possible for 32 bit. */ void * -pmap_mapdev(vm_offset_t pa, vm_size_t size) +pmap_mapdev(vm_paddr_t pa, vm_size_t size) { vm_offset_t va, tmpva, offset; @@ -2903,7 +2897,7 @@ int pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) { pt_entry_t *ptep, pte; - vm_offset_t pa; + vm_paddr_t pa; vm_page_t m; int val; boolean_t managed; @@ -3066,8 +3060,8 @@ DB_SHOW_COMMAND(ptable, ddb_pid_dump) continue; pa = TLBLO_PTE_TO_PA(pte); va = ((u_long)i << SEGSHIFT) | (j << PDRSHIFT) | (k << PAGE_SHIFT); - db_printf("\t\t[%04d] va: %p pte: %8x pa:%lx\n", - k, (void *)va, pte, (u_long)pa); + db_printf("\t\t[%04d] va: %p pte: %8jx pa:%jx\n", + k, (void *)va, (uintmax_t)pte, (uintmax_t)pa); } } } @@ -3155,7 +3149,7 @@ pmap_asid_alloc(pmap) } int -page_is_managed(vm_offset_t pa) +page_is_managed(vm_paddr_t pa) { vm_offset_t pgnum = mips_btop(pa); @@ -3171,10 +3165,10 @@ page_is_managed(vm_offset_t pa) return (0); } -static int +static pt_entry_t init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot) { - int rw; + pt_entry_t rw; if (!(prot & VM_PROT_WRITE)) rw = PTE_V | PTE_RO | PTE_C_CACHE; @@ -3203,7 +3197,7 @@ pmap_emulate_modified(pmap_t pmap, vm_offset_t va) { vm_page_t m; pt_entry_t *pte; - vm_offset_t pa; + vm_paddr_t pa; PMAP_LOCK(pmap); pte = pmap_pte(pmap, va); diff --git a/sys/mips/mips/trap.c b/sys/mips/mips/trap.c index 009db7caed60..35b8030aeb7a 100644 --- a/sys/mips/mips/trap.c +++ b/sys/mips/mips/trap.c @@ -1276,8 +1276,8 @@ log_illegal_instruction(const char *msg, struct trapframe *frame) if (!(pc & 3) && useracc((caddr_t)(intptr_t)pc, sizeof(int) * 4, VM_PROT_READ)) { /* dump page table entry for faulting instruction */ - log(LOG_ERR, "Page table info for pc address %#jx: pde = %p, pte = %#x\n", - (intmax_t)pc, (void *)(intptr_t)*pdep, ptep ? *ptep : 0); + log(LOG_ERR, "Page table info for pc address %#jx: pde = %p, pte = %#jx\n", + (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0)); addr = (unsigned int *)(intptr_t)pc; log(LOG_ERR, "Dumping 4 words starting at pc address %p: \n", @@ -1285,8 +1285,8 @@ log_illegal_instruction(const char *msg, struct trapframe *frame) log(LOG_ERR, "%08x %08x %08x %08x\n", addr[0], addr[1], addr[2], addr[3]); } else { - log(LOG_ERR, "pc address %#jx is inaccessible, pde = %p, pte = %#x\n", - (intmax_t)pc, (void *)(intptr_t)*pdep, ptep ? *ptep : 0); + log(LOG_ERR, "pc address %#jx is inaccessible, pde = %p, pte = %#jx\n", + (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0)); } } @@ -1340,8 +1340,8 @@ log_bad_page_fault(char *msg, struct trapframe *frame, int trap_type) (trap_type != T_BUS_ERR_IFETCH) && useracc((caddr_t)(intptr_t)pc, sizeof(int) * 4, VM_PROT_READ)) { /* dump page table entry for faulting instruction */ - log(LOG_ERR, "Page table info for pc address %#jx: pde = %p, pte = %#x\n", - (intmax_t)pc, (void *)(intptr_t)*pdep, ptep ? *ptep : 0); + log(LOG_ERR, "Page table info for pc address %#jx: pde = %p, pte = %#jx\n", + (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0)); addr = (unsigned int *)(intptr_t)pc; log(LOG_ERR, "Dumping 4 words starting at pc address %p: \n", @@ -1349,13 +1349,13 @@ log_bad_page_fault(char *msg, struct trapframe *frame, int trap_type) log(LOG_ERR, "%08x %08x %08x %08x\n", addr[0], addr[1], addr[2], addr[3]); } else { - log(LOG_ERR, "pc address %#jx is inaccessible, pde = %p, pte = %#x\n", - (intmax_t)pc, (void *)(intptr_t)*pdep, ptep ? *ptep : 0); + log(LOG_ERR, "pc address %#jx is inaccessible, pde = %p, pte = %#jx\n", + (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0)); } get_mapping_info((vm_offset_t)frame->badvaddr, &pdep, &ptep); - log(LOG_ERR, "Page table info for bad address %#jx: pde = %p, pte = %#x\n", - (intmax_t)frame->badvaddr, (void *)(intptr_t)*pdep, ptep ? *ptep : 0); + log(LOG_ERR, "Page table info for bad address %#jx: pde = %p, pte = %#jx\n", + (intmax_t)frame->badvaddr, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0)); }