From 1b60bbfe653fb567478ffa8e9fb7478bb8fa3cc6 Mon Sep 17 00:00:00 2001
From: "Stephen J. Kiernan" <stevek@FreeBSD.org>
Date: Wed, 3 Apr 2024 19:38:56 -0400
Subject: [PATCH] arm64: Separate serror handler to EL1H and EL0 versions.

In order to ensure the registers are saved and restored properly for
the exception level, we need separate handlers serror at each of
EL1H and EL0.

Reviewed by:	andrew
Differential Revision:	https://reviews.freebsd.org/D44630
---
 sys/arm64/arm64/exception.S | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/sys/arm64/arm64/exception.S b/sys/arm64/arm64/exception.S
index bab71fed4453..41d7e7f7ae1f 100644
--- a/sys/arm64/arm64/exception.S
+++ b/sys/arm64/arm64/exception.S
@@ -236,6 +236,15 @@ ENTRY(handle_el1h_irq)
 	ERET
 END(handle_el1h_irq)
 
+ENTRY(handle_el1h_serror)
+	save_registers 1
+	KMSAN_ENTER
+	mov	x0, sp
+1:	bl	do_serror
+	b	1b
+	KMSAN_LEAVE
+END(handle_el1h_serror)
+
 ENTRY(handle_el0_sync)
 	save_registers 0
 	KMSAN_ENTER
@@ -260,14 +269,14 @@ ENTRY(handle_el0_irq)
 	ERET
 END(handle_el0_irq)
 
-ENTRY(handle_serror)
+ENTRY(handle_el0_serror)
 	save_registers 0
 	KMSAN_ENTER
 	mov	x0, sp
 1:	bl	do_serror
 	b	1b
 	KMSAN_LEAVE
-END(handle_serror)
+END(handle_el0_serror)
 
 ENTRY(handle_empty_exception)
 	save_registers 0
@@ -303,15 +312,15 @@ exception_vectors:
 	vector el1h_sync 1	/* Synchronous EL1h */
 	vector el1h_irq 1	/* IRQ EL1h */
 	vempty 1		/* FIQ EL1h */
-	vector serror 1		/* Error EL1h */
+	vector el1h_serror 1	/* Error EL1h */
 
 	vector el0_sync 0	/* Synchronous 64-bit EL0 */
 	vector el0_irq 0	/* IRQ 64-bit EL0 */
 	vempty 0		/* FIQ 64-bit EL0 */
-	vector serror 0		/* Error 64-bit EL0 */
+	vector el0_serror 0	/* Error 64-bit EL0 */
 
 	vector el0_sync 0	/* Synchronous 32-bit EL0 */
 	vector el0_irq 0	/* IRQ 32-bit EL0 */
 	vempty 0		/* FIQ 32-bit EL0 */
-	vector serror 0		/* Error 32-bit EL0 */
+	vector el0_serror 0	/* Error 32-bit EL0 */