From 1de8c69de77368f9b17cd8a94e8fafcb0cfd776f Mon Sep 17 00:00:00 2001
From: Navdeep Parhar <np@FreeBSD.org>
Date: Thu, 15 Dec 2016 02:05:29 +0000
Subject: [PATCH] cxgbe(4): Deal with compressed error vectors.

MFC after:	3 days
Sponsored by:	Chelsio Communications
---
 sys/dev/cxgbe/common/common.h |  2 +-
 sys/dev/cxgbe/common/t4_hw.c  | 11 ++++++++---
 sys/dev/cxgbe/common/t4_msg.h |  2 +-
 sys/dev/cxgbe/t4_sge.c        |  2 +-
 4 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/sys/dev/cxgbe/common/common.h b/sys/dev/cxgbe/common/common.h
index f2901f5e4221..2e1f8a98fca3 100644
--- a/sys/dev/cxgbe/common/common.h
+++ b/sys/dev/cxgbe/common/common.h
@@ -227,7 +227,7 @@ struct tp_params {
 
 	uint32_t vlan_pri_map;
 	uint32_t ingress_config;
-	uint32_t rx_pkt_encap;
+	__be16 err_vec_mask;
 
 	int8_t fcoe_shift;
 	int8_t port_shift;
diff --git a/sys/dev/cxgbe/common/t4_hw.c b/sys/dev/cxgbe/common/t4_hw.c
index 381ca2a3a70f..3f49460a7988 100644
--- a/sys/dev/cxgbe/common/t4_hw.c
+++ b/sys/dev/cxgbe/common/t4_hw.c
@@ -8020,12 +8020,17 @@ int t4_init_tp_params(struct adapter *adap)
 	read_filter_mode_and_ingress_config(adap);
 
 	/*
-	 * For T6, cache the adapter's compressed error vector
-	 * and passing outer header info for encapsulated packets.
+	 * Cache a mask of the bits that represent the error vector portion of
+	 * rx_pkt.err_vec.  T6+ can use a compressed error vector to make room
+	 * for information about outer encapsulation (GENEVE/VXLAN/NVGRE).
 	 */
+	tpp->err_vec_mask = htobe16(0xffff);
 	if (chip_id(adap) > CHELSIO_T5) {
 		v = t4_read_reg(adap, A_TP_OUT_CONFIG);
-		tpp->rx_pkt_encap = (v & F_CRXPKTENC) ? 1 : 0;
+		if (v & F_CRXPKTENC) {
+			tpp->err_vec_mask =
+			    htobe16(V_T6_COMPR_RXERR_VEC(M_T6_COMPR_RXERR_VEC));
+		}
 	}
 
 	return 0;
diff --git a/sys/dev/cxgbe/common/t4_msg.h b/sys/dev/cxgbe/common/t4_msg.h
index ea48fc6dde9d..3264bac65a87 100644
--- a/sys/dev/cxgbe/common/t4_msg.h
+++ b/sys/dev/cxgbe/common/t4_msg.h
@@ -2014,7 +2014,7 @@ struct cpl_rx_pkt {
 
 #define S_T6_COMPR_RXERR_VEC    0
 #define M_T6_COMPR_RXERR_VEC    0x3F
-#define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_LEN)
+#define V_T6_COMPR_RXERR_VEC(x) ((x) << S_T6_COMPR_RXERR_VEC)
 #define G_T6_COMPR_RXERR_VEC(x) \
 		(((x) >> S_T6_COMPR_RXERR_VEC) & M_T6_COMPR_RXERR_VEC)
 
diff --git a/sys/dev/cxgbe/t4_sge.c b/sys/dev/cxgbe/t4_sge.c
index 88c2e91bc7ae..bdfaa4db2b00 100644
--- a/sys/dev/cxgbe/t4_sge.c
+++ b/sys/dev/cxgbe/t4_sge.c
@@ -1808,7 +1808,7 @@ t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
 	M_HASHTYPE_SET(m0, sw_hashtype[rss->hash_type][rss->ipv6]);
 	m0->m_pkthdr.flowid = be32toh(rss->hash_val);
 
-	if (cpl->csum_calc && !cpl->err_vec) {
+	if (cpl->csum_calc && !(cpl->err_vec & sc->params.tp.err_vec_mask)) {
 		if (ifp->if_capenable & IFCAP_RXCSUM &&
 		    cpl->l2info & htobe32(F_RXF_IP)) {
 			m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |