mirror of
https://git.FreeBSD.org/src.git
synced 2024-12-01 08:27:59 +00:00
Add generic support for chipsets that say they support AHCI. This should catch new chipsets that we dont know but that we should support.
Add a few new PCI id's. Misc cleanups.
This commit is contained in:
Søren Schmidt
parent
f9721b43ed
commit
200c7605c8
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=173734
@ -155,7 +155,7 @@
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#define ATA_AHCI_GHC 0x04
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#define ATA_AHCI_GHC_AE 0x80000000
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#define ATA_AHCI_GHC_IE 0x00000002
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#define ATA_AHCI_GHC_HR 0x80000001
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#define ATA_AHCI_GHC_HR 0x00000001
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#define ATA_AHCI_IS 0x08
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#define ATA_AHCI_PI 0x0c
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@ -176,6 +176,7 @@ static void ata_via_reset(device_t dev);
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static void ata_via_setmode(device_t dev, int mode);
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static void ata_via_southbridge_fixup(device_t dev);
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static void ata_via_family_setmode(device_t dev, int mode);
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static void ata_set_desc(device_t dev);
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static struct ata_chip_id *ata_match_chip(device_t dev, struct ata_chip_id *index);
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static struct ata_chip_id *ata_find_chip(device_t dev, struct ata_chip_id *index, int slot);
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static int ata_setup_interrupt(device_t dev);
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@ -193,8 +194,10 @@ int
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ata_generic_ident(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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char buffer[64];
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device_set_desc(dev, "GENERIC ATA controller");
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sprintf(buffer, "%s ATA controller", ata_pcivendor2str(dev));
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device_set_desc(dev, buffer);
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ctlr->chipinit = ata_generic_chipinit;
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return 0;
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}
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@ -447,15 +450,48 @@ ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis)
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/*
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* AHCI v1.x compliant SATA chipset support functions
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*/
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int
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ata_ahci_ident(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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char buffer[64];
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/* is this PCI device flagged as an AHCI compliant chip ? */
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if (pci_read_config(dev, PCIR_PROGIF, 1) != PCIP_STORAGE_SATA_AHCI_1_0)
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return ENXIO;
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sprintf(buffer, "%s AHCI controller", ata_pcivendor2str(dev));
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device_set_desc_copy(dev, buffer);
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ctlr->chipinit = ata_ahci_chipinit;
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return 0;
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}
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static int
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ata_ahci_chipinit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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u_int32_t version;
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/* if we have a memory BAR(5) we are likely on an AHCI part */
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ctlr->r_type2 = SYS_RES_MEMORY;
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ctlr->r_rid2 = PCIR_BAR(5);
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if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
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&ctlr->r_rid2, RF_ACTIVE)))
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return ENXIO;
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/* setup interrupt delivery if not done allready by a vendor driver */
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if (!ctlr->r_irq) {
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if (ata_setup_interrupt(dev))
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return ENXIO;
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}
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else
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device_printf(dev, "AHCI called from vendor specific driver\n");
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/* enable AHCI mode */
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
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/* reset AHCI controller */
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
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ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_HR);
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_HR);
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DELAY(1000000);
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if (ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) {
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bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
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@ -463,9 +499,8 @@ ata_ahci_chipinit(device_t dev)
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return ENXIO;
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}
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/* enable AHCI mode */
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
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ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_AE);
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/* reenable AHCI mode */
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ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
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/* get the number of HW channels */
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ctlr->channels =
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@ -830,7 +865,6 @@ int
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ata_acard_ident(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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struct ata_chip_id *idx;
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static struct ata_chip_id ids[] =
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{{ ATA_ATP850R, 0, ATPOLD, 0x00, ATA_UDMA2, "ATP850" },
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{ ATA_ATP860A, 0, 0, 0x00, ATA_UDMA4, "ATP860A" },
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@ -838,15 +872,11 @@ ata_acard_ident(device_t dev)
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{ ATA_ATP865A, 0, 0, 0x00, ATA_UDMA6, "ATP865A" },
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{ ATA_ATP865R, 0, 0, 0x00, ATA_UDMA6, "ATP865R" },
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{ 0, 0, 0, 0, 0, 0}};
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char buffer[64];
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if (!(idx = ata_match_chip(dev, ids)))
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if (!(ctlr->chip = ata_match_chip(dev, ids)))
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return ENXIO;
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sprintf(buffer, "Acard %s %s controller",
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idx->text, ata_mode2str(idx->max_dma));
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device_set_desc_copy(dev, buffer);
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ctlr->chip = idx;
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ata_set_desc(dev);
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ctlr->chipinit = ata_acard_chipinit;
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return 0;
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}
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@ -994,7 +1024,6 @@ int
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ata_ali_ident(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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struct ata_chip_id *idx;
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static struct ata_chip_id ids[] =
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{{ ATA_ALI_5289, 0x00, 2, ALISATA, ATA_SA150, "M5289" },
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{ ATA_ALI_5288, 0x00, 4, ALISATA, ATA_SA300, "M5288" },
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@ -1006,15 +1035,11 @@ ata_ali_ident(device_t dev)
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{ ATA_ALI_5229, 0x20, 0, ALIOLD, ATA_UDMA2, "M5229" },
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{ ATA_ALI_5229, 0x00, 0, ALIOLD, ATA_WDMA2, "M5229" },
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{ 0, 0, 0, 0, 0, 0}};
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char buffer[64];
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if (!(idx = ata_match_chip(dev, ids)))
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if (!(ctlr->chip = ata_match_chip(dev, ids)))
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return ENXIO;
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sprintf(buffer, "AcerLabs %s %s controller",
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idx->text, ata_mode2str(idx->max_dma));
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device_set_desc_copy(dev, buffer);
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ctlr->chip = idx;
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ata_set_desc(dev);
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ctlr->chipinit = ata_ali_chipinit;
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return 0;
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}
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@ -1033,15 +1058,10 @@ ata_ali_chipinit(device_t dev)
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ctlr->allocate = ata_ali_sata_allocate;
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ctlr->setmode = ata_sata_setmode;
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/* if we have a memory resource we can likely do AHCI */
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ctlr->r_type2 = SYS_RES_MEMORY;
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ctlr->r_rid2 = PCIR_BAR(5);
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/* AHCI mode is correctly supported only on the ALi 5288. */
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if ((ctlr->chip->chipid == ATA_ALI_5288) &&
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(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
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&ctlr->r_rid2, RF_ACTIVE)))
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return ata_ahci_chipinit(dev);
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(ata_ahci_chipinit(dev) != ENXIO))
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return 0;
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/* enable PCI interrupt */
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pci_write_config(dev, PCIR_COMMAND,
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@ -1241,7 +1261,6 @@ int
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ata_amd_ident(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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struct ata_chip_id *idx;
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static struct ata_chip_id ids[] =
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{{ ATA_AMD756, 0x00, AMDNVIDIA, 0x00, ATA_UDMA4, "756" },
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{ ATA_AMD766, 0x00, AMDNVIDIA, AMDCABLE|AMDBUG, ATA_UDMA5, "766" },
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@ -1249,15 +1268,11 @@ ata_amd_ident(device_t dev)
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{ ATA_AMD8111, 0x00, AMDNVIDIA, AMDCABLE, ATA_UDMA6, "8111" },
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{ ATA_AMD5536, 0x00, AMDNVIDIA, 0x00, ATA_UDMA5, "CS5536" },
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{ 0, 0, 0, 0, 0, 0}};
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char buffer[64];
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if (!(idx = ata_match_chip(dev, ids)))
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if (!(ctlr->chip = ata_match_chip(dev, ids)))
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return ENXIO;
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sprintf(buffer, "AMD %s %s controller",
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idx->text, ata_mode2str(idx->max_dma));
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device_set_desc_copy(dev, buffer);
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ctlr->chip = idx;
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ata_set_desc(dev);
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ctlr->chipinit = ata_amd_chipinit;
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return 0;
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}
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@ -1288,24 +1303,21 @@ int
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ata_ati_ident(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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struct ata_chip_id *idx;
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static struct ata_chip_id ids[] =
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{{ ATA_ATI_IXP200, 0x00, 0, 0, ATA_UDMA5, "IXP200" },
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{ ATA_ATI_IXP300, 0x00, 0, 0, ATA_UDMA6, "IXP300" },
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{ ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" },
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{ ATA_ATI_IXP300_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP300" },
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{ ATA_ATI_IXP400, 0x00, 0, 0, ATA_UDMA6, "IXP400" },
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{ ATA_ATI_IXP400_S1, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
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{ ATA_ATI_IXP400_S2, 0x00, SIIMEMIO, 0, ATA_SA150, "IXP400" },
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{ ATA_ATI_IXP600, 0x00, 0, 0, ATA_UDMA6, "IXP600" },
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{ ATA_ATI_IXP700, 0x00, 0, 0, ATA_UDMA6, "IXP700" },
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{ 0, 0, 0, 0, 0, 0}};
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char buffer[64];
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if (!(idx = ata_match_chip(dev, ids)))
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if (!(ctlr->chip = ata_match_chip(dev, ids)))
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return ENXIO;
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sprintf(buffer, "ATI %s %s controller",
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idx->text, ata_mode2str(idx->max_dma));
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device_set_desc_copy(dev, buffer);
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ctlr->chip = idx;
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ata_set_desc(dev);
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/* the ATI SATA controller is actually a SiI 3112 controller*/
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if (ctlr->chip->cfg1 & SIIMEMIO)
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@ -1323,6 +1335,11 @@ ata_ati_chipinit(device_t dev)
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if (ata_setup_interrupt(dev))
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return ENXIO;
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/* IXP600 & IXP700 only have 1 PATA channel */
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if ((ctlr->chip->chipid == ATA_ATI_IXP600) ||
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(ctlr->chip->chipid == ATA_ATI_IXP700))
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ctlr->channels = 1;
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ctlr->setmode = ata_ati_setmode;
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return 0;
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}
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@ -1697,7 +1714,6 @@ int
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ata_intel_ident(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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struct ata_chip_id *idx;
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static struct ata_chip_id ids[] =
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{{ ATA_I82371FB, 0, 0, 0x00, ATA_WDMA2, "PIIX" },
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{ ATA_I82371SB, 0, 0, 0x00, ATA_WDMA2, "PIIX3" },
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@ -1749,15 +1765,11 @@ ata_intel_ident(device_t dev)
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{ ATA_I82801IB_AH6, 0, AHCI, 0x00, ATA_SA300, "ICH9" },
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{ ATA_I31244, 0, 0, 0x00, ATA_SA150, "31244" },
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{ 0, 0, 0, 0, 0, 0}};
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char buffer[64];
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if (!(idx = ata_match_chip(dev, ids)))
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if (!(ctlr->chip = ata_match_chip(dev, ids)))
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return ENXIO;
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sprintf(buffer, "Intel %s %s controller",
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idx->text, ata_mode2str(idx->max_dma));
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device_set_desc_copy(dev, buffer);
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ctlr->chip = idx;
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ata_set_desc(dev);
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ctlr->chipinit = ata_intel_chipinit;
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return 0;
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}
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@ -1806,18 +1818,14 @@ ata_intel_chipinit(device_t dev)
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ctlr->reset = ata_intel_reset;
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/*
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* if we have AHCI capability and BAR(5) as a memory resource
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* and AHCI or RAID mode enabled in BIOS we go for AHCI mode
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* if we have AHCI capability and AHCI or RAID mode enabled
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* in BIOS we try for AHCI mode
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*/
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if ((ctlr->chip->cfg1 == AHCI) &&
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(pci_read_config(dev, 0x90, 1) & 0xc0)) {
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ctlr->r_type2 = SYS_RES_MEMORY;
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ctlr->r_rid2 = PCIR_BAR(5);
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if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
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&ctlr->r_rid2,
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RF_ACTIVE)))
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return ata_ahci_chipinit(dev);
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}
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(pci_read_config(dev, 0x90, 1) & 0xc0) &&
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(ata_ahci_chipinit(dev) != ENXIO))
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return 0;
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ctlr->setmode = ata_sata_setmode;
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/* enable PCI interrupt */
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@ -2063,20 +2071,15 @@ int
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ata_ite_ident(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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struct ata_chip_id *idx;
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static struct ata_chip_id ids[] =
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{{ ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
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{ ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" },
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{ 0, 0, 0, 0, 0, 0}};
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char buffer[64];
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if (!(idx = ata_match_chip(dev, ids)))
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if (!(ctlr->chip = ata_match_chip(dev, ids)))
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return ENXIO;
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sprintf(buffer, "ITE %s %s controller",
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idx->text, ata_mode2str(idx->max_dma));
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device_set_desc_copy(dev, buffer);
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ctlr->chip = idx;
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ata_set_desc(dev);
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ctlr->chipinit = ata_ite_chipinit;
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return 0;
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}
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@ -2207,12 +2210,9 @@ ata_jmicron_chipinit(device_t dev)
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/* do we have multiple PCI functions ? */
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if (pci_read_config(dev, 0xdf, 1) & 0x40) {
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/* if we have a memory BAR(5) we are on the AHCI part */
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ctlr->r_type2 = SYS_RES_MEMORY;
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ctlr->r_rid2 = PCIR_BAR(5);
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if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
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&ctlr->r_rid2, RF_ACTIVE)))
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return ata_ahci_chipinit(dev);
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/* are we on the AHCI part ? */
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if (ata_ahci_chipinit(dev) != ENXIO)
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return 0;
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/* otherwise we are on the PATA part */
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ctlr->allocate = ata_pci_allocate;
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@ -2226,13 +2226,8 @@ ata_jmicron_chipinit(device_t dev)
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pci_write_config(dev, 0x40, 0x80c0a131, 4);
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pci_write_config(dev, 0x80, 0x01200000, 4);
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ctlr->r_type2 = SYS_RES_MEMORY;
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ctlr->r_rid2 = PCIR_BAR(5);
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if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
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&ctlr->r_rid2, RF_ACTIVE))){
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if ((error = ata_ahci_chipinit(dev)))
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return error;
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}
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if ((error = ata_ahci_chipinit(dev)))
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return error;
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ctlr->allocate = ata_jmicron_allocate;
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ctlr->reset = ata_jmicron_reset;
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@ -2335,7 +2330,6 @@ int
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ata_marvell_ident(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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struct ata_chip_id *idx;
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static struct ata_chip_id ids[] =
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{{ ATA_M88SX5040, 0, 4, MV50XX, ATA_SA150, "88SX5040" },
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{ ATA_M88SX5041, 0, 4, MV50XX, ATA_SA150, "88SX5041" },
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@ -2346,15 +2340,12 @@ ata_marvell_ident(device_t dev)
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{ ATA_M88SX6101, 0, 1, MV61XX, ATA_UDMA6, "88SX6101" },
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{ ATA_M88SX6145, 0, 2, MV61XX, ATA_UDMA6, "88SX6145" },
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{ 0, 0, 0, 0, 0, 0}};
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char buffer[64];
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if (!(idx = ata_match_chip(dev, ids)))
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if (!(ctlr->chip = ata_match_chip(dev, ids)))
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return ENXIO;
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sprintf(buffer, "Marvell %s %s controller",
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idx->text, ata_mode2str(idx->max_dma));
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device_set_desc_copy(dev, buffer);
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ctlr->chip = idx;
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ata_set_desc(dev);
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switch (ctlr->chip->cfg2) {
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case MV50XX:
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case MV60XX:
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@ -2905,7 +2896,6 @@ int
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ata_nvidia_ident(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
|
||||
struct ata_chip_id *idx;
|
||||
static struct ata_chip_id ids[] =
|
||||
{{ ATA_NFORCE1, 0, AMDNVIDIA, NVIDIA, ATA_UDMA5, "nForce" },
|
||||
{ ATA_NFORCE2, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce2" },
|
||||
@ -2931,16 +2921,16 @@ ata_nvidia_ident(device_t dev)
|
||||
{ ATA_NFORCE_MCP61_S1, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
|
||||
{ ATA_NFORCE_MCP61_S2, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
|
||||
{ ATA_NFORCE_MCP61_S3, 0, 0, NV4|NVQ, ATA_SA300, "nForce MCP61" },
|
||||
{ ATA_NFORCE_MCP65, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP65" },
|
||||
{ ATA_NFORCE_MCP67, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP67" },
|
||||
{ ATA_NFORCE_MCP73, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP73" },
|
||||
{ ATA_NFORCE_MCP77, 0, AMDNVIDIA, NVIDIA, ATA_UDMA6, "nForce MCP77" },
|
||||
{ 0, 0, 0, 0, 0, 0}} ;
|
||||
char buffer[64] ;
|
||||
|
||||
if (!(idx = ata_match_chip(dev, ids)))
|
||||
if (!(ctlr->chip = ata_match_chip(dev, ids)))
|
||||
return ENXIO;
|
||||
|
||||
sprintf(buffer, "nVidia %s %s controller",
|
||||
idx->text, ata_mode2str(idx->max_dma));
|
||||
device_set_desc_copy(dev, buffer);
|
||||
ctlr->chip = idx;
|
||||
ata_set_desc(dev);
|
||||
ctlr->chipinit = ata_nvidia_chipinit;
|
||||
return 0;
|
||||
}
|
||||
@ -4030,7 +4020,6 @@ int
|
||||
ata_serverworks_ident(device_t dev)
|
||||
{
|
||||
struct ata_pci_controller *ctlr = device_get_softc(dev);
|
||||
struct ata_chip_id *idx;
|
||||
static struct ata_chip_id ids[] =
|
||||
{{ ATA_ROSB4, 0x00, SWKS33, 0, ATA_UDMA2, "ROSB4" },
|
||||
{ ATA_CSB5, 0x92, SWKS100, 0, ATA_UDMA5, "CSB5" },
|
||||
@ -4044,15 +4033,11 @@ ata_serverworks_ident(device_t dev)
|
||||
{ ATA_FRODO4, 0x00, SWKSMIO, 4, ATA_SA150, "Frodo4" },
|
||||
{ ATA_FRODO8, 0x00, SWKSMIO, 8, ATA_SA150, "Frodo8" },
|
||||
{ 0, 0, 0, 0, 0, 0}};
|
||||
char buffer[64];
|
||||
|
||||
if (!(idx = ata_match_chip(dev, ids)))
|
||||
if (!(ctlr->chip = ata_match_chip(dev, ids)))
|
||||
return ENXIO;
|
||||
|
||||
sprintf(buffer, "ServerWorks %s %s controller",
|
||||
idx->text, ata_mode2str(idx->max_dma));
|
||||
device_set_desc_copy(dev, buffer);
|
||||
ctlr->chip = idx;
|
||||
ata_set_desc(dev);
|
||||
ctlr->chipinit = ata_serverworks_chipinit;
|
||||
return 0;
|
||||
}
|
||||
@ -4211,7 +4196,6 @@ int
|
||||
ata_sii_ident(device_t dev)
|
||||
{
|
||||
struct ata_pci_controller *ctlr = device_get_softc(dev);
|
||||
struct ata_chip_id *idx;
|
||||
static struct ata_chip_id ids[] =
|
||||
{{ ATA_SII3114, 0x00, SIIMEMIO, SII4CH, ATA_SA150, "SiI 3114" },
|
||||
{ ATA_SII3512, 0x02, SIIMEMIO, 0, ATA_SA150, "SiI 3512" },
|
||||
@ -4228,14 +4212,11 @@ ata_sii_ident(device_t dev)
|
||||
{ ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "CMD 646U2" },
|
||||
{ ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "CMD 646" },
|
||||
{ 0, 0, 0, 0, 0, 0}};
|
||||
char buffer[64];
|
||||
|
||||
if (!(idx = ata_match_chip(dev, ids)))
|
||||
if (!(ctlr->chip = ata_match_chip(dev, ids)))
|
||||
return ENXIO;
|
||||
|
||||
sprintf(buffer, "%s %s controller", idx->text, ata_mode2str(idx->max_dma));
|
||||
device_set_desc_copy(dev, buffer);
|
||||
ctlr->chip = idx;
|
||||
ata_set_desc(dev);
|
||||
ctlr->chipinit = ata_sii_chipinit;
|
||||
return 0;
|
||||
}
|
||||
@ -5112,7 +5093,6 @@ int
|
||||
ata_via_ident(device_t dev)
|
||||
{
|
||||
struct ata_pci_controller *ctlr = device_get_softc(dev);
|
||||
struct ata_chip_id *idx;
|
||||
static struct ata_chip_id ids[] =
|
||||
{{ ATA_VIA82C586, 0x02, VIA33, 0x00, ATA_UDMA2, "82C586B" },
|
||||
{ ATA_VIA82C586, 0x00, VIA33, 0x00, ATA_WDMA2, "82C586" },
|
||||
@ -5139,21 +5119,17 @@ ata_via_ident(device_t dev)
|
||||
{ ATA_VIA8237S, 0x00, 7, 0x00, ATA_SA150, "8237S" },
|
||||
{ ATA_VIA8251, 0x00, 0, VIAAHCI, ATA_SA300, "8251" },
|
||||
{ 0, 0, 0, 0, 0, 0 }};
|
||||
char buffer[64];
|
||||
|
||||
if (pci_get_devid(dev) == ATA_VIA82C571) {
|
||||
if (!(idx = ata_find_chip(dev, ids, -99)))
|
||||
if (!(ctlr->chip = ata_find_chip(dev, ids, -99)))
|
||||
return ENXIO;
|
||||
}
|
||||
else {
|
||||
if (!(idx = ata_match_chip(dev, new_ids)))
|
||||
if (!(ctlr->chip = ata_match_chip(dev, new_ids)))
|
||||
return ENXIO;
|
||||
}
|
||||
|
||||
sprintf(buffer, "VIA %s %s controller",
|
||||
idx->text, ata_mode2str(idx->max_dma));
|
||||
device_set_desc_copy(dev, buffer);
|
||||
ctlr->chip = idx;
|
||||
ata_set_desc(dev);
|
||||
ctlr->chipinit = ata_via_chipinit;
|
||||
return 0;
|
||||
}
|
||||
@ -5167,15 +5143,10 @@ ata_via_chipinit(device_t dev)
|
||||
return ENXIO;
|
||||
|
||||
if (ctlr->chip->max_dma >= ATA_SA150) {
|
||||
if (ctlr->chip->cfg2 == VIAAHCI) {
|
||||
ctlr->r_type2 = SYS_RES_MEMORY;
|
||||
ctlr->r_rid2 = PCIR_BAR(5);
|
||||
if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
|
||||
&ctlr->r_rid2,
|
||||
RF_ACTIVE))) {
|
||||
return ata_ahci_chipinit(dev);
|
||||
}
|
||||
}
|
||||
/* do we have AHCI capability ? */
|
||||
if ((ctlr->chip->cfg2 == VIAAHCI) && ata_ahci_chipinit(dev) != ENXIO)
|
||||
return 0;
|
||||
|
||||
ctlr->r_type2 = SYS_RES_IOPORT;
|
||||
ctlr->r_rid2 = PCIR_BAR(5);
|
||||
if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
|
||||
@ -5254,7 +5225,7 @@ ata_via_allocate(device_t dev)
|
||||
ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
|
||||
}
|
||||
ata_pci_hw(dev);
|
||||
if (ch->unit > 1)
|
||||
if (ch->unit >= 2)
|
||||
return 0;
|
||||
}
|
||||
else {
|
||||
@ -5407,6 +5378,18 @@ ata_via_family_setmode(device_t dev, int mode)
|
||||
|
||||
|
||||
/* misc functions */
|
||||
static void
|
||||
ata_set_desc(device_t dev)
|
||||
{
|
||||
struct ata_pci_controller *ctlr = device_get_softc(dev);
|
||||
char buffer[128];
|
||||
|
||||
sprintf(buffer, "%s %s %s controller",
|
||||
ata_pcivendor2str(dev), ctlr->chip->text,
|
||||
ata_mode2str(ctlr->chip->max_dma));
|
||||
device_set_desc_copy(dev, buffer);
|
||||
}
|
||||
|
||||
static struct ata_chip_id *
|
||||
ata_match_chip(device_t dev, struct ata_chip_id *index)
|
||||
{
|
||||
@ -5458,6 +5441,7 @@ ata_setup_interrupt(device_t dev)
|
||||
}
|
||||
if ((bus_setup_intr(dev, ctlr->r_irq, ATA_INTR_FLAGS, NULL,
|
||||
ata_generic_intr, ctlr, &ctlr->handle))) {
|
||||
/* SOS XXX release r_irq */
|
||||
device_printf(dev, "unable to setup interrupt\n");
|
||||
return ENXIO;
|
||||
}
|
||||
|
||||
@ -76,6 +76,13 @@ ata_pci_probe(device_t dev)
|
||||
if (pci_get_class(dev) != PCIC_STORAGE)
|
||||
return ENXIO;
|
||||
|
||||
/* if this is an AHCI chipset grab it */
|
||||
if (pci_get_subclass(dev) == PCIS_STORAGE_SATA) {
|
||||
if (!ata_ahci_ident(dev))
|
||||
return ATA_PROBE_OK;
|
||||
}
|
||||
|
||||
/* run through the vendor specific drivers */
|
||||
switch (pci_get_vendor(dev)) {
|
||||
case ATA_ACARD_ID:
|
||||
if (!ata_acard_ident(dev))
|
||||
@ -172,8 +179,7 @@ ata_pci_probe(device_t dev)
|
||||
}
|
||||
|
||||
/* unknown chipset, try generic DMA if it seems possible */
|
||||
if ((pci_get_class(dev) == PCIC_STORAGE) &&
|
||||
(pci_get_subclass(dev) == PCIS_STORAGE_IDE)) {
|
||||
if (pci_get_subclass(dev) == PCIS_STORAGE_IDE) {
|
||||
if (!ata_generic_ident(dev))
|
||||
return ATA_PROBE_OK;
|
||||
}
|
||||
@ -504,6 +510,35 @@ ata_pci_dmainit(device_t dev)
|
||||
}
|
||||
}
|
||||
|
||||
char *
|
||||
ata_pcivendor2str(device_t dev)
|
||||
{
|
||||
switch (pci_get_vendor(dev)) {
|
||||
case ATA_ACARD_ID: return "Acard";
|
||||
case ATA_ACER_LABS_ID: return "AcerLabs";
|
||||
case ATA_AMD_ID: return "AMD";
|
||||
case ATA_ATI_ID: return "ATI";
|
||||
case ATA_CYRIX_ID: return "Cyrix";
|
||||
case ATA_CYPRESS_ID: return "Cypress";
|
||||
case ATA_HIGHPOINT_ID: return "HighPoint";
|
||||
case ATA_INTEL_ID: return "Intel";
|
||||
case ATA_ITE_ID: return "ITE";
|
||||
case ATA_JMICRON_ID: return "JMicron";
|
||||
case ATA_MARVELL_ID: return "Marvell";
|
||||
case ATA_NATIONAL_ID: return "National";
|
||||
case ATA_NETCELL_ID: return "Netcell";
|
||||
case ATA_NVIDIA_ID: return "nVidia";
|
||||
case ATA_PROMISE_ID: return "Promise";
|
||||
case ATA_SERVERWORKS_ID: return "ServerWorks";
|
||||
case ATA_SILICON_IMAGE_ID: return "SiI";
|
||||
case ATA_SIS_ID: return "SiS";
|
||||
case ATA_VIA_ID: return "VIA";
|
||||
case ATA_CENATEK_ID: return "Cenatek";
|
||||
case ATA_MICRON_ID: return "Micron";
|
||||
default: return "Generic";
|
||||
}
|
||||
}
|
||||
|
||||
static device_method_t ata_pci_methods[] = {
|
||||
/* device interface */
|
||||
DEVMETHOD(device_probe, ata_pci_probe),
|
||||
|
||||
@ -99,10 +99,12 @@ struct ata_connect_task {
|
||||
#define ATA_ATI_ID 0x1002
|
||||
#define ATA_ATI_IXP200 0x43491002
|
||||
#define ATA_ATI_IXP300 0x43691002
|
||||
#define ATA_ATI_IXP400 0x43761002
|
||||
#define ATA_ATI_IXP300_S1 0x436e1002
|
||||
#define ATA_ATI_IXP400 0x43761002
|
||||
#define ATA_ATI_IXP400_S1 0x43791002
|
||||
#define ATA_ATI_IXP400_S2 0x437a1002
|
||||
#define ATA_ATI_IXP600 0x438c1002
|
||||
#define ATA_ATI_IXP700 0x439c1002
|
||||
|
||||
#define ATA_CENATEK_ID 0x16ca
|
||||
#define ATA_CENATEK_ROCKET 0x000116ca
|
||||
@ -232,6 +234,10 @@ struct ata_connect_task {
|
||||
#define ATA_NFORCE_MCP61_S1 0x03e710de
|
||||
#define ATA_NFORCE_MCP61_S2 0x03f610de
|
||||
#define ATA_NFORCE_MCP61_S3 0x03f710de
|
||||
#define ATA_NFORCE_MCP65 0x044810de
|
||||
#define ATA_NFORCE_MCP67 0x056010de
|
||||
#define ATA_NFORCE_MCP73 0x056c10de
|
||||
#define ATA_NFORCE_MCP77 0x075910de
|
||||
|
||||
#define ATA_PROMISE_ID 0x105a
|
||||
#define ATA_PDC20246 0x4d33105a
|
||||
@ -449,11 +455,13 @@ int ata_pci_setup_intr(device_t dev, device_t child, struct resource *irq, int f
|
||||
int ata_pci_allocate(device_t dev);
|
||||
void ata_pci_hw(device_t dev);
|
||||
int ata_pci_status(device_t dev);
|
||||
void ata_pci_dmainit(device_t);
|
||||
void ata_pci_dmainit(device_t dev);
|
||||
char *ata_pcivendor2str(device_t dev);
|
||||
|
||||
|
||||
/* global prototypes ata-chipset.c */
|
||||
int ata_generic_ident(device_t);
|
||||
int ata_ahci_ident(device_t);
|
||||
int ata_acard_ident(device_t);
|
||||
int ata_ali_ident(device_t);
|
||||
int ata_amd_ident(device_t);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user