From 27bbd0d3ef63d178f57eedf6e77a36223738f99f Mon Sep 17 00:00:00 2001
From: "Justin T. Gibbs" <gibbs@FreeBSD.org>
Date: Tue, 20 Mar 2001 04:37:19 +0000
Subject: [PATCH] This is an MFC candidate.

In our idle loop, use an or instruction to set PRELOADEN rather
than rewriting the contents of DMAPARAMS to DFCNTRL.  The later
may re-enable the DMA engine if the idle loop is called to complete
the preload of at least one segment when a target disconnects on
an S/G segment boundary but before we have completed fetching the
next segment.  This correts a hang, usually in message out phase,
when this situation occurs.  This bug has been here for a long
time, so the situation is rare, but not impossible to reproduce.
It only affected Ultra2/U160 controllers.

Correct a few comments.

Extra Sanity. Make sure that SCSIEN is also turned off, along with
HDMAEN, at the end of the data phase.
---
 sys/dev/aic7xxx/aic7xxx.seq | 13 ++++++-------
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/sys/dev/aic7xxx/aic7xxx.seq b/sys/dev/aic7xxx/aic7xxx.seq
index d85c89f80b08..8788e6088f9c 100644
--- a/sys/dev/aic7xxx/aic7xxx.seq
+++ b/sys/dev/aic7xxx/aic7xxx.seq
@@ -28,7 +28,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- * $Id: //depot/src/aic7xxx/aic7xxx.seq#23 $
+ * $Id: //depot/src/aic7xxx/aic7xxx.seq#24 $
  *
  * $FreeBSD$
  */
@@ -758,8 +758,8 @@ idle_sg_avail:
 		test	SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2;
 		or	SINDEX, LAST_SEG;
 		mov	SG_CACHE_PRE, SINDEX;
-		/* Load the segment by writing DFCNTRL again */
-		mov	DFCNTRL, DMAPARAMS;
+		/* Load the segment */
+		or	DFCNTRL, PRELOADEN;
 	}
 	ret;
 }
@@ -948,7 +948,7 @@ ultra2_dmafifoempty:
 		test	DFSTATUS, MREQPEND	jnz ultra2_dmafifoempty;
 ultra2_dmahalt:
 		and     DFCNTRL, ~(SCSIEN|HDMAEN);
-		test	DFCNTRL, HDMAEN jnz .;
+		test	DFCNTRL, SCSIEN|HDMAEN jnz .;
 
 		/*
 		 * If, by chance, we stopped before being able
@@ -2068,7 +2068,7 @@ dma_scb_fromhost:
 			 * latch is full.
 			 */
 			clr	A;
-			/* Wait for some data to arrive. */
+			/* Wait for at least 8 bytes of data to arrive. */
 dma_scb_hang_fifo:
 			test	DFSTATUS, FIFOQWDEMP jnz dma_scb_hang_fifo;
 dma_scb_hang_wait:
@@ -2078,8 +2078,7 @@ dma_scb_hang_wait:
 			test	DFSTATUS, HDONE	jnz dma_scb_hang_dma_done;
 			/*
 			 * The PCI module no longer intends to perform
-			 * a PCI transaction and HDONE has not come true.
-			 * We are hung.  Drain the fifo.
+			 * a PCI transaction.  Drain the fifo.
 			 */
 dma_scb_hang_empty_fifo:
 			/*