diff --git a/sys/mips/include/cpu.h b/sys/mips/include/cpu.h
index 3e939a04d7c2..84cfe305f0a4 100644
--- a/sys/mips/include/cpu.h
+++ b/sys/mips/include/cpu.h
@@ -163,11 +163,8 @@
  * The bits in the CONFIG register
  */
 #define CFG_K0_UNCACHED	2
-#if defined(CPU_SB1)
-#define CFG_K0_COHERENT	5	/* cacheable coherent */
-#else
 #define	CFG_K0_CACHED	3
-#endif
+#define	CFG_K0_MASK	0x7
 
 /*
  * The bits in the context register.
diff --git a/sys/mips/mips/locore.S b/sys/mips/mips/locore.S
index 11d9cdca96a2..44dda850f511 100644
--- a/sys/mips/mips/locore.S
+++ b/sys/mips/mips/locore.S
@@ -128,11 +128,7 @@ VECTOR(_locore, unknown)
 	mtc0	t2, COP_0_STATUS_REG
 	COP0_SYNC
 	/* Make sure KSEG0 is cached */
-#ifdef CPU_SB1
-	li	t0, CFG_K0_COHERENT
-#else
 	li	t0, CFG_K0_CACHED
-#endif
 	mtc0	t0, MIPS_COP_0_CONFIG
 	COP0_SYNC
 
diff --git a/sys/mips/sibyte/sb_machdep.c b/sys/mips/sibyte/sb_machdep.c
index 8bb265c5a668..4e4d81a8a215 100644
--- a/sys/mips/sibyte/sb_machdep.c
+++ b/sys/mips/sibyte/sb_machdep.c
@@ -230,12 +230,29 @@ platform_trap_exit(void)
 
 }
 
+static void
+kseg0_map_coherent(void)
+{
+	uint32_t config;
+	const int CFG_K0_COHERENT = 5;
+
+	config = mips_rd_config();
+	config &= ~CFG_K0_MASK;
+	config |= CFG_K0_COHERENT;
+	mips_wr_config(config);
+}
+
 void
 platform_start(__register_t a0, __register_t a1, __register_t a2,
 	       __register_t a3)
 {
 	vm_offset_t kernend;
 
+	/*
+	 * Make sure that kseg0 is mapped cacheable-coherent
+	 */
+	kseg0_map_coherent();
+
 	/* clear the BSS and SBSS segments */
 	memset(&edata, 0, (vm_offset_t)&end - (vm_offset_t)&edata);
 	kernend = round_page((vm_offset_t)&end);