From 570255d8a5777ddb5ffd0567537ce72d3538c85b Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Tue, 21 Jul 2009 08:38:45 +0000 Subject: [PATCH] Do not use OCP85XX_LBC_OFF twice when accessing LBC registers on MPC85XX. It turns LBC control registers were not programmed correctly on MPC85XX. We were accessing bogus addresses as the base offset (OCP85XX_LBC_OFF) was erroneously added during offset calculations. Effectively the state of LBC control registers was not altered by the kernel initialization code, but everything worked as long as we coincided to use the same settings (LBC decode windows) as firmware has initialized. Submitted by: Lukasz Wojcik Reviewed by: marcel Approved by: re (kensmith) Obtained from: Semihalf --- sys/powerpc/mpc85xx/lbc.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/sys/powerpc/mpc85xx/lbc.h b/sys/powerpc/mpc85xx/lbc.h index 24e741a67908..c5d19e2aa7ac 100644 --- a/sys/powerpc/mpc85xx/lbc.h +++ b/sys/powerpc/mpc85xx/lbc.h @@ -39,10 +39,10 @@ #define LBC_DEVTYPE_RTC 2 /* Local access registers */ -#define LBC85XX_BR(n) (OCP85XX_LBC_OFF + (8 * n)) -#define LBC85XX_OR(n) (OCP85XX_LBC_OFF + 4 + (8 * n)) -#define LBC85XX_LBCR (OCP85XX_LBC_OFF + 0xd0) -#define LBC85XX_LCRR (OCP85XX_LBC_OFF + 0xd4) +#define LBC85XX_BR(n) (8 * n) +#define LBC85XX_OR(n) (4 + (8 * n)) +#define LBC85XX_LBCR (0xd0) +#define LBC85XX_LCRR (0xd4) /* LBC machine select */ #define LBCRES_MSEL_GPCM 0