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- Add register definitions related to extended capability IDs in
PCI-express. I used PCIZ_* for ID constants (plain capability IDs use PCIY_*). - Add register definitions for the Advanced Error Reporting, Virtual Channels, and Device Serial Number extended capabilities. - Teach pciconf -c to list extended as well as plain capabilities. Adds more detailed parsing for AER, VC, and device serial numbers. MFC after: 2 weeks
This commit is contained in:
John Baldwin
parent
3b0620e06c
commit
79c2de35b5
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=212326
@ -36,6 +36,7 @@
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* PCIV_xxx: PCI vendor ID (only required to fixup ancient devices)
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* PCID_xxx: device ID
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* PCIY_xxx: capability identification number
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* PCIZ_xxx: extended capability identification number
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*/
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/* some PCI bus constants */
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@ -117,6 +118,28 @@
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#define PCIY_SATA 0x12 /* SATA */
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#define PCIY_PCIAF 0x13 /* PCI Advanced Features */
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/* Extended Capability Register Fields */
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#define PCIR_EXTCAP 0x100
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#define PCIM_EXTCAP_ID 0x0000ffff
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#define PCIM_EXTCAP_VER 0x000f0000
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#define PCIM_EXTCAP_NEXTPTR 0xfff00000
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#define PCI_EXTCAP_ID(ecap) ((ecap) & PCIM_EXTCAP_ID)
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#define PCI_EXTCAP_VER(ecap) (((ecap) & PCIM_EXTCAP_VER) >> 16)
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#define PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20)
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/* Extended Capability Identification Numbers */
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#define PCIZ_AER 0x0001 /* Advanced Error Reporting */
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#define PCIZ_VC 0x0002 /* Virtual Channel */
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#define PCIZ_SERNUM 0x0003 /* Device Serial Number */
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#define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */
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#define PCIZ_VENDOR 0x000b /* Vendor Unique */
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#define PCIZ_ACS 0x000d /* Access Control Services */
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#define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */
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#define PCIZ_ATS 0x000f /* Address Translation Services */
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#define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */
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/* config registers for header type 0 devices */
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#define PCIR_BARS 0x10
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@ -663,3 +686,64 @@
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#define PCIR_PCIAFCTRL_FLR 0x01
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#define PCIR_PCIAF_STATUS 0x5
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#define PCIR_PCIAFSTATUS_TP 0x01
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/* Advanced Error Reporting */
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#define PCIR_AER_UC_STATUS 0x04
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#define PCIR_AER_UC_TRAINING_ERROR 0x00000001
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#define PCIR_AER_UC_DL_PROTOCOL_ERROR 0x00000010
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#define PCIR_AER_UC_POISONED_TLP 0x00001000
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#define PCIR_AER_UC_FC_PROTOCOL_ERROR 0x00002000
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#define PCIR_AER_UC_COMPLETION_TIMEOUT 0x00004000
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#define PCIR_AER_UC_COMPLETER_ABORT 0x00008000
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#define PCIR_AER_UC_UNEXPECTED_COMPLETION 0x00010000
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#define PCIR_AER_UC_RECEIVER_OVERFLOW 0x00020000
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#define PCIR_AER_UC_MALFORMED_TLP 0x00040000
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#define PCIR_AER_UC_ECRC_ERROR 0x00080000
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#define PCIR_AER_UC_UNSUPPORTED_REQUEST 0x00100000
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#define PCIR_AER_UC_ACS_VIOLATION 0x00200000
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#define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */
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#define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */
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#define PCIR_AER_COR_STATUS 0x10
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#define PCIM_AER_COR_RECEIVER_ERROR 0x00000001
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#define PCIM_AER_COR_BAD_TLP 0x00000040
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#define PCIM_AER_COR_BAD_DLLP 0x00000080
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#define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100
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#define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000
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#define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */
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#define PCIR_AER_CAP_CONTROL 0x18
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#define PCIM_AER_FIRST_ERROR_PTR 0x0000001f
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#define PCIM_AER_ECRC_GEN_CAPABLE 0x00000020
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#define PCIM_AER_ECRC_GEN_ENABLE 0x00000040
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#define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080
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#define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100
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#define PCIR_AER_HEADER_LOG 0x1c
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#define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */
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#define PCIR_AER_ROOTERR_COR_ENABLE 0x00000001
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#define PCIR_AER_ROOTERR_NF_ENABLE 0x00000002
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#define PCIR_AER_ROOTERR_F_ENABLE 0x00000004
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#define PCIR_AER_ROOTERR_STATUS 0x30 /* Only for root complex ports */
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#define PCIR_AER_ROOTERR_COR_ERR 0x00000001
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#define PCIR_AER_ROOTERR_MULTI_COR_ERR 0x00000002
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#define PCIR_AER_ROOTERR_UC_ERR 0x00000004
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#define PCIR_AER_ROOTERR_MULTI_UC_ERR 0x00000008
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#define PCIR_AER_ROOTERR_FIRST_UC_FATAL 0x00000010
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#define PCIR_AER_ROOTERR_NF_ERR 0x00000020
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#define PCIR_AER_ROOTERR_F_ERR 0x00000040
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#define PCIR_AER_ROOTERR_INT_MESSAGE 0xf8000000
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#define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */
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#define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */
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/* Virtual Channel definitions */
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#define PCIR_VC_CAP1 0x04
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#define PCIM_VC_CAP1_EXT_COUNT 0x00000007
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#define PCIM_VC_CAP1_LOWPRI_EXT_COUNT 0x00000070
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#define PCIR_VC_CAP2 0x08
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#define PCIR_VC_CONTROL 0x0C
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#define PCIR_VC_STATUS 0x0E
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#define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0C)
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#define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0C)
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#define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0C)
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/* Serial Number definitions */
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#define PCIR_SERIAL_LOW 0x04
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#define PCIR_SERIAL_HIGH 0x08
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@ -45,6 +45,8 @@ static const char rcsid[] =
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#include "pciconf.h"
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static void list_ecaps(int fd, struct pci_conf *p);
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static void
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cap_power(int fd, struct pci_conf *p, uint8_t ptr)
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{
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@ -530,4 +532,97 @@ list_caps(int fd, struct pci_conf *p)
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printf("\n");
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ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1);
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}
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list_ecaps(fd, p);
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}
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/* From <sys/systm.h>. */
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static __inline uint32_t
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bitcount32(uint32_t x)
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{
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x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1);
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x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2);
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x = (x + (x >> 4)) & 0x0f0f0f0f;
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x = (x + (x >> 8));
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x = (x + (x >> 16)) & 0x000000ff;
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return (x);
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}
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static void
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ecap_aer(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
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{
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uint32_t sta, mask;
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printf("AER %d", ver);
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if (ver != 1)
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return;
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sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4);
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mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4);
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printf(" %d fatal", bitcount32(sta & mask));
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printf(" %d non-fatal", bitcount32(sta & ~mask));
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sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4);
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printf(" %d corrected", bitcount32(sta));
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}
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static void
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ecap_vc(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
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{
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uint32_t cap1;
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printf("VC %d", ver);
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if (ver != 1)
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return;
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cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4);
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printf(" max VC%d", cap1 & PCIM_VC_CAP1_EXT_COUNT);
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if ((cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) != 0)
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printf(" lowpri VC0-VC%d",
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(cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) >> 4);
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}
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static void
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ecap_sernum(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
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{
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uint32_t high, low;
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printf("Serial %d", ver);
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if (ver != 1)
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return;
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low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4);
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high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4);
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printf(" %08x%08x", high, low);
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}
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static void
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list_ecaps(int fd, struct pci_conf *p)
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{
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uint32_t ecap;
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uint16_t ptr;
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ptr = PCIR_EXTCAP;
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ecap = read_config(fd, &p->pc_sel, ptr, 4);
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if (ecap == 0xffffffff || ecap == 0)
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return;
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for (;;) {
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printf("ecap %04x[%03x] = ", PCI_EXTCAP_ID(ecap), ptr);
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switch (PCI_EXTCAP_ID(ecap)) {
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case PCIZ_AER:
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ecap_aer(fd, p, ptr, PCI_EXTCAP_VER(ecap));
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break;
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case PCIZ_VC:
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ecap_vc(fd, p, ptr, PCI_EXTCAP_VER(ecap));
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break;
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case PCIZ_SERNUM:
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ecap_sernum(fd, p, ptr, PCI_EXTCAP_VER(ecap));
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break;
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default:
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printf("unknown %d", PCI_EXTCAP_VER(ecap));
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break;
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}
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printf("\n");
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ptr = PCI_EXTCAP_NEXTPTR(ecap);
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if (ptr == 0)
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break;
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ecap = read_config(fd, &p->pc_sel, ptr, 4);
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}
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}
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