From 7bfa86f62a6452c13e3b8681124f7f7efd4f7104 Mon Sep 17 00:00:00 2001 From: Warner Losh Date: Tue, 18 Nov 2014 01:39:21 +0000 Subject: [PATCH] Modernize comments about BIOSes being lame since in this detail they aren't lame, the rules changed along the way. Catch up to 1999 or so with the new rules. --- sys/dev/pccbb/pccbb.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/sys/dev/pccbb/pccbb.c b/sys/dev/pccbb/pccbb.c index 9724154238ef..f5f9c9ad5621 100644 --- a/sys/dev/pccbb/pccbb.c +++ b/sys/dev/pccbb/pccbb.c @@ -1584,13 +1584,17 @@ cbb_resume(device_t self) uint32_t tmp; /* - * Some BIOSes will not save the BARs for the pci chips, so we - * must do it ourselves. If the BAR is reset to 0 for an I/O - * device, it will read back as 0x1, so no explicit test for - * memory devices are needed. + * In the APM and early ACPI era, BIOSes saved the PCI config + * registers. As chips became more complicated, that functionality moved + * into the ACPI code / tables. We must therefore, restore the settings + * we made here to make sure the device come back. Transitions to Dx + * from D0 and back to D0 cause the bridge to lose its config space, so + * all the bus mappings and such are preserved. * - * Note: The PCI bus code should do this automatically for us on - * suspend/resume, but until it does, we have to cope. + * For most drivers, the PCI layer handles this saving. However, + * sicne there's much black magic and archane art hidden in these + * few lines of code that would be difficult to transition into + * the PCI layer. */ pci_write_config(self, CBBR_SOCKBASE, rman_get_start(sc->base_res), 4); DEVPRINTF((self, "PCI Memory allocated: %08lx\n",