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Move common GIC interrupt numbers to the common header. These are the same

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across the GICv2 and GICv3 drivers so we only need a single copy of them.

Sponsored by:	Turing Robotic Industries
This commit is contained in:
Andrew Turner 2018-06-19 16:14:23 +00:00
parent d6c579b29f
commit 8214ff0f9e
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=335373
3 changed files with 10 additions and 14 deletions
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6
sys/arm/arm/gic.h
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@ -39,12 +39,6 @@
#ifndef _ARM_GIC_H_
#define _ARM_GIC_H_
#define GIC_FIRST_SGI 0 /* Irqs 0-15 are SGIs/IPIs. */
#define GIC_LAST_SGI 15
#define GIC_FIRST_PPI 16 /* Irqs 16-31 are private (per */
#define GIC_LAST_PPI 31 /* core) peripheral interrupts. */
#define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */
#ifdef INTRNG
struct arm_gic_range {
uint64_t bus;

9
sys/arm/arm/gic_common.h
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@ -44,6 +44,15 @@
__BUS_ACCESSOR(gic, hw_rev, GIC, HW_REV, u_int);
__BUS_ACCESSOR(gic, bus, GIC, BUS, u_int);
/* Software Generated Interrupts */
#define GIC_FIRST_SGI 0 /* Irqs 0-15 are SGIs/IPIs. */
#define GIC_LAST_SGI 15
/* Private Peripheral Interrupts */
#define GIC_FIRST_PPI 16 /* Irqs 16-31 are private (per */
#define GIC_LAST_PPI 31 /* core) peripheral interrupts. */
/* Shared Peripheral Interrupts */
#define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */
/* Common register values */
#define GICD_CTLR 0x0000 /* v1 ICDDCR */
#define GICD_TYPER 0x0004 /* v1 ICDICTR */

9
sys/arm64/arm64/gic_v3_reg.h
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@ -44,14 +44,7 @@
/* Upper value is determined by LPI max priority */
#define GIC_PRIORITY_MIN (0xFCUL)
/* Numbers for software generated interrupts */
#define GIC_FIRST_SGI (0)
#define GIC_LAST_SGI (15)
/* Numbers for private peripheral interrupts */
#define GIC_FIRST_PPI (16)
#define GIC_LAST_PPI (31)
/* Numbers for spared peripheral interrupts */
#define GIC_FIRST_SPI (32)
/* Numbers for shared peripheral interrupts */
#define GIC_LAST_SPI (1019)
/* Numbers for local peripheral interrupts */
#define GIC_FIRST_LPI (8192)