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synced 2024-12-11 09:50:12 +00:00
Clear any possibly pending PCI error bits left by the firmware. These
could trigger an error interrupt that we can't actually to do anything against as soon as enabling the error handlers. While at it don't bother about writing only to the write-one-to-clear bits when clearing error bits.
This commit is contained in:
Marius Strobl
parent
4f55a298ce
commit
9d769eb369
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=183152
@ -369,9 +369,6 @@ psycho_attach(device_t dev)
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sc->sc_mtx = osc->sc_mtx;
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}
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/* Clear PCI AFSR. */
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PCICTL_WRITE8(sc, PCR_AFS, PCIAFSR_ERRMASK);
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csr = PSYCHO_READ8(sc, PSR_CS);
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ver = PSYCHO_GCSR_VERS(csr);
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sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */
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@ -425,7 +422,7 @@ psycho_attach(device_t dev)
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break;
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}
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csr |= PCICTL_SERR | PCICTL_ERRINTEN | PCICTL_ARB_4;
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csr |= PCICTL_ERRINTEN | PCICTL_ARB_4;
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csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN);
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#ifdef PSYCHO_DEBUG
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device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n",
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@ -533,46 +530,7 @@ psycho_attach(device_t dev)
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"controller for INO %d", __func__, n);
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}
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/*
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* Establish handlers for interesting interrupts...
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*
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* XXX We need to remember these and remove this to support
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* hotplug on the UPA/FHC bus.
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*
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* XXX Not all controllers have these, but installing them
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* is better than trying to sort through this mess.
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*/
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psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL);
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psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL);
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#ifdef DEBUGGER_ON_POWERFAIL
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psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail,
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NULL);
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#else
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psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL,
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(driver_intr_t *)psycho_powerfail);
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#endif
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/* Psycho-specific initialization */
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if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
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/*
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* Hummingbirds/Sabres do not have the following two
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* interrupts.
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*/
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/*
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* The spare hardware interrupt is used for the
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* over-temperature interrupt.
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*/
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psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP,
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NULL, psycho_overtemp);
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#ifdef PSYCHO_MAP_WAKEUP
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/*
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* psycho_wakeup() doesn't do anything useful right
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* now.
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*/
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psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP,
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psycho_wakeup, NULL);
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#endif /* PSYCHO_MAP_WAKEUP */
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/* Initialize the counter-timer. */
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sparc64_counter_init(device_get_nameunit(dev),
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rman_get_bustag(sc->sc_mem_res),
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@ -612,14 +570,6 @@ psycho_attach(device_t dev)
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iommu_reset(sc->sc_is);
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}
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/*
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* Register a PCI bus error interrupt handler according to which
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* half this is. Hummingbird/Sabre don't have a PCI bus B error
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* interrupt but they are also only used for PCI bus A.
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*/
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psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP :
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PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL);
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/* Allocate our tags. */
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sc->sc_pci_memt = psycho_alloc_bus_tag(sc, PCI_MEMORY_BUS_SPACE);
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sc->sc_pci_iot = psycho_alloc_bus_tag(sc, PCI_IO_BUS_SPACE);
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@ -643,11 +593,61 @@ psycho_attach(device_t dev)
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prop_array[0], prop_array[1], prop_array[0]);
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sc->sc_pci_secbus = prop_array[0];
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/* Clear PCI status error bits. */
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/* Clear any pending PCI error bits. */
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PCIB_WRITE_CONFIG(dev, sc->sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
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PCIR_STATUS, PCIM_STATUS_PERR | PCIM_STATUS_RMABORT |
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PCIM_STATUS_RTABORT | PCIM_STATUS_STABORT |
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PCIM_STATUS_PERRREPORT, 2);
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PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_pci_secbus,
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PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2);
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PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS));
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PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS));
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if (osc == NULL) {
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/*
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* Establish handlers for interesting interrupts...
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*
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* XXX We need to remember these and remove this to support
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* hotplug on the UPA/FHC bus.
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*
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* XXX Not all controllers have these, but installing them
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* is better than trying to sort through this mess.
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*/
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psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL);
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psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL);
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#ifdef DEBUGGER_ON_POWERFAIL
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psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, psycho_powerfail,
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NULL);
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#else
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psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL,
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(driver_intr_t *)psycho_powerfail);
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#endif
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if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
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/*
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* Hummingbirds/Sabres do not have the following two
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* interrupts.
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*/
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/*
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* The spare hardware interrupt is used for the
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* over-temperature interrupt.
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*/
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psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP,
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NULL, psycho_overtemp);
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#ifdef PSYCHO_MAP_WAKEUP
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/*
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* psycho_wakeup() doesn't do anything useful right
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* now.
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*/
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psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP,
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psycho_wakeup, NULL);
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#endif /* PSYCHO_MAP_WAKEUP */
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}
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}
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/*
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* Register a PCI bus error interrupt handler according to which
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* half this is. Hummingbird/Sabre don't have a PCI bus B error
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* interrupt but they are also only used for PCI bus A.
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*/
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psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP :
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PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL);
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/*
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* Set the latency timer register as this isn't always done by the
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@ -808,7 +808,7 @@ psycho_ce(void *arg)
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device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx "
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"AFSR %#lx\n", (u_long)afar, (u_long)afsr);
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/* Clear the error bits that we caught. */
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PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr & CEAFSR_ERRMASK);
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PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr);
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mtx_unlock_spin(sc->sc_mtx);
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return (FILTER_HANDLED);
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}
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@ -265,10 +265,6 @@
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#define CEAFSR_P_DRD (1UL << 62) /* Pri. error caused by DVMA read */
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#define CEAFSR_P_PIO (1UL << 63) /* Pri. error caused by PIO access */
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#define CEAFSR_ERRMASK \
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(CEAFSR_P_PIO | CEAFSR_P_DRD | CEAFSR_P_DWR | \
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CEAFSR_S_PIO | CEAFSR_S_DRD | CEAFSR_S_DWR)
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/* PCI asynchronous fault status register */
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#define PCIAFSR_P_MA (1UL << 63) /* Pri. master abort */
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#define PCIAFSR_P_TA (1UL << 62) /* Pri. target abort */
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@ -282,10 +278,6 @@
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#define PCIAFSR_BLK (1UL << 31) /* failed pri. transfer was block r/w */
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#define PCIAFSR_MID (0x3eUL << 25) /* UPA MID causing error transaction */
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#define PCIAFSR_ERRMASK \
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(PCIAFSR_P_MA | PCIAFSR_P_TA | PCIAFSR_P_RTRY | PCIAFSR_P_RERR |\
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PCIAFSR_S_MA | PCIAFSR_S_TA | PCIAFSR_S_RTRY | PCIAFSR_S_RERR)
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/* PCI diagnostic register */
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#define DIAG_RTRY_DIS 0x0000000000000040 /* dis. retry limit */
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#define DIAG_ISYNC_DIS 0x0000000000000020 /* dis. DMA write / int sync */
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