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Bring the binutils_2_12_20020622 snap version of this to the HEAD branch.
This commit is contained in:
David E. O'Brien
parent
67fc1b2b4d
commit
adadc07b46
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=99468
@ -186,9 +186,9 @@ typedef struct _i386_insn i386_insn;
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/* List of chars besides those in app.c:symbol_chars that can start an
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operand. Used to prevent the scrubber eating vital white-space. */
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#ifdef LEX_AT
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const char extra_symbol_chars[] = "*%-(@";
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const char extra_symbol_chars[] = "*%-(@[";
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#else
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const char extra_symbol_chars[] = "*%-(";
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const char extra_symbol_chars[] = "*%-([";
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#endif
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#if (defined (TE_I386AIX) \
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@ -2212,15 +2212,15 @@ process_suffix ()
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/* For movzx and movsx, need to check the register type. */
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if (intel_syntax
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&& (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe))
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if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX)
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{
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unsigned int prefix = DATA_PREFIX_OPCODE;
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&& (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)
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&& i.suffix == BYTE_MNEM_SUFFIX)
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{
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unsigned int prefix = DATA_PREFIX_OPCODE;
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if ((i.op[1].regs->reg_type & Reg16) != 0)
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if (!add_prefix (prefix))
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return 0;
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}
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if ((i.op[1].regs->reg_type & Reg16) != 0)
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if (!add_prefix (prefix))
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return 0;
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}
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if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
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{
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@ -2232,6 +2232,7 @@ process_suffix ()
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else
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i.tm.base_opcode |= 1;
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}
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/* Now select between word & dword operations via the operand
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size prefix, except for instructions that will ignore this
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prefix anyway. */
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@ -2313,7 +2314,7 @@ check_byte_reg ()
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if (flag_code == CODE_64BIT
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&& (i.tm.operand_types[op] & InOutPortReg) == 0)
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{
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as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
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as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
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i.op[op].regs->reg_name,
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i.suffix);
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return 0;
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@ -2372,7 +2373,7 @@ check_long_reg ()
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lowering is more complicated. */
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if (flag_code == CODE_64BIT)
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{
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as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
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as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
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i.op[op].regs->reg_name,
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i.suffix);
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return 0;
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@ -2389,7 +2390,7 @@ check_long_reg ()
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else if ((i.types[op] & Reg64) != 0
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&& (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
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{
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as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
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as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
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i.op[op].regs->reg_name,
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i.suffix);
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return 0;
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@ -2421,7 +2422,7 @@ check_qword_reg ()
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{
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/* Prohibit these changes in the 64bit mode, since the
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lowering is more complicated. */
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as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
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as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
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i.op[op].regs->reg_name,
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i.suffix);
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return 0;
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@ -2454,7 +2455,7 @@ check_word_reg ()
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lowering is more complicated. */
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if (flag_code == CODE_64BIT)
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{
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as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
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as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
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i.op[op].regs->reg_name,
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i.suffix);
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return 0;
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@ -2984,7 +2985,6 @@ output_jump ()
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{
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char *p;
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int size;
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fixS *fixP;
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if (i.tm.opcode_modifier & JumpByte)
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{
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@ -3035,9 +3035,8 @@ output_jump ()
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p = frag_more (1 + size);
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*p++ = i.tm.base_opcode;
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fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
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i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
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fixP->fx_pcrel_adjust = size;
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fix_new_exp (frag_now, p - frag_now->fr_literal, size,
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i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
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}
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static void
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@ -3230,7 +3229,6 @@ output_disp ()
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int size = 4;
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int sign = 0;
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int pcrel = (i.flags[n] & Operand_PCrel) != 0;
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fixS *fixP;
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/* The PC relative address is computed relative
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to the instruction boundary, so in case immediate
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@ -3270,11 +3268,9 @@ output_disp ()
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}
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p = frag_more (size);
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fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
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i.op[n].disps, pcrel,
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reloc (size, pcrel, sign, i.reloc[n]));
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if (pcrel)
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fixP->fx_pcrel_adjust = size;
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fix_new_exp (frag_now, p - frag_now->fr_literal, size,
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i.op[n].disps, pcrel,
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reloc (size, pcrel, sign, i.reloc[n]));
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}
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}
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}
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@ -4219,7 +4215,6 @@ md_estimate_size_before_relax (fragP, segment)
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RELOC_ENUM reloc_type;
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unsigned char *opcode;
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int old_fr_fix;
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fixS *fixP;
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if (fragP->fr_var != NO_RELOC)
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reloc_type = fragP->fr_var;
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@ -4237,18 +4232,15 @@ md_estimate_size_before_relax (fragP, segment)
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/* Make jmp (0xeb) a (d)word displacement jump. */
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opcode[0] = 0xe9;
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fragP->fr_fix += size;
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fixP = fix_new (fragP, old_fr_fix, size,
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fragP->fr_symbol,
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fragP->fr_offset, 1,
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reloc_type);
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fixP->fx_pcrel_adjust = size;
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fix_new (fragP, old_fr_fix, size,
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fragP->fr_symbol,
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fragP->fr_offset, 1,
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reloc_type);
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break;
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case COND_JUMP86:
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if (no_cond_jump_promotion)
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goto relax_guess;
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if (size == 2)
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if (size == 2
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&& (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
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{
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/* Negate the condition, and branch past an
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unconditional jump. */
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@ -4259,18 +4251,24 @@ md_estimate_size_before_relax (fragP, segment)
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/* We added two extra opcode bytes, and have a two byte
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offset. */
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fragP->fr_fix += 2 + 2;
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fixP = fix_new (fragP, old_fr_fix + 2, 2,
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fragP->fr_symbol,
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fragP->fr_offset, 1,
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reloc_type);
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fixP->fx_pcrel_adjust = size;
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fix_new (fragP, old_fr_fix + 2, 2,
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fragP->fr_symbol,
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fragP->fr_offset, 1,
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reloc_type);
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break;
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}
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/* Fall through. */
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case COND_JUMP:
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if (no_cond_jump_promotion)
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goto relax_guess;
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if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
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{
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fragP->fr_fix += 1;
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fix_new (fragP, old_fr_fix, 1,
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fragP->fr_symbol,
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fragP->fr_offset, 1,
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BFD_RELOC_8_PCREL);
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break;
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}
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/* This changes the byte-displacement jump 0x7N
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to the (d)word-displacement jump 0x0f,0x8N. */
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@ -4278,11 +4276,10 @@ md_estimate_size_before_relax (fragP, segment)
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opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
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/* We've added an opcode byte. */
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fragP->fr_fix += 1 + size;
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fixP = fix_new (fragP, old_fr_fix + 1, size,
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fragP->fr_symbol,
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fragP->fr_offset, 1,
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reloc_type);
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fixP->fx_pcrel_adjust = size;
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fix_new (fragP, old_fr_fix + 1, size,
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fragP->fr_symbol,
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fragP->fr_offset, 1,
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reloc_type);
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break;
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default:
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@ -4293,7 +4290,6 @@ md_estimate_size_before_relax (fragP, segment)
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return fragP->fr_fix - old_fr_fix;
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}
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relax_guess:
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/* Guess size depending on current relax state. Initially the relax
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state will correspond to a short jump and we return 1, because
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the variable part of the frag (the branch offset) is one byte
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@ -4611,6 +4607,8 @@ md_apply_fix3 (fixP, valP, seg)
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else if (use_rela_relocations)
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{
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fixP->fx_no_overflow = 1;
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/* Remember value for tc_gen_reloc. */
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fixP->fx_addnumber = value;
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value = 0;
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}
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#endif
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@ -5124,9 +5122,23 @@ tc_gen_reloc (section, fixp)
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/* Use the rela in 64bit mode. */
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else
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{
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rel->addend = fixp->fx_offset;
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if (fixp->fx_pcrel)
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rel->addend -= fixp->fx_pcrel_adjust;
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if (!fixp->fx_pcrel)
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rel->addend = fixp->fx_offset;
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else
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switch (code)
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{
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case BFD_RELOC_X86_64_PLT32:
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case BFD_RELOC_X86_64_GOT32:
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case BFD_RELOC_X86_64_GOTPCREL:
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rel->addend = fixp->fx_offset - fixp->fx_size;
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break;
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default:
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rel->addend = (section->vma
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- fixp->fx_size
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+ fixp->fx_addnumber
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+ md_pcrel_from (fixp));
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break;
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}
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}
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rel->howto = bfd_reloc_type_lookup (stdoutput, code);
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