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https://git.FreeBSD.org/src.git
synced 2024-12-13 10:02:38 +00:00
Add two of three workarounds for interrupt storms for o2micro parts as
obtained from o2micro. These should only be needed for 'older' o2micro bridges (anything before the 7xxx series of bridges), but will work with the new bridges. # I don't plan on porting it to oldcard, but will happily commit to # oldcard if someone else needs them.
This commit is contained in:
Warner Losh
parent
1eb3be492d
commit
e4e7b5bc54
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=115887
@ -395,6 +395,13 @@
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#define EXCA_RID_296 0x32
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#define EXCA_RID_396 0xb2
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/*
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* o2 micro specific registers
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*/
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#define EXCA_O2MICRO_CTRL_C 0x3a
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#define EXCA_O2CC_IREQ_INTC 0x80
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#define EXCA_O2CC_STSCHG_INTC 0x20
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/* Plug and play */
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#define EXCA_PNP_ACTIONTEC 0x1802A904 /* AEI0218 */
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#define EXCA_PNP_IBM3765 0x65374d24 /* IBM3765 */
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@ -172,12 +172,12 @@ struct yenta_chipinfo {
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{PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS},
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/* 02Micro */
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{PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_CIRRUS},
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{PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_CIRRUS},
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{PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_CIRRUS},
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{PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_CIRRUS},
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{PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_CIRRUS},
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{PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_CIRRUS},
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{PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO},
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{PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO},
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{PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO},
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{PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO},
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{PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO},
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{PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO},
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/* sentinel */
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{0 /* null id */, "unknown", CB_UNKNOWN},
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@ -402,7 +402,7 @@ cbb_probe(device_t brdev)
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static void
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cbb_chipinit(struct cbb_softc *sc)
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{
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uint32_t mux, sysctrl;
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uint32_t mux, sysctrl, reg;
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/* Set CardBus latency timer */
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if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20)
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@ -486,6 +486,36 @@ cbb_chipinit(struct cbb_softc *sc)
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* on some machines.
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*/
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pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4);
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break;
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case CB_O2MICRO:
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/*
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* Issue #1: INT# generated at the same time as
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* selected ISA IRQ. When IREQ# or STSCHG# is active,
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* in addition to the ISA IRQ being generated, INT#
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* will also be generated at the same time.
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*
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* Some of our older controllers have an issue in
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* which the slot's PCI INT# will be asserted whenever
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* IREQ# or STSCGH# is asserted even if ExCA registers
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* 03h or 05h have an ISA IRQ selected.
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*
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* The fix for this issue, which will work for any
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* controller (old or new), is to set ExCA registers
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* 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b.
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* These bits are undocumented. By setting this
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* register (of each slot) to '1010xxxxb' a routing of
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* IREQ# to INTC# and STSCHG# to INTC# is selected.
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* Since INTC# isn't connected there will be no
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* unexpected PCI INT when IREQ# or STSCHG# is active.
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* However, INTA# (slot 0) or INTB# (slot 1) will
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* still be correctly generated if NO ISA IRQ is
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* selected (ExCA regs 03h or 05h are cleared).
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*/
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reg = exca_getb(&sc->exca, EXCA_O2MICRO_CTRL_C);
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reg = (reg & 0x0f) |
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EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC;
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exca_putb(&sc->exca, EXCA_O2MICRO_CTRL_C, reg);
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break;
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case CB_TOPIC97:
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/*
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@ -555,6 +585,45 @@ cbb_chipinit(struct cbb_softc *sc)
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pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4);
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}
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static void
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cbb_powerstate_d0(device_t dev)
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{
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u_int32_t membase, irq;
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if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
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/* Save important PCI config data. */
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membase = pci_read_config(dev, CBBR_SOCKBASE, 4);
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irq = pci_read_config(dev, PCIR_INTLINE, 4);
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/* Reset the power state. */
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device_printf(dev, "chip is in D%d power mode "
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"-- setting to D0\n", pci_get_powerstate(dev));
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pci_set_powerstate(dev, PCI_POWERSTATE_D0);
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/* Restore PCI config data. */
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pci_write_config(dev, CBBR_SOCKBASE, membase, 4);
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pci_write_config(dev, PCIR_INTLINE, irq, 4);
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}
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}
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/*
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* Print out the config space
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*/
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static void
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cbb_print_config(device_t dev)
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{
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int i;
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device_printf(dev, "PCI Configuration space:");
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for (i = 0; i < 256; i += 4) {
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if (i % 16 == 0)
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printf("\n 0x%02x: ", i);
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printf("0x%08x ", pci_read_config(dev, i, 4));
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}
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printf("\n");
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}
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static int
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cbb_attach(device_t brdev)
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{
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@ -572,6 +641,8 @@ cbb_attach(device_t brdev)
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SLIST_INIT(&sc->rl);
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STAILQ_INIT(&sc->intr_handlers);
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cbb_powerstate_d0(brdev);
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#ifndef BURN_THE_BOATS
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/*
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* The PCI bus code should assign us memory in the absense
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@ -621,8 +692,11 @@ cbb_attach(device_t brdev)
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DEVPRINTF((brdev, "PCI Memory allocated: %08lx\n",
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rman_get_start(sc->base_res)));
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#endif
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} else {
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DEVPRINTF((brdev, "Found memory at %08lx\n",
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rman_get_start(sc->base_res)));
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}
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sc->bst = rman_get_bustag(sc->base_res);
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sc->bsh = rman_get_bushandle(sc->base_res);
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exca_init(&sc->exca, brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET);
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@ -674,11 +748,14 @@ cbb_attach(device_t brdev)
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/* reset interrupt */
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cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT));
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if (bootverbose)
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cbb_print_config(brdev);
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/* Start the thread */
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if (kthread_create(cbb_event_thread, sc, &sc->event_thread, 0, 0,
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"%s%d", device_get_name(sc->dev), device_get_unit(sc->dev))) {
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device_printf (sc->dev, "unable to create event thread.\n");
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panic ("cbb_create_event_thread");
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"%s%d", device_get_name(brdev), device_get_unit(brdev))) {
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device_printf(brdev, "unable to create event thread.\n");
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panic("cbb_create_event_thread");
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}
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return (0);
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@ -1041,13 +1118,60 @@ cbb_detect_voltage(device_t brdev)
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return (vol);
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}
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static uint8_t
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cbb_o2micro_power_hack(struct cbb_softc *sc)
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{
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uint8_t reg;
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/*
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* Issue #2: INT# not qualified with IRQ Routing Bit. An
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* unexpected PCI INT# may be generated during PC-Card
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* initialization even with the IRQ Routing Bit Set with some
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* PC-Cards.
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*
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* This is a two part issue. The first part is that some of
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* our older controllers have an issue in which the slot's PCI
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* INT# is NOT qualified by the IRQ routing bit (PCI reg. 3Eh
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* bit 7). Regardless of the IRQ routing bit, if NO ISA IRQ
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* is selected (ExCA register 03h bits 3:0, of the slot, are
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* cleared) we will generate INT# if IREQ# is asserted. The
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* second part is because some PC-Cards prematurally assert
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* IREQ# before the ExCA registers are fully programmed. This
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* in turn asserts INT# because ExCA register 03h bits 3:0
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* (ISA IRQ Select) are not yet programmed.
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*
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* The fix for this issue, which will work for any controller
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* (old or new), is to set ExCA register 03h bits 3:0 = 0001b
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* (select IRQ1), of the slot, before turning on slot power.
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* Selecting IRQ1 will result in INT# NOT being asserted
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* (because IRQ1 is selected), and IRQ1 won't be asserted
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* because our controllers don't generate IRQ1.
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*/
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reg = exca_getb(&sc->exca, EXCA_INTR);
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exca_putb(&sc->exca, EXCA_INTR, (reg & 0xf0) | 1);
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return (reg);
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}
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/*
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* Restore the damage that cbb_o2micro_power_hack does to EXCA_INTR so
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* we don't have an interrupt storm on power on. This has the efect of
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* disabling card status change interrupts for the duration of poweron.
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*/
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static void
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cbb_o2micro_power_hack2(struct cbb_softc *sc, uint8_t reg)
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{
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exca_putb(&sc->exca, EXCA_INTR, reg);
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}
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static int
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cbb_power(device_t brdev, int volts)
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{
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uint32_t status, sock_ctrl;
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struct cbb_softc *sc = device_get_softc(brdev);
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int timeout;
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int retval = 0;
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uint32_t sockevent;
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uint8_t reg = 0;
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DEVPRINTF((sc->dev, "cbb_power: %s and %s [%x]\n",
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(volts & CARD_VCCMASK) == CARD_VCC_UC ? "CARD_VCC_UC" :
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@ -1113,6 +1237,8 @@ cbb_power(device_t brdev, int volts)
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if (cbb_get(sc, CBB_SOCKET_CONTROL) == sock_ctrl)
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return (1); /* no change necessary */
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if (volts != 0 && sc->chipset == CB_O2MICRO)
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reg = cbb_o2micro_power_hack(sc);
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cbb_set(sc, CBB_SOCKET_CONTROL, sock_ctrl);
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status = cbb_get(sc, CBB_SOCKET_STATE);
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@ -1133,7 +1259,7 @@ cbb_power(device_t brdev, int volts)
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cbb_set(sc, CBB_SOCKET_EVENT, sockevent);
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if (timeout < 0) {
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printf ("VCC supply failed.\n");
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return (0);
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goto done;
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}
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/* XXX
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@ -1162,9 +1288,13 @@ cbb_power(device_t brdev, int volts)
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(volts & CARD_VPPMASK) == CARD_VPP_0V ? "CARD_VPP_0V" :
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"VPP-UNKNOWN",
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volts);
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return (0);
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goto done;
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}
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return (1); /* power changed correctly */
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retval = 1;
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done:;
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if (volts != 0 && sc->chipset == CB_O2MICRO)
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cbb_o2micro_power_hack2(sc, reg);
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return (retval);
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}
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/*
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@ -80,6 +80,7 @@ struct cbb_softc {
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#define CB_CIRRUS 6 /* Cirrus Logic CLPD683x */
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#define CB_TOPIC95 7 /* Toshiba ToPIC95 */
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#define CB_TOPIC97 8 /* Toshiba ToPIC97/100 */
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#define CB_O2MICRO 9 /* O2Micro chips */
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SLIST_HEAD(, cbb_reslist) rl;
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STAILQ_HEAD(, cbb_intrhand) intr_handlers;
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