From f8739dd5f97c8e352a0ef91ccf6a4d79b0a2d587 Mon Sep 17 00:00:00 2001 From: Marcel Moolenaar Date: Sat, 16 Nov 2002 17:05:06 +0000 Subject: [PATCH] Implement the lock with a cmpxchg instruction instead of a xchg. Both are atomic, but the cmpxchg has memory ordering hints. We give this acquire semantics. NOTE: The unlock in libc_r is implemented by a "normal" assign statement. This is not correct on ia64 due to the memory ordering characteristics of the architecture. We need release semantics for an unlock. --- lib/libc_r/arch/ia64/_atomic_lock.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/lib/libc_r/arch/ia64/_atomic_lock.S b/lib/libc_r/arch/ia64/_atomic_lock.S index 836b3751abb0..d2fc18a02f2e 100644 --- a/lib/libc_r/arch/ia64/_atomic_lock.S +++ b/lib/libc_r/arch/ia64/_atomic_lock.S @@ -38,11 +38,12 @@ * is not currently locked. * * long _atomic_lock(long *); - * eax will contain the return value (zero if lock obtained). */ ENTRY(_atomic_lock, 1) + mov ar.ccv = r0 add r14 = 1, r0 + nop 0 ;; - xchg8 r8 = [r32], r14 + cmpxchg8.acq r8 = [r32], r14, ar.ccv br.ret.sptk rp END(_atomic_lock)