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- Rename the IPI_WAIT macro to IPI_DONE.
- Don't require all receivers of ipis to wait for all other receivers, only that the sender wait for all receivers. This should reduce the amount of time spent with interrupts disabled, which may be a cause of ipi timeouts. Discussed with: tmm
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=116567
@ -37,12 +37,9 @@ __FBSDID("$FreeBSD$");
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.register %g2, #ignore
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.register %g3, #ignore
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#define IPI_WAIT(r1, r2, r3, r4) \
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#define IPI_DONE(r1, r2, r3, r4) \
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lduw [PCPU(CPUMASK)], r4 ; \
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ATOMIC_CLEAR_INT(r1, r2, r3, r4) ; \
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9: lduw [r1], r2 ; \
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brnz,a,pn r2, 9b ; \
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nop
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ATOMIC_CLEAR_INT(r1, r2, r3, r4)
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/*
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* Invalidate a physical page in the data cache. For UltraSPARC I and II.
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@ -80,7 +77,7 @@ ENTRY(tl_ipi_spitfire_dcache_page_inval)
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2: brgz,pt %g2, 1b
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sub %g2, %g4, %g2
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IPI_WAIT(%g5, %g1, %g2, %g3)
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IPI_DONE(%g5, %g1, %g2, %g3)
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retry
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END(tl_ipi_spitfire_dcache_page_inval)
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@ -121,7 +118,7 @@ ENTRY(tl_ipi_spitfire_icache_page_inval)
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2: brgz,pt %g2, 1b
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sub %g2, %g4, %g2
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IPI_WAIT(%g5, %g1, %g2, %g3)
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IPI_DONE(%g5, %g1, %g2, %g3)
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retry
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END(tl_ipi_spitfire_icache_page_inval)
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@ -153,7 +150,7 @@ ENTRY(tl_ipi_cheetah_dcache_page_inval)
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blt,a,pt %xcc, 1b
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nop
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IPI_WAIT(%g5, %g1, %g2, %g3)
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IPI_DONE(%g5, %g1, %g2, %g3)
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retry
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END(tl_ipi_cheetah_dcache_page_inval)
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@ -208,7 +205,7 @@ ENTRY(tl_ipi_tlb_page_demap)
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stxa %g0, [%g2] ASI_IMMU_DEMAP
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membar #Sync
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IPI_WAIT(%g5, %g1, %g2, %g3)
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IPI_DONE(%g5, %g1, %g2, %g3)
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retry
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END(tl_ipi_tlb_page_demap)
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@ -251,7 +248,7 @@ ENTRY(tl_ipi_tlb_range_demap)
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blt,a,pt %xcc, 1b
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nop
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IPI_WAIT(%g5, %g1, %g2, %g3)
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IPI_DONE(%g5, %g1, %g2, %g3)
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retry
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END(tl_ipi_tlb_range_demap)
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@ -274,6 +271,6 @@ ENTRY(tl_ipi_tlb_context_demap)
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stxa %g0, [%g1] ASI_IMMU_DEMAP
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membar #Sync
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IPI_WAIT(%g5, %g1, %g2, %g3)
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IPI_DONE(%g5, %g1, %g2, %g3)
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retry
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END(tl_ipi_tlb_context_demap)
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