mirror/freebsd
1
0
Fork 0
mirror of https://git.FreeBSD.org/src.git synced 2024-12-17 10:26:15 +00:00
Code Issues Releases Activity

Add in a write barrier after each if_arge write.

Browse Source 
Without correct barriers, this code just plain doesn't work on the
mips74k cores (specifically the AR9344.)

In particular, the MDIO register accesses need this barriering or MII bus
access results in out-of-order garbage.

Tested:

* AR9344 (mips74k)
* AR9331 (mips24k)
This commit is contained in:
Adrian Chadd 2013-10-16 02:46:00 +00:00
parent 8c25111afe
commit ff7824ff52
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=256573
1 changed files with 11 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
sys/mips/atheros/if_argevar.h
View File

@ -55,10 +55,17 @@
/*
* register space access macros
*/
#define ARGE_BARRIER_READ(sc) bus_barrier(sc->arge_res, 0, 0, \
BUS_SPACE_BARRIER_READ)
#define ARGE_BARRIER_WRITE(sc) bus_barrier(sc->arge_res, 0, 0, \
BUS_SPACE_BARRIER_WRITE)
#define ARGE_BARRIER_RW(sc) bus_barrier(sc->arge_res, 0, 0, \
BUS_SPACE_BARRIER_READ | \
BUS_SPACE_BARRIER_WRITE)
#define ARGE_WRITE(sc, reg, val) do { \
bus_write_4(sc->arge_res, (reg), (val)); \
ARGE_BARRIER_WRITE((sc)); \
} while (0)
#define ARGE_READ(sc, reg) bus_read_4(sc->arge_res, (reg))
#define ARGE_SET_BITS(sc, reg, bits) \
@ -71,6 +78,9 @@
ARGE_WRITE((_sc), (_reg), (_val))
#define ARGE_MDIO_READ(_sc, _reg) \
ARGE_READ((_sc), (_reg))
#define ARGE_MDIO_BARRIER_READ(_sc) ARGE_BARRIER_READ(_sc)
#define ARGE_MDIO_BARRIER_WRITE(_sc) ARGE_BARRIER_WRITE(_sc)
#define ARGE_MDIO_BARRIER_RW(_sc) ARGE_BARRIER_READ_RW(_sc)
#define ARGE_DESC_EMPTY (1 << 31)
#define ARGE_DESC_MORE (1 << 24)