mirror of
https://git.FreeBSD.org/src.git
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54912308c8
Move cxgbetool from tools/tools to usr.sbin. Compile and install it on platforms where cxgbe(4) is built by default. Knobs (WITH_CXGBETOOL and WITHOUT_CXGBETOOL) have been added so that the user can override the default setting. Reviewed by: ngie@, gnn@, bdrewery@ MFC after: 1 month Sponsored by: Chelsio Communications Differential Revision: https://reviews.freebsd.org/D9854
65102 lines
1.8 MiB
65102 lines
1.8 MiB
/* This file is automatically generated --- changes will be lost */
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/* Generation Date : Mon Dec 7 19:40:45 IST 2015 */
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/* Directory name: t5_reg.txt, Changeset: 6934:86d3c0167c2c */
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__FBSDID("$FreeBSD$");
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struct reg_info t5_sge_regs[] = {
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{ "SGE_PF_KDOORBELL", 0x1e000, 0 },
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{ "QID", 15, 17 },
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{ "Priority", 14, 1 },
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{ "Type", 13, 1 },
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{ "PIDX", 0, 13 },
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{ "SGE_PF_GTS", 0x1e004, 0 },
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{ "IngressQID", 16, 16 },
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{ "TimerReg", 13, 3 },
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{ "SEIntArm", 12, 1 },
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{ "CIDXInc", 0, 12 },
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{ "SGE_PF_KTIMESTAMP_LO", 0x1e008, 0 },
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{ "SGE_PF_KTIMESTAMP_HI", 0x1e00c, 0 },
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{ "SGE_PF_KDOORBELL", 0x1e400, 0 },
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{ "QID", 15, 17 },
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{ "Priority", 14, 1 },
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{ "Type", 13, 1 },
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{ "PIDX", 0, 13 },
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{ "SGE_PF_GTS", 0x1e404, 0 },
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{ "IngressQID", 16, 16 },
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{ "TimerReg", 13, 3 },
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{ "SEIntArm", 12, 1 },
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{ "CIDXInc", 0, 12 },
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{ "SGE_PF_KTIMESTAMP_LO", 0x1e408, 0 },
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{ "SGE_PF_KTIMESTAMP_HI", 0x1e40c, 0 },
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{ "SGE_PF_KDOORBELL", 0x1e800, 0 },
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{ "QID", 15, 17 },
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{ "Priority", 14, 1 },
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{ "Type", 13, 1 },
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{ "PIDX", 0, 13 },
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{ "SGE_PF_GTS", 0x1e804, 0 },
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{ "IngressQID", 16, 16 },
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{ "TimerReg", 13, 3 },
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{ "SEIntArm", 12, 1 },
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{ "CIDXInc", 0, 12 },
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{ "SGE_PF_KTIMESTAMP_LO", 0x1e808, 0 },
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{ "SGE_PF_KTIMESTAMP_HI", 0x1e80c, 0 },
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{ "SGE_PF_KDOORBELL", 0x1ec00, 0 },
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{ "QID", 15, 17 },
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{ "Priority", 14, 1 },
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{ "Type", 13, 1 },
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{ "PIDX", 0, 13 },
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{ "SGE_PF_GTS", 0x1ec04, 0 },
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{ "IngressQID", 16, 16 },
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{ "TimerReg", 13, 3 },
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{ "SEIntArm", 12, 1 },
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{ "CIDXInc", 0, 12 },
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{ "SGE_PF_KTIMESTAMP_LO", 0x1ec08, 0 },
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{ "SGE_PF_KTIMESTAMP_HI", 0x1ec0c, 0 },
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{ "SGE_PF_KDOORBELL", 0x1f000, 0 },
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{ "QID", 15, 17 },
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{ "Priority", 14, 1 },
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{ "Type", 13, 1 },
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{ "PIDX", 0, 13 },
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{ "SGE_PF_GTS", 0x1f004, 0 },
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{ "IngressQID", 16, 16 },
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{ "TimerReg", 13, 3 },
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{ "SEIntArm", 12, 1 },
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{ "CIDXInc", 0, 12 },
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{ "SGE_PF_KTIMESTAMP_LO", 0x1f008, 0 },
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{ "SGE_PF_KTIMESTAMP_HI", 0x1f00c, 0 },
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{ "SGE_PF_KDOORBELL", 0x1f400, 0 },
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{ "QID", 15, 17 },
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{ "Priority", 14, 1 },
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{ "Type", 13, 1 },
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{ "PIDX", 0, 13 },
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{ "SGE_PF_GTS", 0x1f404, 0 },
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{ "IngressQID", 16, 16 },
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{ "TimerReg", 13, 3 },
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{ "SEIntArm", 12, 1 },
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{ "CIDXInc", 0, 12 },
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{ "SGE_PF_KTIMESTAMP_LO", 0x1f408, 0 },
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{ "SGE_PF_KTIMESTAMP_HI", 0x1f40c, 0 },
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{ "SGE_PF_KDOORBELL", 0x1f800, 0 },
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{ "QID", 15, 17 },
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{ "Priority", 14, 1 },
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{ "Type", 13, 1 },
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{ "PIDX", 0, 13 },
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{ "SGE_PF_GTS", 0x1f804, 0 },
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{ "IngressQID", 16, 16 },
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{ "TimerReg", 13, 3 },
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{ "SEIntArm", 12, 1 },
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{ "CIDXInc", 0, 12 },
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{ "SGE_PF_KTIMESTAMP_LO", 0x1f808, 0 },
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{ "SGE_PF_KTIMESTAMP_HI", 0x1f80c, 0 },
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{ "SGE_PF_KDOORBELL", 0x1fc00, 0 },
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{ "QID", 15, 17 },
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{ "Priority", 14, 1 },
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{ "Type", 13, 1 },
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{ "PIDX", 0, 13 },
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{ "SGE_PF_GTS", 0x1fc04, 0 },
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{ "IngressQID", 16, 16 },
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{ "TimerReg", 13, 3 },
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{ "SEIntArm", 12, 1 },
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{ "CIDXInc", 0, 12 },
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{ "SGE_PF_KTIMESTAMP_LO", 0x1fc08, 0 },
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{ "SGE_PF_KTIMESTAMP_HI", 0x1fc0c, 0 },
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{ "SGE_CONTROL", 0x1008, 0 },
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{ "IgrAllCPLtoFL", 31, 1 },
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{ "FLSplitMin", 22, 9 },
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{ "RxPktCPLMode", 18, 1 },
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{ "EgrStatusPageSize", 17, 1 },
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{ "IngHintEnable1", 15, 1 },
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{ "IngHintEnable0", 14, 1 },
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{ "IngIntCompareIDX", 13, 1 },
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{ "PktShift", 10, 3 },
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{ "IngPCIeBoundary", 7, 3 },
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{ "IngPadBoundary", 4, 3 },
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{ "GlobalEnable", 0, 1 },
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{ "SGE_HOST_PAGE_SIZE", 0x100c, 0 },
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{ "HostPageSizePF7", 28, 4 },
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{ "HostPageSizePF6", 24, 4 },
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{ "HostPageSizePF5", 20, 4 },
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{ "HostPageSizePF4", 16, 4 },
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{ "HostPageSizePF3", 12, 4 },
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{ "HostPageSizePF2", 8, 4 },
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{ "HostPageSizePF1", 4, 4 },
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{ "HostPageSizePF0", 0, 4 },
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{ "SGE_EGRESS_QUEUES_PER_PAGE_PF", 0x1010, 0 },
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{ "QueuesPerPagePF7", 28, 4 },
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{ "QueuesPerPagePF6", 24, 4 },
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{ "QueuesPerPagePF5", 20, 4 },
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{ "QueuesPerPagePF4", 16, 4 },
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{ "QueuesPerPagePF3", 12, 4 },
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{ "QueuesPerPagePF2", 8, 4 },
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{ "QueuesPerPagePF1", 4, 4 },
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{ "QueuesPerPagePF0", 0, 4 },
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{ "SGE_EGRESS_QUEUES_PER_PAGE_VF", 0x1014, 0 },
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{ "QueuesPerPageVFPF7", 28, 4 },
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{ "QueuesPerPageVFPF6", 24, 4 },
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{ "QueuesPerPageVFPF5", 20, 4 },
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{ "QueuesPerPageVFPF4", 16, 4 },
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{ "QueuesPerPageVFPF3", 12, 4 },
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{ "QueuesPerPageVFPF2", 8, 4 },
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{ "QueuesPerPageVFPF1", 4, 4 },
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{ "QueuesPerPageVFPF0", 0, 4 },
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{ "SGE_USER_MODE_LIMITS", 0x1018, 0 },
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{ "Opcode_Min", 24, 8 },
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{ "Opcode_Max", 16, 8 },
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{ "Length_Min", 8, 8 },
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{ "Length_Max", 0, 8 },
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{ "SGE_WR_ERROR", 0x101c, 0 },
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{ "SGE_PERR_INJECT", 0x1020, 0 },
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{ "MemSel", 1, 5 },
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{ "InjectDataErr", 0, 1 },
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{ "SGE_INT_CAUSE1", 0x1024, 0 },
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{ "perr_pc_chpi_rsp2", 31, 1 },
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{ "perr_flm_CreditFifo", 30, 1 },
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{ "perr_imsg_hint_fifo", 29, 1 },
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{ "perr_pc_mctag", 24, 1 },
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{ "perr_pc_chpi_rsp1", 23, 1 },
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{ "perr_pc_chpi_rsp0", 22, 1 },
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{ "perr_dbp_pc_rsp_fifo3", 21, 1 },
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{ "perr_dbp_pc_rsp_fifo2", 20, 1 },
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{ "perr_dbp_pc_rsp_fifo1", 19, 1 },
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{ "perr_dbp_pc_rsp_fifo0", 18, 1 },
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{ "perr_dmarbt", 17, 1 },
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{ "perr_flm_DbpFifo", 16, 1 },
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{ "perr_flm_MCReq_fifo", 15, 1 },
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{ "perr_flm_HintFifo", 14, 1 },
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{ "perr_align_ctl_fifo3", 13, 1 },
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{ "perr_align_ctl_fifo2", 12, 1 },
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{ "perr_align_ctl_fifo1", 11, 1 },
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{ "perr_align_ctl_fifo0", 10, 1 },
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{ "perr_edma_fifo3", 9, 1 },
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{ "perr_edma_fifo2", 8, 1 },
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{ "perr_edma_fifo1", 7, 1 },
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{ "perr_edma_fifo0", 6, 1 },
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{ "perr_pd_fifo3", 5, 1 },
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{ "perr_pd_fifo2", 4, 1 },
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{ "perr_pd_fifo1", 3, 1 },
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{ "perr_pd_fifo0", 2, 1 },
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{ "perr_ing_ctxt_mifrsp", 1, 1 },
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{ "perr_egr_ctxt_mifrsp", 0, 1 },
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{ "SGE_INT_ENABLE1", 0x1028, 0 },
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{ "perr_pc_chpi_rsp2", 31, 1 },
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{ "perr_flm_CreditFifo", 30, 1 },
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{ "perr_imsg_hint_fifo", 29, 1 },
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{ "perr_pc_mctag", 24, 1 },
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{ "perr_pc_chpi_rsp1", 23, 1 },
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{ "perr_pc_chpi_rsp0", 22, 1 },
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{ "perr_dbp_pc_rsp_fifo3", 21, 1 },
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{ "perr_dbp_pc_rsp_fifo2", 20, 1 },
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{ "perr_dbp_pc_rsp_fifo1", 19, 1 },
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{ "perr_dbp_pc_rsp_fifo0", 18, 1 },
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{ "perr_dmarbt", 17, 1 },
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{ "perr_flm_DbpFifo", 16, 1 },
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{ "perr_flm_MCReq_fifo", 15, 1 },
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{ "perr_flm_HintFifo", 14, 1 },
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{ "perr_align_ctl_fifo3", 13, 1 },
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{ "perr_align_ctl_fifo2", 12, 1 },
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{ "perr_align_ctl_fifo1", 11, 1 },
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{ "perr_align_ctl_fifo0", 10, 1 },
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{ "perr_edma_fifo3", 9, 1 },
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{ "perr_edma_fifo2", 8, 1 },
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{ "perr_edma_fifo1", 7, 1 },
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{ "perr_edma_fifo0", 6, 1 },
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{ "perr_pd_fifo3", 5, 1 },
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{ "perr_pd_fifo2", 4, 1 },
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{ "perr_pd_fifo1", 3, 1 },
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{ "perr_pd_fifo0", 2, 1 },
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{ "perr_ing_ctxt_mifrsp", 1, 1 },
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{ "perr_egr_ctxt_mifrsp", 0, 1 },
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{ "SGE_PERR_ENABLE1", 0x102c, 0 },
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{ "perr_pc_chpi_rsp2", 31, 1 },
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{ "perr_flm_CreditFifo", 30, 1 },
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{ "perr_imsg_hint_fifo", 29, 1 },
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{ "perr_pc_mctag", 24, 1 },
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{ "perr_pc_chpi_rsp1", 23, 1 },
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{ "perr_pc_chpi_rsp0", 22, 1 },
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{ "perr_dbp_pc_rsp_fifo3", 21, 1 },
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{ "perr_dbp_pc_rsp_fifo2", 20, 1 },
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{ "perr_dbp_pc_rsp_fifo1", 19, 1 },
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{ "perr_dbp_pc_rsp_fifo0", 18, 1 },
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{ "perr_dmarbt", 17, 1 },
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{ "perr_flm_DbpFifo", 16, 1 },
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{ "perr_flm_MCReq_fifo", 15, 1 },
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{ "perr_flm_HintFifo", 14, 1 },
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{ "perr_align_ctl_fifo3", 13, 1 },
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{ "perr_align_ctl_fifo2", 12, 1 },
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{ "perr_align_ctl_fifo1", 11, 1 },
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{ "perr_align_ctl_fifo0", 10, 1 },
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{ "perr_edma_fifo3", 9, 1 },
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{ "perr_edma_fifo2", 8, 1 },
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{ "perr_edma_fifo1", 7, 1 },
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{ "perr_edma_fifo0", 6, 1 },
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{ "perr_pd_fifo3", 5, 1 },
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{ "perr_pd_fifo2", 4, 1 },
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{ "perr_pd_fifo1", 3, 1 },
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{ "perr_pd_fifo0", 2, 1 },
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{ "perr_ing_ctxt_mifrsp", 1, 1 },
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{ "perr_egr_ctxt_mifrsp", 0, 1 },
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{ "SGE_INT_CAUSE2", 0x1030, 0 },
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{ "perr_dbp_hint_fl_fifo", 24, 1 },
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{ "perr_egr_dbp_tx_coal", 23, 1 },
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{ "perr_dbp_fl_fifo", 22, 1 },
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{ "perr_eswitch_fifo3", 21, 1 },
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{ "perr_eswitch_fifo2", 20, 1 },
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{ "perr_eswitch_fifo1", 19, 1 },
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{ "perr_eswitch_fifo0", 18, 1 },
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{ "perr_pc_dbp1", 17, 1 },
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{ "perr_pc_dbp0", 16, 1 },
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{ "perr_pc_dbp2", 15, 1 },
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{ "perr_conm_sram", 14, 1 },
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{ "perr_pc_mc_rsp", 13, 1 },
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{ "perr_isw_idma0_fifo", 12, 1 },
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{ "perr_isw_idma1_fifo", 11, 1 },
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{ "perr_isw_dbp_fifo", 10, 1 },
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{ "perr_isw_gts_fifo", 9, 1 },
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{ "perr_itp_evr", 8, 1 },
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{ "perr_flm_cntxmem", 7, 1 },
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{ "perr_flm_l1Cache", 6, 1 },
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{ "perr_dbp_hint_fifo", 5, 1 },
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{ "perr_dbp_hp_fifo", 4, 1 },
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{ "perr_dbp_lp_fifo", 3, 1 },
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{ "perr_ing_ctxt_cache", 2, 1 },
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{ "perr_egr_ctxt_cache", 1, 1 },
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{ "perr_base_size", 0, 1 },
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{ "SGE_INT_ENABLE2", 0x1034, 0 },
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{ "perr_dbp_hint_fl_fifo", 24, 1 },
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{ "perr_egr_dbp_tx_coal", 23, 1 },
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{ "perr_dbp_fl_fifo", 22, 1 },
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{ "perr_eswitch_fifo3", 21, 1 },
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{ "perr_eswitch_fifo2", 20, 1 },
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{ "perr_eswitch_fifo1", 19, 1 },
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{ "perr_eswitch_fifo0", 18, 1 },
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{ "perr_pc_dbp1", 17, 1 },
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{ "perr_pc_dbp0", 16, 1 },
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{ "perr_pc_dbp2", 15, 1 },
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{ "perr_conm_sram", 14, 1 },
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{ "perr_pc_mc_rsp", 13, 1 },
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{ "perr_isw_idma0_fifo", 12, 1 },
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{ "perr_isw_idma1_fifo", 11, 1 },
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{ "perr_isw_dbp_fifo", 10, 1 },
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{ "perr_isw_gts_fifo", 9, 1 },
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{ "perr_itp_evr", 8, 1 },
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{ "perr_flm_cntxmem", 7, 1 },
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{ "perr_flm_l1Cache", 6, 1 },
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{ "perr_dbp_hint_fifo", 5, 1 },
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{ "perr_dbp_hp_fifo", 4, 1 },
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{ "perr_dbp_lp_fifo", 3, 1 },
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{ "perr_ing_ctxt_cache", 2, 1 },
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{ "perr_egr_ctxt_cache", 1, 1 },
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{ "perr_base_size", 0, 1 },
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{ "SGE_PERR_ENABLE2", 0x1038, 0 },
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{ "perr_dbp_hint_fl_fifo", 24, 1 },
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{ "perr_egr_dbp_tx_coal", 23, 1 },
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{ "perr_dbp_fl_fifo", 22, 1 },
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{ "perr_eswitch_fifo3", 21, 1 },
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{ "perr_eswitch_fifo2", 20, 1 },
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{ "perr_eswitch_fifo1", 19, 1 },
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{ "perr_eswitch_fifo0", 18, 1 },
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{ "perr_pc_dbp1", 17, 1 },
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{ "perr_pc_dbp0", 16, 1 },
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{ "perr_pc_dbp2", 15, 1 },
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{ "perr_conm_sram", 14, 1 },
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{ "perr_pc_mc_rsp", 13, 1 },
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{ "perr_isw_idma0_fifo", 12, 1 },
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{ "perr_isw_idma1_fifo", 11, 1 },
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{ "perr_isw_dbp_fifo", 10, 1 },
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{ "perr_isw_gts_fifo", 9, 1 },
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{ "perr_itp_evr", 8, 1 },
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{ "perr_flm_cntxmem", 7, 1 },
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{ "perr_flm_l1Cache", 6, 1 },
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{ "perr_dbp_hint_fifo", 5, 1 },
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{ "perr_dbp_hp_fifo", 4, 1 },
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{ "perr_dbp_lp_fifo", 3, 1 },
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{ "perr_ing_ctxt_cache", 2, 1 },
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{ "perr_egr_ctxt_cache", 1, 1 },
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{ "perr_base_size", 0, 1 },
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{ "SGE_INT_CAUSE3", 0x103c, 0 },
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{ "err_flm_dbp", 31, 1 },
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{ "err_flm_idma1", 30, 1 },
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{ "err_flm_idma0", 29, 1 },
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{ "err_flm_hint", 28, 1 },
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{ "err_pcie_error3", 27, 1 },
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{ "err_pcie_error2", 26, 1 },
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{ "err_pcie_error1", 25, 1 },
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{ "err_pcie_error0", 24, 1 },
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{ "err_timer_above_max_qid", 23, 1 },
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{ "err_cpl_exceed_iqe_size", 22, 1 },
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{ "err_invalid_cidx_inc", 21, 1 },
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{ "err_itp_time_paused", 20, 1 },
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{ "err_cpl_opcode_0", 19, 1 },
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{ "err_dropped_db", 18, 1 },
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{ "err_data_cpl_on_high_qid1", 17, 1 },
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{ "err_data_cpl_on_high_qid0", 16, 1 },
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{ "err_bad_db_pidx3", 15, 1 },
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{ "err_bad_db_pidx2", 14, 1 },
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{ "err_bad_db_pidx1", 13, 1 },
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{ "err_bad_db_pidx0", 12, 1 },
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{ "err_ing_pcie_chan", 11, 1 },
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{ "err_ing_ctxt_prio", 10, 1 },
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{ "err_egr_ctxt_prio", 9, 1 },
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{ "dbfifo_hp_int", 8, 1 },
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{ "dbfifo_lp_int", 7, 1 },
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{ "reg_address_err", 6, 1 },
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{ "ingress_size_err", 5, 1 },
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{ "egress_size_err", 4, 1 },
|
|
{ "err_inv_ctxt3", 3, 1 },
|
|
{ "err_inv_ctxt2", 2, 1 },
|
|
{ "err_inv_ctxt1", 1, 1 },
|
|
{ "err_inv_ctxt0", 0, 1 },
|
|
{ "SGE_INT_ENABLE3", 0x1040, 0 },
|
|
{ "err_flm_dbp", 31, 1 },
|
|
{ "err_flm_idma1", 30, 1 },
|
|
{ "err_flm_idma0", 29, 1 },
|
|
{ "err_flm_hint", 28, 1 },
|
|
{ "err_pcie_error3", 27, 1 },
|
|
{ "err_pcie_error2", 26, 1 },
|
|
{ "err_pcie_error1", 25, 1 },
|
|
{ "err_pcie_error0", 24, 1 },
|
|
{ "err_timer_above_max_qid", 23, 1 },
|
|
{ "err_cpl_exceed_iqe_size", 22, 1 },
|
|
{ "err_invalid_cidx_inc", 21, 1 },
|
|
{ "err_itp_time_paused", 20, 1 },
|
|
{ "err_cpl_opcode_0", 19, 1 },
|
|
{ "err_dropped_db", 18, 1 },
|
|
{ "err_data_cpl_on_high_qid1", 17, 1 },
|
|
{ "err_data_cpl_on_high_qid0", 16, 1 },
|
|
{ "err_bad_db_pidx3", 15, 1 },
|
|
{ "err_bad_db_pidx2", 14, 1 },
|
|
{ "err_bad_db_pidx1", 13, 1 },
|
|
{ "err_bad_db_pidx0", 12, 1 },
|
|
{ "err_ing_pcie_chan", 11, 1 },
|
|
{ "err_ing_ctxt_prio", 10, 1 },
|
|
{ "err_egr_ctxt_prio", 9, 1 },
|
|
{ "dbfifo_hp_int", 8, 1 },
|
|
{ "dbfifo_lp_int", 7, 1 },
|
|
{ "reg_address_err", 6, 1 },
|
|
{ "ingress_size_err", 5, 1 },
|
|
{ "egress_size_err", 4, 1 },
|
|
{ "err_inv_ctxt3", 3, 1 },
|
|
{ "err_inv_ctxt2", 2, 1 },
|
|
{ "err_inv_ctxt1", 1, 1 },
|
|
{ "err_inv_ctxt0", 0, 1 },
|
|
{ "SGE_FL_BUFFER_SIZE0", 0x1044, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE1", 0x1048, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE2", 0x104c, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE3", 0x1050, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE4", 0x1054, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE5", 0x1058, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE6", 0x105c, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE7", 0x1060, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE8", 0x1064, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE9", 0x1068, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE10", 0x106c, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE11", 0x1070, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE12", 0x1074, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE13", 0x1078, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE14", 0x107c, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_FL_BUFFER_SIZE15", 0x1080, 0 },
|
|
{ "Size", 4, 28 },
|
|
{ "SGE_DBQ_CTXT_BADDR", 0x1084, 0 },
|
|
{ "BaseAddr", 3, 29 },
|
|
{ "SGE_IMSG_CTXT_BADDR", 0x1088, 0 },
|
|
{ "BaseAddr", 3, 29 },
|
|
{ "SGE_FLM_CACHE_BADDR", 0x108c, 0 },
|
|
{ "BaseAddr", 3, 29 },
|
|
{ "SGE_FLM_CFG", 0x1090, 0 },
|
|
{ "OpMode", 26, 6 },
|
|
{ "NoHdr", 18, 1 },
|
|
{ "CachePtrCnt", 16, 2 },
|
|
{ "EDRAMPtrCnt", 14, 2 },
|
|
{ "HdrStartFLQ", 11, 3 },
|
|
{ "FetchThresh", 6, 5 },
|
|
{ "CreditCnt", 4, 2 },
|
|
{ "CreditCntPacking", 2, 2 },
|
|
{ "NoEDRAM", 0, 1 },
|
|
{ "SGE_CONM_CTRL", 0x1094, 0 },
|
|
{ "EgrThresholdPacking", 14, 6 },
|
|
{ "EgrThreshold", 8, 6 },
|
|
{ "IngThreshold", 2, 6 },
|
|
{ "SGE_TIMESTAMP_LO", 0x1098, 0 },
|
|
{ "SGE_TIMESTAMP_HI", 0x109c, 0 },
|
|
{ "Opcode", 28, 2 },
|
|
{ "Value", 0, 28 },
|
|
{ "SGE_INGRESS_RX_THRESHOLD", 0x10a0, 0 },
|
|
{ "Threshold_0", 24, 6 },
|
|
{ "Threshold_1", 16, 6 },
|
|
{ "Threshold_2", 8, 6 },
|
|
{ "Threshold_3", 0, 6 },
|
|
{ "SGE_DBFIFO_STATUS", 0x10a4, 0 },
|
|
{ "Bar2Valid", 31, 1 },
|
|
{ "Bar2Full", 30, 1 },
|
|
{ "LP_Int_Thresh", 18, 12 },
|
|
{ "LP_Count", 0, 18 },
|
|
{ "SGE_DOORBELL_CONTROL", 0x10a8, 0 },
|
|
{ "HintDepthCtl", 27, 5 },
|
|
{ "NoCoalesce", 26, 1 },
|
|
{ "HP_Weight", 24, 2 },
|
|
{ "HP_Disable", 23, 1 },
|
|
{ "ForceUserDBtoLP", 22, 1 },
|
|
{ "ForceVFPF0DBtoLP", 21, 1 },
|
|
{ "ForceVFPF1DBtoLP", 20, 1 },
|
|
{ "ForceVFPF2DBtoLP", 19, 1 },
|
|
{ "ForceVFPF3DBtoLP", 18, 1 },
|
|
{ "ForceVFPF4DBtoLP", 17, 1 },
|
|
{ "ForceVFPF5DBtoLP", 16, 1 },
|
|
{ "ForceVFPF6DBtoLP", 15, 1 },
|
|
{ "ForceVFPF7DBtoLP", 14, 1 },
|
|
{ "Enable_Drop", 13, 1 },
|
|
{ "Drop_Timeout", 1, 12 },
|
|
{ "Dropped_DB", 0, 1 },
|
|
{ "SGE_DROPPED_DOORBELL", 0x10ac, 0 },
|
|
{ "SGE_DOORBELL_THROTTLE_CONTROL", 0x10b0, 0 },
|
|
{ "Bar2ThrottleCount", 16, 8 },
|
|
{ "ClrCoalesceDisable", 15, 1 },
|
|
{ "OpenBar2GateOnce", 14, 1 },
|
|
{ "ForceOpenBar2Gate", 13, 1 },
|
|
{ "Throttle_Count", 1, 12 },
|
|
{ "Throttle_Enable", 0, 1 },
|
|
{ "SGE_ITP_CONTROL", 0x10b4, 0 },
|
|
{ "Critical_Time", 10, 15 },
|
|
{ "LL_Empty", 4, 6 },
|
|
{ "LL_Read_Wait_Disable", 0, 1 },
|
|
{ "SGE_TIMER_VALUE_0_AND_1", 0x10b8, 0 },
|
|
{ "TimerValue0", 16, 16 },
|
|
{ "TimerValue1", 0, 16 },
|
|
{ "SGE_TIMER_VALUE_2_AND_3", 0x10bc, 0 },
|
|
{ "TimerValue2", 16, 16 },
|
|
{ "TimerValue3", 0, 16 },
|
|
{ "SGE_TIMER_VALUE_4_AND_5", 0x10c0, 0 },
|
|
{ "TimerValue4", 16, 16 },
|
|
{ "TimerValue5", 0, 16 },
|
|
{ "SGE_DEBUG_INDEX", 0x10cc, 0 },
|
|
{ "SGE_DEBUG_DATA_HIGH", 0x10d0, 0 },
|
|
{ "SGE_DEBUG_DATA_LOW", 0x10d4, 0 },
|
|
{ "SGE_REVISION", 0x10d8, 0 },
|
|
{ "SGE_INT_CAUSE4", 0x10dc, 0 },
|
|
{ "bar2_egress_len_or_addr_err", 29, 1 },
|
|
{ "err_cpl_exceed_max_iqe_size1", 28, 1 },
|
|
{ "err_cpl_exceed_max_iqe_size0", 27, 1 },
|
|
{ "err_wr_len_too_large3", 26, 1 },
|
|
{ "err_wr_len_too_large2", 25, 1 },
|
|
{ "err_wr_len_too_large1", 24, 1 },
|
|
{ "err_wr_len_too_large0", 23, 1 },
|
|
{ "err_large_minfetch_with_txcoal3", 22, 1 },
|
|
{ "err_large_minfetch_with_txcoal2", 21, 1 },
|
|
{ "err_large_minfetch_with_txcoal1", 20, 1 },
|
|
{ "err_large_minfetch_with_txcoal0", 19, 1 },
|
|
{ "coal_with_hp_disable_err", 18, 1 },
|
|
{ "bar2_egress_coal0_err", 17, 1 },
|
|
{ "bar2_egress_size_err", 16, 1 },
|
|
{ "flm_pc_rsp_err", 15, 1 },
|
|
{ "dbfifo_hp_int_low", 14, 1 },
|
|
{ "dbfifo_lp_int_low", 13, 1 },
|
|
{ "dbfifo_fl_int_low", 12, 1 },
|
|
{ "dbfifo_fl_int", 11, 1 },
|
|
{ "err_rx_cpl_packet_size1", 10, 1 },
|
|
{ "err_rx_cpl_packet_size0", 9, 1 },
|
|
{ "err_bad_upfl_inc_credit3", 8, 1 },
|
|
{ "err_bad_upfl_inc_credit2", 7, 1 },
|
|
{ "err_bad_upfl_inc_credit1", 6, 1 },
|
|
{ "err_bad_upfl_inc_credit0", 5, 1 },
|
|
{ "err_physaddr_len0_idma1", 4, 1 },
|
|
{ "err_physaddr_len0_idma0", 3, 1 },
|
|
{ "err_flm_invalid_pkt_drop1", 2, 1 },
|
|
{ "err_flm_invalid_pkt_drop0", 1, 1 },
|
|
{ "err_unexpected_timer", 0, 1 },
|
|
{ "SGE_INT_ENABLE4", 0x10e0, 0 },
|
|
{ "bar2_egress_len_or_addr_err", 29, 1 },
|
|
{ "err_cpl_exceed_max_iqe_size1", 28, 1 },
|
|
{ "err_cpl_exceed_max_iqe_size0", 27, 1 },
|
|
{ "err_wr_len_too_large3", 26, 1 },
|
|
{ "err_wr_len_too_large2", 25, 1 },
|
|
{ "err_wr_len_too_large1", 24, 1 },
|
|
{ "err_wr_len_too_large0", 23, 1 },
|
|
{ "err_large_minfetch_with_txcoal3", 22, 1 },
|
|
{ "err_large_minfetch_with_txcoal2", 21, 1 },
|
|
{ "err_large_minfetch_with_txcoal1", 20, 1 },
|
|
{ "err_large_minfetch_with_txcoal0", 19, 1 },
|
|
{ "coal_with_hp_disable_err", 18, 1 },
|
|
{ "bar2_egress_coal0_err", 17, 1 },
|
|
{ "bar2_egress_size_err", 16, 1 },
|
|
{ "flm_pc_rsp_err", 15, 1 },
|
|
{ "dbfifo_hp_int_low", 14, 1 },
|
|
{ "dbfifo_lp_int_low", 13, 1 },
|
|
{ "dbfifo_fl_int_low", 12, 1 },
|
|
{ "dbfifo_fl_int", 11, 1 },
|
|
{ "err_rx_cpl_packet_size1", 10, 1 },
|
|
{ "err_rx_cpl_packet_size0", 9, 1 },
|
|
{ "err_bad_upfl_inc_credit3", 8, 1 },
|
|
{ "err_bad_upfl_inc_credit2", 7, 1 },
|
|
{ "err_bad_upfl_inc_credit1", 6, 1 },
|
|
{ "err_bad_upfl_inc_credit0", 5, 1 },
|
|
{ "err_physaddr_len0_idma1", 4, 1 },
|
|
{ "err_physaddr_len0_idma0", 3, 1 },
|
|
{ "err_flm_invalid_pkt_drop1", 2, 1 },
|
|
{ "err_flm_invalid_pkt_drop0", 1, 1 },
|
|
{ "err_unexpected_timer", 0, 1 },
|
|
{ "SGE_STAT_TOTAL", 0x10e4, 0 },
|
|
{ "SGE_STAT_MATCH", 0x10e8, 0 },
|
|
{ "SGE_STAT_CFG", 0x10ec, 0 },
|
|
{ "StatSource", 9, 4 },
|
|
{ "ITPOpMode", 8, 1 },
|
|
{ "EgrCtxtOpMode", 6, 2 },
|
|
{ "IngCtxtOpMode", 4, 2 },
|
|
{ "StatMode", 2, 2 },
|
|
{ "SGE_HINT_CFG", 0x10f0, 0 },
|
|
{ "uPCutoffThreshLp", 12, 11 },
|
|
{ "HintsAllowedNoHdr", 6, 6 },
|
|
{ "HintsAllowedHdr", 0, 6 },
|
|
{ "SGE_INGRESS_QUEUES_PER_PAGE_PF", 0x10f4, 0 },
|
|
{ "QueuesPerPagePF7", 28, 4 },
|
|
{ "QueuesPerPagePF6", 24, 4 },
|
|
{ "QueuesPerPagePF5", 20, 4 },
|
|
{ "QueuesPerPagePF4", 16, 4 },
|
|
{ "QueuesPerPagePF3", 12, 4 },
|
|
{ "QueuesPerPagePF2", 8, 4 },
|
|
{ "QueuesPerPagePF1", 4, 4 },
|
|
{ "QueuesPerPagePF0", 0, 4 },
|
|
{ "SGE_INGRESS_QUEUES_PER_PAGE_VF", 0x10f8, 0 },
|
|
{ "QueuesPerPageVFPF7", 28, 4 },
|
|
{ "QueuesPerPageVFPF6", 24, 4 },
|
|
{ "QueuesPerPageVFPF5", 20, 4 },
|
|
{ "QueuesPerPageVFPF4", 16, 4 },
|
|
{ "QueuesPerPageVFPF3", 12, 4 },
|
|
{ "QueuesPerPageVFPF2", 8, 4 },
|
|
{ "QueuesPerPageVFPF1", 4, 4 },
|
|
{ "QueuesPerPageVFPF0", 0, 4 },
|
|
{ "SGE_ERROR_STATS", 0x1100, 0 },
|
|
{ "Cause_Register", 24, 3 },
|
|
{ "Cause_Bit", 19, 5 },
|
|
{ "Uncaptured_Error", 18, 1 },
|
|
{ "Error_QID_Valid", 17, 1 },
|
|
{ "Error_QID", 0, 17 },
|
|
{ "SGE_INT_CAUSE5", 0x110c, 0 },
|
|
{ "err_T_RxCRC", 31, 1 },
|
|
{ "perr_MC_RspData", 30, 1 },
|
|
{ "perr_PC_RspData", 29, 1 },
|
|
{ "perr_PD_RdRspData", 28, 1 },
|
|
{ "perr_U_RxData", 27, 1 },
|
|
{ "perr_UD_RxData", 26, 1 },
|
|
{ "perr_uP_Data", 25, 1 },
|
|
{ "perr_CIM2SGE_RxData", 24, 1 },
|
|
{ "perr_hint_delay_fifo1", 23, 1 },
|
|
{ "perr_hint_delay_fifo0", 22, 1 },
|
|
{ "perr_imsg_pd_fifo", 21, 1 },
|
|
{ "perr_ulptx_fifo1", 20, 1 },
|
|
{ "perr_ulptx_fifo0", 19, 1 },
|
|
{ "perr_idma2imsg_fifo1", 18, 1 },
|
|
{ "perr_idma2imsg_fifo0", 17, 1 },
|
|
{ "perr_pointer_data_fifo0", 16, 1 },
|
|
{ "perr_pointer_data_fifo1", 15, 1 },
|
|
{ "perr_pointer_hdr_fifo0", 14, 1 },
|
|
{ "perr_pointer_hdr_fifo1", 13, 1 },
|
|
{ "perr_payload_fifo0", 12, 1 },
|
|
{ "perr_payload_fifo1", 11, 1 },
|
|
{ "perr_edma_input_fifo3", 10, 1 },
|
|
{ "perr_edma_input_fifo2", 9, 1 },
|
|
{ "perr_edma_input_fifo1", 8, 1 },
|
|
{ "perr_edma_input_fifo0", 7, 1 },
|
|
{ "perr_mgt_bar2_fifo", 6, 1 },
|
|
{ "perr_headersplit_fifo1", 5, 1 },
|
|
{ "perr_headersplit_fifo0", 4, 1 },
|
|
{ "perr_cim_fifo1", 3, 1 },
|
|
{ "perr_cim_fifo0", 2, 1 },
|
|
{ "perr_idma_switch_output_fifo1", 1, 1 },
|
|
{ "perr_idma_switch_output_fifo0", 0, 1 },
|
|
{ "SGE_INT_ENABLE5", 0x1110, 0 },
|
|
{ "err_T_RxCRC", 31, 1 },
|
|
{ "perr_MC_RspData", 30, 1 },
|
|
{ "perr_PC_RspData", 29, 1 },
|
|
{ "perr_PD_RdRspData", 28, 1 },
|
|
{ "perr_U_RxData", 27, 1 },
|
|
{ "perr_UD_RxData", 26, 1 },
|
|
{ "perr_uP_Data", 25, 1 },
|
|
{ "perr_CIM2SGE_RxData", 24, 1 },
|
|
{ "perr_hint_delay_fifo1", 23, 1 },
|
|
{ "perr_hint_delay_fifo0", 22, 1 },
|
|
{ "perr_imsg_pd_fifo", 21, 1 },
|
|
{ "perr_ulptx_fifo1", 20, 1 },
|
|
{ "perr_ulptx_fifo0", 19, 1 },
|
|
{ "perr_idma2imsg_fifo1", 18, 1 },
|
|
{ "perr_idma2imsg_fifo0", 17, 1 },
|
|
{ "perr_pointer_data_fifo0", 16, 1 },
|
|
{ "perr_pointer_data_fifo1", 15, 1 },
|
|
{ "perr_pointer_hdr_fifo0", 14, 1 },
|
|
{ "perr_pointer_hdr_fifo1", 13, 1 },
|
|
{ "perr_payload_fifo0", 12, 1 },
|
|
{ "perr_payload_fifo1", 11, 1 },
|
|
{ "perr_edma_input_fifo3", 10, 1 },
|
|
{ "perr_edma_input_fifo2", 9, 1 },
|
|
{ "perr_edma_input_fifo1", 8, 1 },
|
|
{ "perr_edma_input_fifo0", 7, 1 },
|
|
{ "perr_mgt_bar2_fifo", 6, 1 },
|
|
{ "perr_headersplit_fifo1", 5, 1 },
|
|
{ "perr_headersplit_fifo0", 4, 1 },
|
|
{ "perr_cim_fifo1", 3, 1 },
|
|
{ "perr_cim_fifo0", 2, 1 },
|
|
{ "perr_idma_switch_output_fifo1", 1, 1 },
|
|
{ "perr_idma_switch_output_fifo0", 0, 1 },
|
|
{ "SGE_PERR_ENABLE5", 0x1114, 0 },
|
|
{ "err_T_RxCRC", 31, 1 },
|
|
{ "perr_MC_RspData", 30, 1 },
|
|
{ "perr_PC_RspData", 29, 1 },
|
|
{ "perr_PD_RdRspData", 28, 1 },
|
|
{ "perr_U_RxData", 27, 1 },
|
|
{ "perr_UD_RxData", 26, 1 },
|
|
{ "perr_uP_Data", 25, 1 },
|
|
{ "perr_CIM2SGE_RxData", 24, 1 },
|
|
{ "perr_hint_delay_fifo1", 23, 1 },
|
|
{ "perr_hint_delay_fifo0", 22, 1 },
|
|
{ "perr_imsg_pd_fifo", 21, 1 },
|
|
{ "perr_ulptx_fifo1", 20, 1 },
|
|
{ "perr_ulptx_fifo0", 19, 1 },
|
|
{ "perr_idma2imsg_fifo1", 18, 1 },
|
|
{ "perr_idma2imsg_fifo0", 17, 1 },
|
|
{ "perr_pointer_data_fifo0", 16, 1 },
|
|
{ "perr_pointer_data_fifo1", 15, 1 },
|
|
{ "perr_pointer_hdr_fifo0", 14, 1 },
|
|
{ "perr_pointer_hdr_fifo1", 13, 1 },
|
|
{ "perr_payload_fifo0", 12, 1 },
|
|
{ "perr_payload_fifo1", 11, 1 },
|
|
{ "perr_edma_input_fifo3", 10, 1 },
|
|
{ "perr_edma_input_fifo2", 9, 1 },
|
|
{ "perr_edma_input_fifo1", 8, 1 },
|
|
{ "perr_edma_input_fifo0", 7, 1 },
|
|
{ "perr_mgt_bar2_fifo", 6, 1 },
|
|
{ "perr_headersplit_fifo1", 5, 1 },
|
|
{ "perr_headersplit_fifo0", 4, 1 },
|
|
{ "perr_cim_fifo1", 3, 1 },
|
|
{ "perr_cim_fifo0", 2, 1 },
|
|
{ "perr_idma_switch_output_fifo1", 1, 1 },
|
|
{ "perr_idma_switch_output_fifo0", 0, 1 },
|
|
{ "SGE_DBFIFO_STATUS2", 0x1118, 0 },
|
|
{ "FL_Int_Thresh", 24, 4 },
|
|
{ "FL_Count", 14, 10 },
|
|
{ "HP_Int_Thresh", 10, 4 },
|
|
{ "HP_Count", 0, 10 },
|
|
{ "SGE_FETCH_BURST_MAX_0_AND_1", 0x111c, 0 },
|
|
{ "FetchBurstMax0", 16, 10 },
|
|
{ "FetchBurstMax1", 0, 10 },
|
|
{ "SGE_FETCH_BURST_MAX_2_AND_3", 0x1120, 0 },
|
|
{ "FetchBurstMax2", 16, 10 },
|
|
{ "FetchBurstMax3", 0, 10 },
|
|
{ "SGE_CONTROL2", 0x1124, 0 },
|
|
{ "uPFLCutoffDis", 21, 1 },
|
|
{ "RxCplSizeAutocorrect", 20, 1 },
|
|
{ "IdmaArbRoundRobin", 19, 1 },
|
|
{ "IngPackBoundary", 16, 3 },
|
|
{ "CGEN_Egress_Context", 15, 1 },
|
|
{ "CGEN_Ingress_Context", 14, 1 },
|
|
{ "CGEN_IDMA", 13, 1 },
|
|
{ "CGEN_DBP", 12, 1 },
|
|
{ "CGEN_EDMA", 11, 1 },
|
|
{ "VFIFO_Enable", 10, 1 },
|
|
{ "FLM_Reschedule_Mode", 9, 1 },
|
|
{ "HintDepthCtlFL", 4, 5 },
|
|
{ "Force_Ordering", 3, 1 },
|
|
{ "TX_Coalesce_Size", 2, 1 },
|
|
{ "Coal_Strict_CIM_Pri", 1, 1 },
|
|
{ "TX_Coalesce_Pri", 0, 1 },
|
|
{ "SGE_DEEP_SLEEP", 0x1128, 0 },
|
|
{ "IDMA1_Sleep_Status", 11, 1 },
|
|
{ "IDMA0_Sleep_Status", 10, 1 },
|
|
{ "IDMA1_Sleep_Req", 9, 1 },
|
|
{ "IDMA0_Sleep_Req", 8, 1 },
|
|
{ "EDMA3_Sleep_Status", 7, 1 },
|
|
{ "EDMA2_Sleep_Status", 6, 1 },
|
|
{ "EDMA1_Sleep_Status", 5, 1 },
|
|
{ "EDMA0_Sleep_Status", 4, 1 },
|
|
{ "EDMA3_Sleep_Req", 3, 1 },
|
|
{ "EDMA2_Sleep_Req", 2, 1 },
|
|
{ "EDMA1_Sleep_Req", 1, 1 },
|
|
{ "EDMA0_Sleep_Req", 0, 1 },
|
|
{ "SGE_DOORBELL_THROTTLE_THRESHOLD", 0x112c, 0 },
|
|
{ "Throttle_Threshold_fl", 16, 4 },
|
|
{ "Throttle_Threshold_hp", 12, 4 },
|
|
{ "Throttle_Threshold_lp", 0, 12 },
|
|
{ "SGE_DBP_FETCH_THRESHOLD", 0x1130, 0 },
|
|
{ "dbp_fetch_threshold_fl", 21, 4 },
|
|
{ "dbp_fetch_threshold_hp", 17, 4 },
|
|
{ "dbp_fetch_threshold_lp", 5, 12 },
|
|
{ "dbp_fetch_threshold_mode", 4, 1 },
|
|
{ "dbp_fetch_threshold_en3", 3, 1 },
|
|
{ "dbp_fetch_threshold_en2", 2, 1 },
|
|
{ "dbp_fetch_threshold_en1", 1, 1 },
|
|
{ "dbp_fetch_threshold_en0", 0, 1 },
|
|
{ "SGE_DBP_FETCH_THRESHOLD_QUEUE", 0x1134, 0 },
|
|
{ "dbp_fetch_threshold_iq1", 16, 16 },
|
|
{ "dbp_fetch_threshold_iq0", 0, 16 },
|
|
{ "SGE_DBVFIFO_BADDR", 0x1138, 0 },
|
|
{ "BaseAddr", 3, 29 },
|
|
{ "SGE_DBVFIFO_SIZE", 0x113c, 0 },
|
|
{ "Size", 6, 12 },
|
|
{ "SGE_DBFIFO_STATUS3", 0x1140, 0 },
|
|
{ "LP_Ptrs_Equal", 21, 1 },
|
|
{ "LP_Snaphot", 20, 1 },
|
|
{ "FL_Int_Thresh_Low", 16, 4 },
|
|
{ "HP_Int_Thresh_Low", 12, 4 },
|
|
{ "LP_Int_Thresh_Low", 0, 12 },
|
|
{ "SGE_CHANGESET", 0x1144, 0 },
|
|
{ "SGE_PC_RSP_ERROR", 0x1148, 0 },
|
|
{ "SGE_PC0_REQ_BIST_CMD", 0x1180, 0 },
|
|
{ "SGE_PC0_REQ_BIST_ERROR_CNT", 0x1184, 0 },
|
|
{ "SGE_PC1_REQ_BIST_CMD", 0x1190, 0 },
|
|
{ "SGE_PC1_REQ_BIST_ERROR_CNT", 0x1194, 0 },
|
|
{ "SGE_PC0_RSP_BIST_CMD", 0x11a0, 0 },
|
|
{ "SGE_PC0_RSP_BIST_ERROR_CNT", 0x11a4, 0 },
|
|
{ "SGE_PC1_RSP_BIST_CMD", 0x11b0, 0 },
|
|
{ "SGE_PC1_RSP_BIST_ERROR_CNT", 0x11b4, 0 },
|
|
{ "SGE_CTXT_CMD", 0x11fc, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Opcode", 28, 2 },
|
|
{ "CtxtType", 24, 2 },
|
|
{ "QID", 0, 17 },
|
|
{ "SGE_CTXT_DATA0", 0x1200, 0 },
|
|
{ "SGE_CTXT_DATA1", 0x1204, 0 },
|
|
{ "SGE_CTXT_DATA2", 0x1208, 0 },
|
|
{ "SGE_CTXT_DATA3", 0x120c, 0 },
|
|
{ "SGE_CTXT_DATA4", 0x1210, 0 },
|
|
{ "SGE_CTXT_DATA5", 0x1214, 0 },
|
|
{ "SGE_CTXT_DATA6", 0x1218, 0 },
|
|
{ "SGE_CTXT_DATA7", 0x121c, 0 },
|
|
{ "SGE_CTXT_MASK0", 0x1220, 0 },
|
|
{ "SGE_CTXT_MASK1", 0x1224, 0 },
|
|
{ "SGE_CTXT_MASK2", 0x1228, 0 },
|
|
{ "SGE_CTXT_MASK3", 0x122c, 0 },
|
|
{ "SGE_CTXT_MASK4", 0x1230, 0 },
|
|
{ "SGE_CTXT_MASK5", 0x1234, 0 },
|
|
{ "SGE_CTXT_MASK6", 0x1238, 0 },
|
|
{ "SGE_CTXT_MASK7", 0x123c, 0 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_0", 0x1280, 0 },
|
|
{ "CIM_WM", 24, 2 },
|
|
{ "debug_uP_SOP_cnt", 20, 4 },
|
|
{ "debug_uP_EOP_cnt", 16, 4 },
|
|
{ "debug_CIM_SOP1_cnt", 12, 4 },
|
|
{ "debug_CIM_EOP1_cnt", 8, 4 },
|
|
{ "debug_CIM_SOP0_cnt", 4, 4 },
|
|
{ "debug_CIM_EOP0_cnt", 0, 4 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_1", 0x1284, 0 },
|
|
{ "debug_T_Rx_SOP1_cnt", 28, 4 },
|
|
{ "debug_T_Rx_EOP1_cnt", 24, 4 },
|
|
{ "debug_T_Rx_SOP0_cnt", 20, 4 },
|
|
{ "debug_T_Rx_EOP0_cnt", 16, 4 },
|
|
{ "debug_U_Rx_SOP1_cnt", 12, 4 },
|
|
{ "debug_U_Rx_EOP1_cnt", 8, 4 },
|
|
{ "debug_U_Rx_SOP0_cnt", 4, 4 },
|
|
{ "debug_U_Rx_EOP0_cnt", 0, 4 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_2", 0x1288, 0 },
|
|
{ "debug_UD_Rx_SOP3_cnt", 28, 4 },
|
|
{ "debug_UD_Rx_EOP3_cnt", 24, 4 },
|
|
{ "debug_UD_Rx_SOP2_cnt", 20, 4 },
|
|
{ "debug_UD_Rx_EOP2_cnt", 16, 4 },
|
|
{ "debug_UD_Rx_SOP1_cnt", 12, 4 },
|
|
{ "debug_UD_Rx_EOP1_cnt", 8, 4 },
|
|
{ "debug_UD_Rx_SOP0_cnt", 4, 4 },
|
|
{ "debug_UD_Rx_EOP0_cnt", 0, 4 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_3", 0x128c, 0 },
|
|
{ "debug_U_Tx_SOP3_cnt", 28, 4 },
|
|
{ "debug_U_Tx_EOP3_cnt", 24, 4 },
|
|
{ "debug_U_Tx_SOP2_cnt", 20, 4 },
|
|
{ "debug_U_Tx_EOP2_cnt", 16, 4 },
|
|
{ "debug_U_Tx_SOP1_cnt", 12, 4 },
|
|
{ "debug_U_Tx_EOP1_cnt", 8, 4 },
|
|
{ "debug_U_Tx_SOP0_cnt", 4, 4 },
|
|
{ "debug_U_Tx_EOP0_cnt", 0, 4 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_4", 0x1290, 0 },
|
|
{ "debug_PC_Rsp_SOP1_cnt", 28, 4 },
|
|
{ "debug_PC_Rsp_EOP1_cnt", 24, 4 },
|
|
{ "debug_PC_Rsp_SOP0_cnt", 20, 4 },
|
|
{ "debug_PC_Rsp_EOP0_cnt", 16, 4 },
|
|
{ "debug_PC_Req_SOP1_cnt", 12, 4 },
|
|
{ "debug_PC_Req_EOP1_cnt", 8, 4 },
|
|
{ "debug_PC_Req_SOP0_cnt", 4, 4 },
|
|
{ "debug_PC_Req_EOP0_cnt", 0, 4 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_5", 0x1294, 0 },
|
|
{ "debug_PD_RdReq_SOP3_cnt", 28, 4 },
|
|
{ "debug_PD_RdReq_EOP3_cnt", 24, 4 },
|
|
{ "debug_PD_RdReq_SOP2_cnt", 20, 4 },
|
|
{ "debug_PD_RdReq_EOP2_cnt", 16, 4 },
|
|
{ "debug_PD_RdReq_SOP1_cnt", 12, 4 },
|
|
{ "debug_PD_RdReq_EOP1_cnt", 8, 4 },
|
|
{ "debug_PD_RdReq_SOP0_cnt", 4, 4 },
|
|
{ "debug_PD_RdReq_EOP0_cnt", 0, 4 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_6", 0x1298, 0 },
|
|
{ "debug_PD_RdRsp_SOP3_cnt", 28, 4 },
|
|
{ "debug_PD_RdRsp_EOP3_cnt", 24, 4 },
|
|
{ "debug_PD_RdRsp_SOP2_cnt", 20, 4 },
|
|
{ "debug_PD_RdRsp_EOP2_cnt", 16, 4 },
|
|
{ "debug_PD_RdRsp_SOP1_cnt", 12, 4 },
|
|
{ "debug_PD_RdRsp_EOP1_cnt", 8, 4 },
|
|
{ "debug_PD_RdRsp_SOP0_cnt", 4, 4 },
|
|
{ "debug_PD_RdRsp_EOP0_cnt", 0, 4 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_7", 0x129c, 0 },
|
|
{ "debug_PD_WrReq_SOP3_cnt", 28, 4 },
|
|
{ "debug_PD_WrReq_EOP3_cnt", 24, 4 },
|
|
{ "debug_PD_WrReq_SOP2_cnt", 20, 4 },
|
|
{ "debug_PD_WrReq_EOP2_cnt", 16, 4 },
|
|
{ "debug_PD_WrReq_SOP1_cnt", 12, 4 },
|
|
{ "debug_PD_WrReq_EOP1_cnt", 8, 4 },
|
|
{ "debug_PD_WrReq_SOP0_cnt", 4, 4 },
|
|
{ "debug_PD_WrReq_EOP0_cnt", 0, 4 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_8", 0x12a0, 0 },
|
|
{ "GlobalEnable_Off", 29, 1 },
|
|
{ "debug_CIM2SGE_RxAFull_d", 27, 2 },
|
|
{ "debug_CPLSW_CIM_TxAFull_d", 25, 2 },
|
|
{ "debug_uP_Full", 24, 1 },
|
|
{ "debug_M_rd_req_outstanding_PC", 23, 1 },
|
|
{ "debug_M_rd_req_outstanding_VFIFO", 22, 1 },
|
|
{ "debug_M_rd_req_outstanding_IMSG", 21, 1 },
|
|
{ "debug_M_rd_req_outstanding_CMARB", 20, 1 },
|
|
{ "debug_M_rd_req_outstanding_FLM", 19, 1 },
|
|
{ "debug_M_ReqVld", 18, 1 },
|
|
{ "debug_M_ReqRdy", 17, 1 },
|
|
{ "debug_M_RspVld", 16, 1 },
|
|
{ "debug_PD_WrReq_Int3_cnt", 12, 4 },
|
|
{ "debug_PD_WrReq_Int2_cnt", 8, 4 },
|
|
{ "debug_PD_WrReq_Int1_cnt", 4, 4 },
|
|
{ "debug_PD_WrReq_Int0_cnt", 0, 4 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_9", 0x12a4, 0 },
|
|
{ "debug_CPLSW_TP_Rx_SOP1_cnt", 28, 4 },
|
|
{ "debug_CPLSW_TP_Rx_EOP1_cnt", 24, 4 },
|
|
{ "debug_CPLSW_TP_Rx_SOP0_cnt", 20, 4 },
|
|
{ "debug_CPLSW_TP_Rx_EOP0_cnt", 16, 4 },
|
|
{ "debug_CPLSW_CIM_SOP1_cnt", 12, 4 },
|
|
{ "debug_CPLSW_CIM_EOP1_cnt", 8, 4 },
|
|
{ "debug_CPLSW_CIM_SOP0_cnt", 4, 4 },
|
|
{ "debug_CPLSW_CIM_EOP0_cnt", 0, 4 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_10", 0x12a8, 0 },
|
|
{ "debug_T_RxAFull_d", 30, 2 },
|
|
{ "debug_PD_RdRspAFull_d", 26, 4 },
|
|
{ "debug_PD_RdReqAFull_d", 22, 4 },
|
|
{ "debug_PD_WrReqAFull_d", 18, 4 },
|
|
{ "debug_PC_RspAFull_d", 15, 3 },
|
|
{ "debug_PC_ReqAFull_d", 12, 3 },
|
|
{ "debug_U_TxAFull_d", 8, 4 },
|
|
{ "debug_UD_RxAFull_d", 4, 4 },
|
|
{ "debug_U_RxAFull_d", 2, 2 },
|
|
{ "debug_CIM_AFull_d", 0, 2 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_11", 0x12ac, 0 },
|
|
{ "debug_flm_idma1_cache_data_active", 24, 1 },
|
|
{ "debug_flm_idma1_cache_hdr_active", 23, 1 },
|
|
{ "debug_flm_idma1_ctxt_data_active", 22, 1 },
|
|
{ "debug_flm_idma1_ctxt_hdr_active", 21, 1 },
|
|
{ "debug_st_flm_idma1_cache", 19, 2 },
|
|
{ "debug_st_flm_idma1_ctxt", 16, 3 },
|
|
{ "debug_flm_idma0_cache_data_active", 8, 1 },
|
|
{ "debug_flm_idma0_cache_hdr_active", 7, 1 },
|
|
{ "debug_flm_idma0_ctxt_data_active", 6, 1 },
|
|
{ "debug_flm_idma0_ctxt_hdr_active", 5, 1 },
|
|
{ "debug_st_flm_idma0_cache", 3, 2 },
|
|
{ "debug_st_flm_idma0_ctxt", 0, 3 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_12", 0x12b0, 0 },
|
|
{ "debug_CPLSW_SOP1_cnt", 28, 4 },
|
|
{ "debug_CPLSW_EOP1_cnt", 24, 4 },
|
|
{ "debug_CPLSW_SOP0_cnt", 20, 4 },
|
|
{ "debug_CPLSW_EOP0_cnt", 16, 4 },
|
|
{ "debug_PC_Rsp_SOP2_cnt", 12, 4 },
|
|
{ "debug_PC_Rsp_EOP2_cnt", 8, 4 },
|
|
{ "debug_PC_Req_SOP2_cnt", 4, 4 },
|
|
{ "debug_PC_Req_EOP2_cnt", 0, 4 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_13", 0x12b4, 0 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_14", 0x12b8, 0 },
|
|
{ "SGE_DEBUG_DATA_HIGH_INDEX_15", 0x12bc, 0 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_0", 0x12c0, 0 },
|
|
{ "debug_st_idma1_flm_req", 29, 3 },
|
|
{ "debug_st_idma0_flm_req", 26, 3 },
|
|
{ "debug_st_imsg_ctxt", 23, 3 },
|
|
{ "debug_st_imsg", 18, 5 },
|
|
{ "debug_st_idma1_ialn", 16, 2 },
|
|
{ "debug_st_idma1_idma_sm", 9, 6 },
|
|
{ "debug_st_idma0_ialn", 7, 2 },
|
|
{ "debug_st_idma0_idma_sm", 0, 6 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_1", 0x12c4, 0 },
|
|
{ "debug_itp_empty", 12, 6 },
|
|
{ "debug_itp_expired", 6, 6 },
|
|
{ "debug_itp_pause", 5, 1 },
|
|
{ "debug_itp_del_done", 4, 1 },
|
|
{ "debug_itp_add_done", 3, 1 },
|
|
{ "debug_itp_evr_state", 0, 3 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_2", 0x12c8, 0 },
|
|
{ "debug_st_dbp_thread2_cimfl", 25, 5 },
|
|
{ "debug_st_dbp_thread2_main", 20, 5 },
|
|
{ "debug_st_dbp_thread1_cimfl", 15, 5 },
|
|
{ "debug_st_dbp_thread1_main", 10, 5 },
|
|
{ "debug_st_dbp_thread0_cimfl", 5, 5 },
|
|
{ "debug_st_dbp_thread0_main", 0, 5 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_3", 0x12cc, 0 },
|
|
{ "debug_st_dbp_upcp_main", 14, 5 },
|
|
{ "debug_st_dbp_dbfifo_main", 13, 1 },
|
|
{ "debug_st_dbp_ctxt", 10, 3 },
|
|
{ "debug_st_dbp_thread3_cimfl", 5, 5 },
|
|
{ "debug_st_dbp_thread3_main", 0, 5 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_4", 0x12d0, 0 },
|
|
{ "debug_st_edma3_align_sub", 29, 3 },
|
|
{ "debug_st_edma3_align", 27, 2 },
|
|
{ "debug_st_edma3_req", 24, 3 },
|
|
{ "debug_st_edma2_align_sub", 21, 3 },
|
|
{ "debug_st_edma2_align", 19, 2 },
|
|
{ "debug_st_edma2_req", 16, 3 },
|
|
{ "debug_st_edma1_align_sub", 13, 3 },
|
|
{ "debug_st_edma1_align", 11, 2 },
|
|
{ "debug_st_edma1_req", 8, 3 },
|
|
{ "debug_st_edma0_align_sub", 5, 3 },
|
|
{ "debug_st_edma0_align", 3, 2 },
|
|
{ "debug_st_edma0_req", 0, 3 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_5", 0x12d4, 0 },
|
|
{ "debug_st_flm_dbptr", 30, 2 },
|
|
{ "debug_flm_cache_locked_count", 23, 7 },
|
|
{ "debug_flm_cache_agent", 20, 3 },
|
|
{ "debug_st_flm_cache", 16, 4 },
|
|
{ "debug_flm_dbptr_cidx_stall", 12, 1 },
|
|
{ "debug_flm_dbptr_qid", 0, 12 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_6", 0x12d8, 0 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_7", 0x12dc, 0 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_8", 0x12e0, 0 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_9", 0x12e4, 0 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_10", 0x12e8, 0 },
|
|
{ "debug_imsg_cpl", 16, 8 },
|
|
{ "debug_imsg_qid", 0, 16 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_11", 0x12ec, 0 },
|
|
{ "debug_idma1_qid", 16, 16 },
|
|
{ "debug_idma0_qid", 0, 16 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_12", 0x12f0, 0 },
|
|
{ "debug_idma1_flm_req_qid", 16, 16 },
|
|
{ "debug_idma0_flm_req_qid", 0, 16 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_13", 0x12f4, 0 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_14", 0x12f8, 0 },
|
|
{ "SGE_DEBUG_DATA_LOW_INDEX_15", 0x12fc, 0 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1300, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1308, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1310, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1318, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1320, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1328, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1330, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1338, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1340, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1348, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1350, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1358, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1360, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1368, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1370, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1378, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1380, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1388, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1390, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1398, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13a0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13a8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13b0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13b8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13c0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13c8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13d0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13d8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13e0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13e8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13f0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x13f8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1400, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1408, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1410, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1418, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1420, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1428, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1430, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1438, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1440, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1448, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1450, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1458, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1460, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1468, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1470, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1478, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1480, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1488, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1490, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1498, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14a0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14a8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14b0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14b8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14c0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14c8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14d0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14d8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14e0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14e8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14f0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x14f8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1500, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1508, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1510, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1518, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1520, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1528, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1530, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1538, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1540, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1548, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1550, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1558, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1560, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1568, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1570, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1578, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1580, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1588, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1590, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1598, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15a0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15a8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15b0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15b8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15c0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15c8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15d0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15d8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15e0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15e8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15f0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x15f8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1600, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1608, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1610, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1618, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1620, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1628, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1630, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1638, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1640, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1648, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1650, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1658, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1660, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1668, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1670, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1678, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1680, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1688, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1690, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1698, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16a0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16a8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16b0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16b8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16c0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16c8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16d0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16d8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16e0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16e8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16f0, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x16f8, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1700, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1708, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1710, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1718, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1720, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1728, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1730, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_HIGH", 0x1738, 0 },
|
|
{ "Egress_Size", 27, 5 },
|
|
{ "Egress_Base", 10, 17 },
|
|
{ "Ingress2_Size", 5, 5 },
|
|
{ "Ingress1_Size", 0, 5 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1304, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x130c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1314, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x131c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1324, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x132c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1334, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x133c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1344, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x134c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1354, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x135c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1364, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x136c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1374, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x137c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1384, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x138c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1394, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x139c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13a4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13ac, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13b4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13bc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13c4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13cc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13d4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13dc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13e4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13ec, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13f4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x13fc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1404, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x140c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1414, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x141c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1424, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x142c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1434, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x143c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1444, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x144c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1454, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x145c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1464, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x146c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1474, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x147c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1484, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x148c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1494, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x149c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14a4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14ac, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14b4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14bc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14c4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14cc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14d4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14dc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14e4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14ec, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14f4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x14fc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1504, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x150c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1514, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x151c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1524, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x152c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1534, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x153c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1544, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x154c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1554, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x155c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1564, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x156c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1574, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x157c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1584, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x158c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1594, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x159c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15a4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15ac, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15b4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15bc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15c4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15cc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15d4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15dc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15e4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15ec, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15f4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x15fc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1604, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x160c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1614, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x161c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1624, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x162c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1634, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x163c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1644, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x164c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1654, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x165c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1664, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x166c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1674, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x167c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1684, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x168c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1694, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x169c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16a4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16ac, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16b4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16bc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16c4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16cc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16d4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16dc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16e4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16ec, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16f4, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x16fc, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1704, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x170c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1714, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x171c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1724, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x172c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x1734, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_QUEUE_BASE_MAP_LOW", 0x173c, 0 },
|
|
{ "Ingress2_Base", 16, 16 },
|
|
{ "Ingress1_Base", 0, 16 },
|
|
{ "SGE_LA_RDPTR_0", 0x1800, 0 },
|
|
{ "SGE_LA_RDDATA_0", 0x1804, 0 },
|
|
{ "SGE_LA_WRPTR_0", 0x1808, 0 },
|
|
{ "SGE_LA_RESERVED_0", 0x180c, 0 },
|
|
{ "SGE_LA_RDPTR_1", 0x1810, 0 },
|
|
{ "SGE_LA_RDDATA_1", 0x1814, 0 },
|
|
{ "SGE_LA_WRPTR_1", 0x1818, 0 },
|
|
{ "SGE_LA_RESERVED_1", 0x181c, 0 },
|
|
{ "SGE_LA_RDPTR_2", 0x1820, 0 },
|
|
{ "SGE_LA_RDDATA_2", 0x1824, 0 },
|
|
{ "SGE_LA_WRPTR_2", 0x1828, 0 },
|
|
{ "SGE_LA_RESERVED_2", 0x182c, 0 },
|
|
{ "SGE_LA_RDPTR_3", 0x1830, 0 },
|
|
{ "SGE_LA_RDDATA_3", 0x1834, 0 },
|
|
{ "SGE_LA_WRPTR_3", 0x1838, 0 },
|
|
{ "SGE_LA_RESERVED_3", 0x183c, 0 },
|
|
{ "SGE_LA_RDPTR_4", 0x1840, 0 },
|
|
{ "SGE_LA_RDDATA_4", 0x1844, 0 },
|
|
{ "SGE_LA_WRPTR_4", 0x1848, 0 },
|
|
{ "SGE_LA_RESERVED_4", 0x184c, 0 },
|
|
{ "SGE_LA_RDPTR_5", 0x1850, 0 },
|
|
{ "SGE_LA_RDDATA_5", 0x1854, 0 },
|
|
{ "SGE_LA_WRPTR_5", 0x1858, 0 },
|
|
{ "SGE_LA_RESERVED_5", 0x185c, 0 },
|
|
{ "SGE_LA_RDPTR_6", 0x1860, 0 },
|
|
{ "SGE_LA_RDDATA_6", 0x1864, 0 },
|
|
{ "SGE_LA_WRPTR_6", 0x1868, 0 },
|
|
{ "SGE_LA_RESERVED_6", 0x186c, 0 },
|
|
{ "SGE_LA_RDPTR_7", 0x1870, 0 },
|
|
{ "SGE_LA_RDDATA_7", 0x1874, 0 },
|
|
{ "SGE_LA_WRPTR_7", 0x1878, 0 },
|
|
{ "SGE_LA_RESERVED_7", 0x187c, 0 },
|
|
{ "SGE_LA_RDPTR_8", 0x1880, 0 },
|
|
{ "SGE_LA_RDDATA_8", 0x1884, 0 },
|
|
{ "SGE_LA_WRPTR_8", 0x1888, 0 },
|
|
{ "SGE_LA_RESERVED_8", 0x188c, 0 },
|
|
{ "SGE_LA_RDPTR_9", 0x1890, 0 },
|
|
{ "SGE_LA_RDDATA_9", 0x1894, 0 },
|
|
{ "SGE_LA_WRPTR_9", 0x1898, 0 },
|
|
{ "SGE_LA_RESERVED_9", 0x189c, 0 },
|
|
{ "SGE_LA_RDPTR_10", 0x18a0, 0 },
|
|
{ "SGE_LA_RDDATA_10", 0x18a4, 0 },
|
|
{ "SGE_LA_WRPTR_10", 0x18a8, 0 },
|
|
{ "SGE_LA_RESERVED_10", 0x18ac, 0 },
|
|
{ "SGE_LA_RDPTR_11", 0x18b0, 0 },
|
|
{ "SGE_LA_RDDATA_11", 0x18b4, 0 },
|
|
{ "SGE_LA_WRPTR_11", 0x18b8, 0 },
|
|
{ "SGE_LA_RESERVED_11", 0x18bc, 0 },
|
|
{ "SGE_LA_RDPTR_12", 0x18c0, 0 },
|
|
{ "SGE_LA_RDDATA_12", 0x18c4, 0 },
|
|
{ "SGE_LA_WRPTR_12", 0x18c8, 0 },
|
|
{ "SGE_LA_RESERVED_12", 0x18cc, 0 },
|
|
{ "SGE_LA_RDPTR_13", 0x18d0, 0 },
|
|
{ "SGE_LA_RDDATA_13", 0x18d4, 0 },
|
|
{ "SGE_LA_WRPTR_13", 0x18d8, 0 },
|
|
{ "SGE_LA_RESERVED_13", 0x18dc, 0 },
|
|
{ "SGE_LA_RDPTR_14", 0x18e0, 0 },
|
|
{ "SGE_LA_RDDATA_14", 0x18e4, 0 },
|
|
{ "SGE_LA_WRPTR_14", 0x18e8, 0 },
|
|
{ "SGE_LA_RESERVED_14", 0x18ec, 0 },
|
|
{ "SGE_LA_RDPTR_15", 0x18f0, 0 },
|
|
{ "SGE_LA_RDDATA_15", 0x18f4, 0 },
|
|
{ "SGE_LA_WRPTR_15", 0x18f8, 0 },
|
|
{ "SGE_LA_RESERVED_15", 0x18fc, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_pcie_regs[] = {
|
|
{ "PCIE_INT_ENABLE", 0x3000, 0 },
|
|
{ "IPGrpPerr", 31, 1 },
|
|
{ "NonFatalErr", 30, 1 },
|
|
{ "RdRspErr", 29, 1 },
|
|
{ "TRGT1GrpPerr", 28, 1 },
|
|
{ "IPSOTPerr", 27, 1 },
|
|
{ "IPRetryPerr", 26, 1 },
|
|
{ "IPRxDataGrpPerr", 25, 1 },
|
|
{ "IPRxHdrGrpPerr", 24, 1 },
|
|
{ "PIOTagQPerr", 23, 1 },
|
|
{ "MAGrpPerr", 22, 1 },
|
|
{ "VFIDPerr", 21, 1 },
|
|
{ "FIDPerr", 20, 1 },
|
|
{ "CfgSnpPerr", 19, 1 },
|
|
{ "HRspPerr", 18, 1 },
|
|
{ "HReqRdPerr", 17, 1 },
|
|
{ "HReqWrPerr", 16, 1 },
|
|
{ "DRspPerr", 15, 1 },
|
|
{ "DReqRdPerr", 14, 1 },
|
|
{ "DReqWrPerr", 13, 1 },
|
|
{ "CRspPerr", 12, 1 },
|
|
{ "CReqRdPerr", 11, 1 },
|
|
{ "MstTagQPerr", 10, 1 },
|
|
{ "TgtTagQPerr", 9, 1 },
|
|
{ "PIOReqGrpPerr", 8, 1 },
|
|
{ "PIOCplGrpPerr", 7, 1 },
|
|
{ "MSIXDIPerr", 6, 1 },
|
|
{ "MSIXDataPerr", 5, 1 },
|
|
{ "MSIXAddrHPerr", 4, 1 },
|
|
{ "MSIXAddrLPerr", 3, 1 },
|
|
{ "MSIXStiPerr", 2, 1 },
|
|
{ "MstTimeoutPerr", 1, 1 },
|
|
{ "MstGrpPerr", 0, 1 },
|
|
{ "PCIE_INT_CAUSE", 0x3004, 0 },
|
|
{ "IPGrpPerr", 31, 1 },
|
|
{ "NonFatalErr", 30, 1 },
|
|
{ "RdRspErr", 29, 1 },
|
|
{ "TRGT1GrpPerr", 28, 1 },
|
|
{ "IPSOTPerr", 27, 1 },
|
|
{ "IPRetryPerr", 26, 1 },
|
|
{ "IPRxDataGrpPerr", 25, 1 },
|
|
{ "IPRxHdrGrpPerr", 24, 1 },
|
|
{ "PIOTagQPerr", 23, 1 },
|
|
{ "MAGrpPerr", 22, 1 },
|
|
{ "VFIDPerr", 21, 1 },
|
|
{ "FIDPerr", 20, 1 },
|
|
{ "CfgSnpPerr", 19, 1 },
|
|
{ "HRspPerr", 18, 1 },
|
|
{ "HReqRdPerr", 17, 1 },
|
|
{ "HReqWrPerr", 16, 1 },
|
|
{ "DRspPerr", 15, 1 },
|
|
{ "DReqRdPerr", 14, 1 },
|
|
{ "DReqWrPerr", 13, 1 },
|
|
{ "CRspPerr", 12, 1 },
|
|
{ "CReqRdPerr", 11, 1 },
|
|
{ "MstTagQPerr", 10, 1 },
|
|
{ "TgtTagQPerr", 9, 1 },
|
|
{ "PIOReqGrpPerr", 8, 1 },
|
|
{ "PIOCplGrpPerr", 7, 1 },
|
|
{ "MSIXDIPerr", 6, 1 },
|
|
{ "MSIXDataPerr", 5, 1 },
|
|
{ "MSIXAddrHPerr", 4, 1 },
|
|
{ "MSIXAddrLPerr", 3, 1 },
|
|
{ "MSIXStiPerr", 2, 1 },
|
|
{ "MstTimeoutPerr", 1, 1 },
|
|
{ "MstGrpPerr", 0, 1 },
|
|
{ "PCIE_PERR_ENABLE", 0x3008, 0 },
|
|
{ "IPGrpPerr", 31, 1 },
|
|
{ "TRGT1GrpPerr", 28, 1 },
|
|
{ "IPSOTPerr", 27, 1 },
|
|
{ "IPRetryPerr", 26, 1 },
|
|
{ "IPRxDataGrpPerr", 25, 1 },
|
|
{ "IPRxHdrGrpPerr", 24, 1 },
|
|
{ "PIOTagQPerr", 23, 1 },
|
|
{ "MAGrpPerr", 22, 1 },
|
|
{ "VFIDPerr", 21, 1 },
|
|
{ "FIDPerr", 20, 1 },
|
|
{ "CfgSnpPerr", 19, 1 },
|
|
{ "HRspPerr", 18, 1 },
|
|
{ "HReqRdPerr", 17, 1 },
|
|
{ "HReqWrPerr", 16, 1 },
|
|
{ "DRspPerr", 15, 1 },
|
|
{ "DReqRdPerr", 14, 1 },
|
|
{ "DReqWrPerr", 13, 1 },
|
|
{ "CRspPerr", 12, 1 },
|
|
{ "CReqRdPerr", 11, 1 },
|
|
{ "MstTagQPerr", 10, 1 },
|
|
{ "TgtTagQPerr", 9, 1 },
|
|
{ "PIOReqGrpPerr", 8, 1 },
|
|
{ "PIOCplGrpPerr", 7, 1 },
|
|
{ "MSIXDIPerr", 6, 1 },
|
|
{ "MSIXDataPerr", 5, 1 },
|
|
{ "MSIXAddrHPerr", 4, 1 },
|
|
{ "MSIXAddrLPerr", 3, 1 },
|
|
{ "MSIXStiPerr", 2, 1 },
|
|
{ "MstTimeoutPerr", 1, 1 },
|
|
{ "MstGrpPerr", 0, 1 },
|
|
{ "PCIE_PERR_INJECT", 0x300c, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "IDE", 0, 1 },
|
|
{ "PCIE_NONFAT_ERR", 0x3010, 0 },
|
|
{ "MAReqTimeout", 29, 1 },
|
|
{ "TRGT1BARTypeErr", 28, 1 },
|
|
{ "MAExtraRspErr", 27, 1 },
|
|
{ "MARspTimeout", 26, 1 },
|
|
{ "INTVFAllMSIDisErr", 25, 1 },
|
|
{ "INTVFRangeErr", 24, 1 },
|
|
{ "INTPLIRspErr", 23, 1 },
|
|
{ "MEMReqRdTagErr", 22, 1 },
|
|
{ "CFGInitDoneErr", 21, 1 },
|
|
{ "BAR2Timeout", 20, 1 },
|
|
{ "VPDTimeout", 19, 1 },
|
|
{ "MEMRspRdTagErr", 18, 1 },
|
|
{ "MEMRspWrTagErr", 17, 1 },
|
|
{ "PIORspRdTagErr", 16, 1 },
|
|
{ "PIORspWrTagErr", 15, 1 },
|
|
{ "DBITimeout", 14, 1 },
|
|
{ "PIOUnAlindWr", 13, 1 },
|
|
{ "BAR2RdErr", 12, 1 },
|
|
{ "MAWrEOPErr", 11, 1 },
|
|
{ "MARdEOPErr", 10, 1 },
|
|
{ "RdRspErr", 9, 1 },
|
|
{ "VPDRspErr", 8, 1 },
|
|
{ "MemReq", 4, 1 },
|
|
{ "PIOReq", 3, 1 },
|
|
{ "BAR2Req", 2, 1 },
|
|
{ "CfgSnp", 0, 1 },
|
|
{ "PCIE_CFG", 0x3014, 0 },
|
|
{ "PIOStopEn", 31, 1 },
|
|
{ "DiagCtrlBus", 28, 3 },
|
|
{ "IPPerrEn", 27, 1 },
|
|
{ "CfgdExtTagEn", 26, 1 },
|
|
{ "CfgdMaxPyldSz", 23, 3 },
|
|
{ "CfgdMaxRdReqSz", 20, 3 },
|
|
{ "DCAEn", 17, 1 },
|
|
{ "CMDReqPriority", 16, 1 },
|
|
{ "VPDReqProtect", 14, 2 },
|
|
{ "DroppedRdRspData", 12, 1 },
|
|
{ "AI_INTX_ReAssertEn", 11, 1 },
|
|
{ "AutoTxnDisable", 10, 1 },
|
|
{ "TC0_Stamp", 9, 1 },
|
|
{ "AI_TCVal", 6, 3 },
|
|
{ "DMAStopEn", 5, 1 },
|
|
{ "DevStateRstMode", 4, 1 },
|
|
{ "LinkReqRstPCIeCRstMode", 3, 1 },
|
|
{ "LinkDnRstEn", 0, 1 },
|
|
{ "PCIE_CFG2", 0x3018, 0 },
|
|
{ "VPDTimer", 16, 16 },
|
|
{ "BAR2Timer", 4, 12 },
|
|
{ "MstReqRdRRASimple", 3, 1 },
|
|
{ "TotMaxTag", 0, 2 },
|
|
{ "PCIE_CFG3", 0x301c, 0 },
|
|
{ "AutoPIOCookieMatch", 6, 1 },
|
|
{ "FLRPndCplMode", 4, 2 },
|
|
{ "HMADCASTFirstOnly", 2, 1 },
|
|
{ "CMDDCASTFirstOnly", 1, 1 },
|
|
{ "DMADCASTFirstOnly", 0, 1 },
|
|
{ "PCIE_CFG4", 0x3020, 0 },
|
|
{ "L1ClkRemovalEn", 17, 1 },
|
|
{ "ReadyEnterL23", 16, 1 },
|
|
{ "ExitL1", 12, 1 },
|
|
{ "EnterL1", 8, 1 },
|
|
{ "GenPME", 0, 8 },
|
|
{ "PCIE_CFG5", 0x3024, 0 },
|
|
{ "EnableSKPParityFix", 2, 1 },
|
|
{ "EnableL2EntryInL1", 1, 1 },
|
|
{ "HoldCplEnteringL1", 0, 1 },
|
|
{ "PCIE_CFG6", 0x3028, 0 },
|
|
{ "PERstTimerCount", 12, 14 },
|
|
{ "PERstTimeout", 8, 1 },
|
|
{ "PERstTimer", 0, 4 },
|
|
{ "PCIE_CFG_SPACE_REQ", 0x3060, 0 },
|
|
{ "Enable", 30, 1 },
|
|
{ "AI", 29, 1 },
|
|
{ "CS2", 28, 1 },
|
|
{ "WrBE", 24, 4 },
|
|
{ "VFVld", 23, 1 },
|
|
{ "RVF", 16, 7 },
|
|
{ "PF", 12, 3 },
|
|
{ "ExtRegister", 8, 4 },
|
|
{ "Register", 0, 8 },
|
|
{ "PCIE_CFG_SPACE_DATA", 0x3064, 0 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3068, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x306c, 0 },
|
|
{ "MemOfst", 7, 25 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3070, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x3074, 0 },
|
|
{ "MemOfst", 7, 25 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3078, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x307c, 0 },
|
|
{ "MemOfst", 7, 25 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3080, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x3084, 0 },
|
|
{ "MemOfst", 7, 25 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3088, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x308c, 0 },
|
|
{ "MemOfst", 7, 25 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3090, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x3094, 0 },
|
|
{ "MemOfst", 7, 25 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x3098, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x309c, 0 },
|
|
{ "MemOfst", 7, 25 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_MEM_ACCESS_BASE_WIN", 0x30a0, 0 },
|
|
{ "PCIEOfst", 10, 22 },
|
|
{ "BIR", 8, 2 },
|
|
{ "Window", 0, 8 },
|
|
{ "PCIE_MEM_ACCESS_OFFSET", 0x30a4, 0 },
|
|
{ "MemOfst", 7, 25 },
|
|
{ "PFNum", 0, 3 },
|
|
{ "PCIE_MAILBOX_BASE_WIN", 0x30a8, 0 },
|
|
{ "PCIEOfst", 6, 26 },
|
|
{ "BIR", 4, 2 },
|
|
{ "Window", 0, 2 },
|
|
{ "PCIE_MAILBOX_OFFSET", 0x30ac, 0 },
|
|
{ "MemOfst", 7, 25 },
|
|
{ "PCIE_MA_CTRL", 0x30b0, 0 },
|
|
{ "TagFree", 29, 1 },
|
|
{ "MaxRspCnt", 24, 5 },
|
|
{ "MaxReqCnt", 16, 7 },
|
|
{ "MaxReqSize", 8, 3 },
|
|
{ "MaxTag", 0, 5 },
|
|
{ "PCIE_FW", 0x30b8, 0 },
|
|
{ "PCIE_FW_PF", 0x30bc, 0 },
|
|
{ "PCIE_FW_PF", 0x30c0, 0 },
|
|
{ "PCIE_FW_PF", 0x30c4, 0 },
|
|
{ "PCIE_FW_PF", 0x30c8, 0 },
|
|
{ "PCIE_FW_PF", 0x30cc, 0 },
|
|
{ "PCIE_FW_PF", 0x30d0, 0 },
|
|
{ "PCIE_FW_PF", 0x30d4, 0 },
|
|
{ "PCIE_FW_PF", 0x30d8, 0 },
|
|
{ "PCIE_PIO_PAUSE", 0x30dc, 0 },
|
|
{ "PIOPauseDone", 31, 1 },
|
|
{ "MSTPauseDone", 30, 1 },
|
|
{ "PauseTime", 4, 24 },
|
|
{ "MSTPause", 1, 1 },
|
|
{ "PIOPause", 0, 1 },
|
|
{ "PCIE_MA_STAT", 0x30e0, 0 },
|
|
{ "PCIE_STATIC_CFG1", 0x30e4, 0 },
|
|
{ "AUXPOWER_DETECTED", 27, 1 },
|
|
{ "PCIE_STATIC_CFG2", 0x30e8, 0 },
|
|
{ "PL_CONTROL", 16, 16 },
|
|
{ "STATIC_SPARE3", 0, 14 },
|
|
{ "PCIE_DBG_INDIR_REQ", 0x30ec, 0 },
|
|
{ "Enable", 31, 1 },
|
|
{ "AI", 30, 1 },
|
|
{ "Pointer", 8, 16 },
|
|
{ "Select", 0, 4 },
|
|
{ "PCIE_DBG_INDIR_DATA_0", 0x30f0, 0 },
|
|
{ "PCIE_DBG_INDIR_DATA_1", 0x30f4, 0 },
|
|
{ "PCIE_DBG_INDIR_DATA_2", 0x30f8, 0 },
|
|
{ "PCIE_DBG_INDIR_DATA_3", 0x30fc, 0 },
|
|
{ "PCIE_PF_INT_CFG", 0x3140, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_PF_INT_CFG2", 0x3144, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_PF_INT_CFG", 0x3148, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_PF_INT_CFG2", 0x314c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_PF_INT_CFG", 0x3150, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_PF_INT_CFG2", 0x3154, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_PF_INT_CFG", 0x3158, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_PF_INT_CFG2", 0x315c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_PF_INT_CFG", 0x3160, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_PF_INT_CFG2", 0x3164, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_PF_INT_CFG", 0x3168, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_PF_INT_CFG2", 0x316c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_PF_INT_CFG", 0x3170, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_PF_INT_CFG2", 0x3174, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_PF_INT_CFG", 0x3178, 0 },
|
|
{ "PBAOfst", 28, 4 },
|
|
{ "TABOfst", 24, 4 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_PF_INT_CFG2", 0x317c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3180, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3184, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3188, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x318c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3190, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3194, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3198, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x319c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31a0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31a4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31a8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31ac, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31b0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31b4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31b8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31bc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31c0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31c4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31c8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31cc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31d0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31d4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31d8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31dc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31e0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31e4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31e8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31ec, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31f0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31f4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x31f8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x31fc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3200, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3204, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3208, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x320c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3210, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3214, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3218, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x321c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3220, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3224, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3228, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x322c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3230, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3234, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3238, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x323c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3240, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3244, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3248, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x324c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3250, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3254, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3258, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x325c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3260, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3264, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3268, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x326c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3270, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3274, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3278, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x327c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3280, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3284, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3288, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x328c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3290, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3294, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3298, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x329c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32a0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32a4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32a8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32ac, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32b0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32b4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32b8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32bc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32c0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32c4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32c8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32cc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32d0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32d4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32d8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32dc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32e0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32e4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32e8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32ec, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32f0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32f4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x32f8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x32fc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3300, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3304, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3308, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x330c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3310, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3314, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3318, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x331c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3320, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3324, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3328, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x332c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3330, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3334, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3338, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x333c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3340, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3344, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3348, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x334c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3350, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3354, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3358, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x335c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3360, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3364, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3368, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x336c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3370, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3374, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3378, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x337c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3380, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3384, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3388, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x338c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3390, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3394, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3398, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x339c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33a0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33a4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33a8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33ac, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33b0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33b4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33b8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33bc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33c0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33c4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33c8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33cc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33d0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33d4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33d8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33dc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33e0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33e4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33e8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33ec, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33f0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33f4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x33f8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x33fc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3400, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3404, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3408, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x340c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3410, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3414, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3418, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x341c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3420, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3424, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3428, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x342c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3430, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3434, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3438, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x343c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3440, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3444, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3448, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x344c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3450, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3454, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3458, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x345c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3460, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3464, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3468, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x346c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3470, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3474, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3478, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x347c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3480, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3484, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3488, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x348c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3490, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3494, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3498, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x349c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34a0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34a4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34a8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34ac, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34b0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34b4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34b8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34bc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34c0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34c4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34c8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34cc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34d0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34d4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34d8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34dc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34e0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34e4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34e8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34ec, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34f0, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34f4, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x34f8, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x34fc, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3500, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3504, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3508, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x350c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3510, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3514, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3518, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x351c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3520, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3524, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3528, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x352c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3530, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3534, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3538, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x353c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3540, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3544, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3548, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x354c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3550, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3554, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3558, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x355c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3560, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3564, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3568, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x356c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3570, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x3574, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_VF_INT_CFG", 0x3578, 0 },
|
|
{ "VecNum", 12, 10 },
|
|
{ "VecBase", 0, 11 },
|
|
{ "PCIE_VF_INT_CFG2", 0x357c, 0 },
|
|
{ "SendFLRRsp", 31, 1 },
|
|
{ "ImmFLRRsp", 24, 1 },
|
|
{ "TxnDisable", 20, 1 },
|
|
{ "PCIE_PF_MSI_EN", 0x35a8, 0 },
|
|
{ "PCIE_VF_MSI_EN_0", 0x35ac, 0 },
|
|
{ "PCIE_VF_MSI_EN_1", 0x35b0, 0 },
|
|
{ "PCIE_VF_MSI_EN_2", 0x35b4, 0 },
|
|
{ "PCIE_VF_MSI_EN_3", 0x35b8, 0 },
|
|
{ "PCIE_PF_MSIX_EN", 0x35bc, 0 },
|
|
{ "PCIE_VF_MSIX_EN_0", 0x35c0, 0 },
|
|
{ "PCIE_VF_MSIX_EN_1", 0x35c4, 0 },
|
|
{ "PCIE_VF_MSIX_EN_2", 0x35c8, 0 },
|
|
{ "PCIE_VF_MSIX_EN_3", 0x35cc, 0 },
|
|
{ "PCIE_FID_VFID_SEL", 0x35ec, 0 },
|
|
{ "PCIE_FID_VFID", 0x3600, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3604, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3608, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x360c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3610, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3614, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3618, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x361c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3620, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3624, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3628, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x362c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3630, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3634, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3638, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x363c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3640, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3644, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3648, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x364c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3650, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3654, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3658, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x365c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3660, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3664, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3668, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x366c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3670, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3674, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3678, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x367c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3680, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3684, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3688, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x368c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3690, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3694, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3698, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x369c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x36fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3700, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3704, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3708, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x370c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3710, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3714, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3718, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x371c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3720, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3724, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3728, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x372c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3730, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3734, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3738, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x373c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3740, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3744, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3748, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x374c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3750, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3754, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3758, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x375c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3760, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3764, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3768, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x376c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3770, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3774, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3778, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x377c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3780, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3784, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3788, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x378c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3790, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3794, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3798, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x379c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x37fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3800, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3804, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3808, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x380c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3810, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3814, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3818, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x381c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3820, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3824, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3828, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x382c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3830, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3834, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3838, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x383c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3840, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3844, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3848, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x384c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3850, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3854, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3858, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x385c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3860, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3864, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3868, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x386c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3870, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3874, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3878, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x387c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3880, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3884, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3888, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x388c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3890, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3894, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3898, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x389c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x38fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3900, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3904, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3908, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x390c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3910, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3914, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3918, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x391c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3920, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3924, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3928, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x392c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3930, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3934, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3938, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x393c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3940, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3944, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3948, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x394c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3950, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3954, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3958, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x395c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3960, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3964, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3968, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x396c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3970, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3974, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3978, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x397c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3980, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3984, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3988, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x398c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3990, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3994, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3998, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x399c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x39fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a00, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a04, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a08, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a0c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a10, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a14, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a18, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a1c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a20, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a24, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a28, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a2c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a30, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a34, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a38, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a3c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a40, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a44, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a48, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a4c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a50, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a54, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a58, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a5c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a60, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a64, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a68, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a6c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a70, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a74, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a78, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a7c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a80, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a84, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a88, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a8c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a90, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a94, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a98, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3a9c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3aa0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3aa4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3aa8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3aac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ab0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ab4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ab8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3abc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ac0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ac4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ac8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3acc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ad0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ad4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ad8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3adc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ae0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ae4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ae8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3aec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3af0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3af4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3af8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3afc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b00, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b04, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b08, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b0c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b10, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b14, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b18, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b1c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b20, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b24, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b28, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b2c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b30, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b34, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b38, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b3c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b40, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b44, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b48, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b4c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b50, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b54, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b58, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b5c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b60, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b64, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b68, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b6c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b70, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b74, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b78, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b7c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b80, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b84, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b88, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b8c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b90, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b94, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b98, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3b9c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ba0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ba4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ba8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3bac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3bb0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3bb4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3bb8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3bbc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3bc0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3bc4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3bc8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3bcc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3bd0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3bd4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3bd8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3bdc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3be0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3be4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3be8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3bec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3bf0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3bf4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3bf8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3bfc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c00, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c04, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c08, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c0c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c10, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c14, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c18, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c1c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c20, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c24, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c28, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c2c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c30, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c34, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c38, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c3c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c40, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c44, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c48, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c4c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c50, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c54, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c58, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c5c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c60, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c64, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c68, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c6c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c70, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c74, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c78, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c7c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c80, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c84, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c88, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c8c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c90, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c94, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c98, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3c9c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ca0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ca4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ca8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3cac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3cb0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3cb4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3cb8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3cbc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3cc0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3cc4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3cc8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ccc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3cd0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3cd4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3cd8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3cdc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ce0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ce4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ce8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3cec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3cf0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3cf4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3cf8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3cfc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d00, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d04, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d08, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d0c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d10, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d14, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d18, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d1c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d20, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d24, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d28, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d2c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d30, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d34, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d38, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d3c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d40, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d44, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d48, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d4c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d50, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d54, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d58, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d5c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d60, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d64, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d68, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d6c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d70, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d74, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d78, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d7c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d80, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d84, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d88, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d8c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d90, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d94, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d98, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3d9c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3da0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3da4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3da8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3dac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3db0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3db4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3db8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3dbc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3dc0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3dc4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3dc8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3dcc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3dd0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3dd4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3dd8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ddc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3de0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3de4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3de8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3dec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3df0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3df4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3df8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3dfc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e00, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e04, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e08, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e0c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e10, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e14, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e18, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e1c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e20, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e24, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e28, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e2c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e30, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e34, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e38, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e3c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e40, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e44, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e48, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e4c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e50, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e54, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e58, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e5c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e60, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e64, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e68, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e6c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e70, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e74, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e78, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e7c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e80, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e84, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e88, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e8c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e90, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e94, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e98, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3e9c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ea0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ea4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ea8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3eac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3eb0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3eb4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3eb8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ebc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ec0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ec4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ec8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ecc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ed0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ed4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ed8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3edc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ee0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ee4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ee8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3eec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ef0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ef4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ef8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3efc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f00, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f04, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f08, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f0c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f10, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f14, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f18, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f1c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f20, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f24, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f28, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f2c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f30, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f34, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f38, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f3c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f40, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f44, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f48, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f4c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f50, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f54, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f58, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f5c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f60, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f64, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f68, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f6c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f70, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f74, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f78, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f7c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f80, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f84, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f88, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f8c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f90, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f94, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f98, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3f9c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fa0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fa4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fa8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fb0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fb4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fb8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fbc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fc0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fc4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fc8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fcc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fd0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fd4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fd8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fdc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fe0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fe4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fe8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3fec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ff0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ff4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ff8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x3ffc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4000, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4004, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4008, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x400c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4010, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4014, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4018, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x401c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4020, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4024, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4028, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x402c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4030, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4034, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4038, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x403c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4040, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4044, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4048, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x404c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4050, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4054, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4058, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x405c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4060, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4064, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4068, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x406c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4070, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4074, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4078, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x407c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4080, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4084, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4088, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x408c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4090, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4094, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4098, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x409c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x40fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4100, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4104, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4108, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x410c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4110, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4114, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4118, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x411c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4120, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4124, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4128, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x412c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4130, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4134, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4138, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x413c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4140, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4144, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4148, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x414c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4150, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4154, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4158, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x415c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4160, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4164, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4168, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x416c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4170, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4174, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4178, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x417c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4180, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4184, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4188, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x418c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4190, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4194, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4198, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x419c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x41fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4200, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4204, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4208, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x420c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4210, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4214, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4218, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x421c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4220, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4224, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4228, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x422c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4230, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4234, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4238, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x423c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4240, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4244, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4248, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x424c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4250, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4254, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4258, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x425c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4260, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4264, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4268, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x426c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4270, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4274, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4278, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x427c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4280, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4284, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4288, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x428c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4290, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4294, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4298, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x429c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x42fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4300, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4304, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4308, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x430c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4310, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4314, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4318, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x431c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4320, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4324, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4328, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x432c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4330, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4334, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4338, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x433c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4340, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4344, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4348, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x434c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4350, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4354, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4358, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x435c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4360, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4364, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4368, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x436c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4370, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4374, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4378, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x437c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4380, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4384, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4388, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x438c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4390, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4394, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4398, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x439c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x43fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4400, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4404, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4408, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x440c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4410, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4414, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4418, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x441c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4420, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4424, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4428, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x442c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4430, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4434, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4438, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x443c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4440, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4444, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4448, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x444c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4450, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4454, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4458, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x445c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4460, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4464, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4468, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x446c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4470, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4474, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4478, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x447c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4480, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4484, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4488, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x448c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4490, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4494, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4498, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x449c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x44fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4500, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4504, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4508, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x450c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4510, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4514, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4518, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x451c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4520, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4524, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4528, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x452c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4530, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4534, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4538, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x453c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4540, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4544, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4548, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x454c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4550, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4554, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4558, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x455c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4560, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4564, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4568, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x456c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4570, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4574, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4578, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x457c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4580, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4584, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4588, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x458c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4590, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4594, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4598, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x459c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x45fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4600, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4604, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4608, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x460c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4610, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4614, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4618, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x461c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4620, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4624, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4628, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x462c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4630, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4634, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4638, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x463c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4640, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4644, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4648, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x464c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4650, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4654, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4658, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x465c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4660, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4664, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4668, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x466c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4670, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4674, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4678, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x467c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4680, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4684, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4688, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x468c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4690, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4694, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4698, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x469c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x46fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4700, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4704, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4708, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x470c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4710, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4714, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4718, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x471c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4720, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4724, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4728, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x472c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4730, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4734, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4738, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x473c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4740, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4744, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4748, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x474c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4750, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4754, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4758, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x475c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4760, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4764, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4768, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x476c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4770, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4774, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4778, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x477c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4780, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4784, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4788, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x478c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4790, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4794, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4798, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x479c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x47fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4800, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4804, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4808, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x480c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4810, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4814, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4818, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x481c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4820, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4824, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4828, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x482c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4830, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4834, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4838, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x483c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4840, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4844, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4848, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x484c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4850, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4854, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4858, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x485c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4860, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4864, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4868, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x486c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4870, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4874, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4878, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x487c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4880, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4884, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4888, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x488c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4890, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4894, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4898, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x489c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x48fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4900, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4904, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4908, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x490c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4910, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4914, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4918, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x491c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4920, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4924, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4928, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x492c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4930, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4934, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4938, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x493c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4940, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4944, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4948, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x494c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4950, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4954, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4958, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x495c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4960, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4964, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4968, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x496c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4970, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4974, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4978, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x497c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4980, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4984, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4988, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x498c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4990, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4994, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4998, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x499c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x49fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a00, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a04, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a08, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a0c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a10, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a14, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a18, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a1c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a20, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a24, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a28, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a2c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a30, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a34, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a38, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a3c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a40, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a44, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a48, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a4c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a50, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a54, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a58, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a5c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a60, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a64, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a68, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a6c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a70, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a74, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a78, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a7c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a80, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a84, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a88, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a8c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a90, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a94, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a98, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4a9c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4aa0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4aa4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4aa8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4aac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ab0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ab4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ab8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4abc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ac0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ac4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ac8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4acc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ad0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ad4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ad8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4adc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ae0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ae4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ae8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4aec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4af0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4af4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4af8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4afc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b00, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b04, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b08, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b0c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b10, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b14, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b18, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b1c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b20, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b24, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b28, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b2c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b30, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b34, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b38, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b3c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b40, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b44, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b48, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b4c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b50, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b54, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b58, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b5c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b60, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b64, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b68, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b6c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b70, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b74, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b78, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b7c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b80, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b84, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b88, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b8c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b90, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b94, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b98, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4b9c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ba0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ba4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ba8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4bac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4bb0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4bb4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4bb8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4bbc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4bc0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4bc4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4bc8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4bcc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4bd0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4bd4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4bd8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4bdc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4be0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4be4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4be8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4bec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4bf0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4bf4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4bf8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4bfc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c00, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c04, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c08, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c0c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c10, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c14, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c18, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c1c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c20, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c24, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c28, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c2c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c30, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c34, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c38, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c3c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c40, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c44, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c48, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c4c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c50, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c54, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c58, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c5c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c60, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c64, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c68, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c6c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c70, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c74, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c78, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c7c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c80, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c84, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c88, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c8c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c90, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c94, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c98, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4c9c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ca0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ca4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ca8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4cac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4cb0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4cb4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4cb8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4cbc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4cc0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4cc4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4cc8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ccc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4cd0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4cd4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4cd8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4cdc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ce0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ce4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ce8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4cec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4cf0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4cf4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4cf8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4cfc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d00, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d04, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d08, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d0c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d10, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d14, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d18, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d1c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d20, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d24, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d28, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d2c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d30, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d34, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d38, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d3c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d40, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d44, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d48, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d4c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d50, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d54, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d58, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d5c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d60, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d64, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d68, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d6c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d70, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d74, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d78, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d7c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d80, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d84, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d88, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d8c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d90, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d94, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d98, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4d9c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4da0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4da4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4da8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4dac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4db0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4db4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4db8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4dbc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4dc0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4dc4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4dc8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4dcc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4dd0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4dd4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4dd8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ddc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4de0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4de4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4de8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4dec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4df0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4df4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4df8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4dfc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e00, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e04, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e08, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e0c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e10, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e14, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e18, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e1c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e20, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e24, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e28, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e2c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e30, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e34, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e38, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e3c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e40, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e44, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e48, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e4c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e50, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e54, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e58, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e5c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e60, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e64, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e68, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e6c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e70, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e74, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e78, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e7c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e80, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e84, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e88, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e8c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e90, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e94, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e98, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4e9c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ea0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ea4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ea8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4eac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4eb0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4eb4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4eb8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ebc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ec0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ec4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ec8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ecc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ed0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ed4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ed8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4edc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ee0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ee4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ee8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4eec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ef0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ef4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ef8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4efc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f00, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f04, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f08, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f0c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f10, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f14, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f18, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f1c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f20, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f24, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f28, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f2c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f30, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f34, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f38, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f3c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f40, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f44, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f48, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f4c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f50, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f54, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f58, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f5c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f60, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f64, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f68, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f6c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f70, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f74, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f78, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f7c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f80, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f84, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f88, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f8c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f90, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f94, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f98, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4f9c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fa0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fa4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fa8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fb0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fb4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fb8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fbc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fc0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fc4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fc8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fcc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fd0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fd4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fd8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fdc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fe0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fe4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fe8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4fec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ff0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ff4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ff8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x4ffc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5000, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5004, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5008, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x500c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5010, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5014, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5018, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x501c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5020, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5024, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5028, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x502c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5030, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5034, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5038, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x503c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5040, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5044, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5048, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x504c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5050, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5054, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5058, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x505c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5060, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5064, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5068, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x506c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5070, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5074, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5078, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x507c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5080, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5084, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5088, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x508c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5090, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5094, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5098, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x509c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x50fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5100, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5104, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5108, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x510c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5110, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5114, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5118, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x511c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5120, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5124, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5128, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x512c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5130, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5134, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5138, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x513c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5140, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5144, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5148, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x514c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5150, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5154, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5158, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x515c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5160, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5164, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5168, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x516c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5170, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5174, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5178, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x517c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5180, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5184, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5188, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x518c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5190, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5194, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5198, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x519c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x51fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5200, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5204, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5208, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x520c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5210, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5214, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5218, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x521c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5220, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5224, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5228, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x522c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5230, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5234, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5238, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x523c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5240, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5244, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5248, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x524c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5250, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5254, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5258, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x525c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5260, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5264, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5268, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x526c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5270, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5274, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5278, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x527c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5280, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5284, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5288, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x528c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5290, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5294, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5298, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x529c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x52fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5300, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5304, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5308, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x530c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5310, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5314, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5318, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x531c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5320, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5324, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5328, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x532c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5330, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5334, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5338, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x533c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5340, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5344, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5348, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x534c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5350, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5354, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5358, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x535c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5360, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5364, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5368, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x536c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5370, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5374, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5378, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x537c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5380, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5384, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5388, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x538c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5390, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5394, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5398, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x539c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x53fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5400, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5404, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5408, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x540c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5410, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5414, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5418, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x541c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5420, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5424, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5428, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x542c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5430, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5434, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5438, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x543c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5440, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5444, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5448, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x544c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5450, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5454, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5458, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x545c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5460, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5464, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5468, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x546c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5470, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5474, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5478, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x547c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5480, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5484, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5488, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x548c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5490, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5494, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5498, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x549c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x54fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5500, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5504, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5508, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x550c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5510, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5514, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5518, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x551c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5520, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5524, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5528, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x552c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5530, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5534, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5538, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x553c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5540, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5544, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5548, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x554c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5550, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5554, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5558, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x555c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5560, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5564, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5568, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x556c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5570, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5574, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5578, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x557c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5580, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5584, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5588, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x558c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5590, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5594, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x5598, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x559c, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55a0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55a4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55a8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55ac, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55b0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55b4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55b8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55bc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55c0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55c4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55c8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55cc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55d0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55d4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55d8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55dc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55e0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55e4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55e8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55ec, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55f0, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55f4, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55f8, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_FID_VFID", 0x55fc, 0 },
|
|
{ "Select", 30, 2 },
|
|
{ "IDO", 24, 1 },
|
|
{ "VFID", 16, 8 },
|
|
{ "TC", 11, 3 },
|
|
{ "VFVld", 10, 1 },
|
|
{ "PF", 7, 3 },
|
|
{ "RVF", 0, 7 },
|
|
{ "PCIE_COOKIE_STAT", 0x5600, 0 },
|
|
{ "CookieB", 16, 10 },
|
|
{ "CookieA", 0, 10 },
|
|
{ "PCIE_COOKIE_STAT", 0x5604, 0 },
|
|
{ "CookieB", 16, 10 },
|
|
{ "CookieA", 0, 10 },
|
|
{ "PCIE_COOKIE_STAT", 0x5608, 0 },
|
|
{ "CookieB", 16, 10 },
|
|
{ "CookieA", 0, 10 },
|
|
{ "PCIE_COOKIE_STAT", 0x560c, 0 },
|
|
{ "CookieB", 16, 10 },
|
|
{ "CookieA", 0, 10 },
|
|
{ "PCIE_COOKIE_STAT", 0x5610, 0 },
|
|
{ "CookieB", 16, 10 },
|
|
{ "CookieA", 0, 10 },
|
|
{ "PCIE_COOKIE_STAT", 0x5614, 0 },
|
|
{ "CookieB", 16, 10 },
|
|
{ "CookieA", 0, 10 },
|
|
{ "PCIE_COOKIE_STAT", 0x5618, 0 },
|
|
{ "CookieB", 16, 10 },
|
|
{ "CookieA", 0, 10 },
|
|
{ "PCIE_COOKIE_STAT", 0x561c, 0 },
|
|
{ "CookieB", 16, 10 },
|
|
{ "CookieA", 0, 10 },
|
|
{ "PCIE_FLR_PIO", 0x5620, 0 },
|
|
{ "RcvdBAR2Cookie", 24, 8 },
|
|
{ "RcvdMARspCookie", 16, 8 },
|
|
{ "RcvdPIORspCookie", 8, 8 },
|
|
{ "ExpdCookie", 0, 8 },
|
|
{ "PCIE_FLR_PIO2", 0x5624, 0 },
|
|
{ "RcvdMAReqCookie", 16, 8 },
|
|
{ "RcvdPIOReqCookie", 8, 8 },
|
|
{ "PCIE_VC0_CDTS0", 0x56cc, 0 },
|
|
{ "CPLD0", 20, 12 },
|
|
{ "PH0", 12, 8 },
|
|
{ "PD0", 0, 12 },
|
|
{ "PCIE_VC0_CDTS1", 0x56d0, 0 },
|
|
{ "CPLH0", 20, 8 },
|
|
{ "NPH0", 12, 8 },
|
|
{ "NPD0", 0, 12 },
|
|
{ "PCIE_VC1_CDTS0", 0x56d4, 0 },
|
|
{ "CPLD1", 20, 12 },
|
|
{ "PH1", 12, 8 },
|
|
{ "PD1", 0, 12 },
|
|
{ "PCIE_VC1_CDTS1", 0x56d8, 0 },
|
|
{ "CPLH1", 20, 8 },
|
|
{ "NPH1", 12, 8 },
|
|
{ "NPD1", 0, 12 },
|
|
{ "PCIE_FLR_PF_STATUS", 0x56dc, 0 },
|
|
{ "PCIE_FLR_VF0_STATUS", 0x56e0, 0 },
|
|
{ "PCIE_FLR_VF1_STATUS", 0x56e4, 0 },
|
|
{ "PCIE_FLR_VF2_STATUS", 0x56e8, 0 },
|
|
{ "PCIE_FLR_VF3_STATUS", 0x56ec, 0 },
|
|
{ "PCIE_STAT", 0x56f4, 0 },
|
|
{ "PM_Status", 24, 8 },
|
|
{ "PM_CurrentState", 20, 3 },
|
|
{ "LTSSMEnable", 12, 1 },
|
|
{ "StateCfgInitF", 4, 7 },
|
|
{ "StateCfgInit", 0, 4 },
|
|
{ "PCIE_CRS", 0x56f8, 0 },
|
|
{ "PCIE_LTSSM", 0x56fc, 0 },
|
|
{ "PCIE_PF_CFG", 0x1e040, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1e044, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1e04c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1e440, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1e444, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1e44c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1e840, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1e844, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1e84c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1ec40, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1ec44, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1ec4c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1f040, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1f044, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1f04c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1f440, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1f444, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1f44c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1f840, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1f844, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1f84c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_PF_CFG", 0x1fc40, 0 },
|
|
{ "INTXStat", 16, 1 },
|
|
{ "AIVec", 4, 10 },
|
|
{ "D3HotEn", 1, 1 },
|
|
{ "CLIDecEn", 0, 1 },
|
|
{ "PCIE_PF_CLI", 0x1fc44, 0 },
|
|
{ "PCIE_PF_EXPROM_OFST", 0x1fc4c, 0 },
|
|
{ "Offset", 10, 14 },
|
|
{ "PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER", 0x5700, 0 },
|
|
{ "Replay_Time_Limit", 16, 16 },
|
|
{ "Ack_Latency_Timer_Limit", 0, 16 },
|
|
{ "PCIE_CORE_VENDOR_SPECIFIC_DLLP", 0x5704, 0 },
|
|
{ "PCIE_CORE_PORT_FORCE_LINK", 0x5708, 0 },
|
|
{ "Low_Power_Entrance_Count", 24, 8 },
|
|
{ "Link_State", 16, 6 },
|
|
{ "Force_Link", 15, 1 },
|
|
{ "Link_Number", 0, 8 },
|
|
{ "PCIE_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL", 0x570c, 0 },
|
|
{ "Enter_ASPM_L1_wo_L0s", 30, 1 },
|
|
{ "L1_Entrance_Latency", 27, 3 },
|
|
{ "L0s_Entrance_Latency", 24, 3 },
|
|
{ "Common_Clock_N_FTS", 16, 8 },
|
|
{ "N_FTS", 8, 8 },
|
|
{ "Ack_Frequency", 0, 8 },
|
|
{ "PCIE_CORE_PORT_LINK_CONTROL", 0x5710, 0 },
|
|
{ "Crosslink_Active", 23, 1 },
|
|
{ "Crosslink_Enable", 22, 1 },
|
|
{ "Link_Mode_Enable", 16, 6 },
|
|
{ "Fast_Link_Mode", 7, 1 },
|
|
{ "DLL_Link_Enable", 5, 1 },
|
|
{ "Reset_Assert", 3, 1 },
|
|
{ "Loopback_Enable", 2, 1 },
|
|
{ "Scramble_Disable", 1, 1 },
|
|
{ "Vendor_Specific_DLLP_Request", 0, 1 },
|
|
{ "PCIE_CORE_LANE_SKEW", 0x5714, 0 },
|
|
{ "Disable_DeSkew", 31, 1 },
|
|
{ "Ack_Nak_Disable", 25, 1 },
|
|
{ "Flow_Control_Disable", 24, 1 },
|
|
{ "Insert_TxSkew", 0, 24 },
|
|
{ "PCIE_CORE_SYMBOL_NUMBER", 0x5718, 0 },
|
|
{ "Flow_Control_Timer_Modifier", 24, 5 },
|
|
{ "Ack_Nak_Timer_Modifier", 19, 5 },
|
|
{ "Replay_Timer_Modifier", 14, 5 },
|
|
{ "MaxFunc", 0, 3 },
|
|
{ "PCIE_CORE_SYMBOL_TIMER_FILTER_MASK1", 0x571c, 0 },
|
|
{ "Mask_RADM_Filter", 16, 16 },
|
|
{ "Disable_FC_Watchdog", 15, 1 },
|
|
{ "SKP_Interval", 0, 11 },
|
|
{ "PCIE_CORE_FILTER_MASK2", 0x5720, 0 },
|
|
{ "PCIE_CORE_DEBUG_0", 0x5728, 0 },
|
|
{ "PCIE_CORE_DEBUG_1", 0x572c, 0 },
|
|
{ "PCIE_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS", 0x5730, 0 },
|
|
{ "TxPH_FC", 12, 8 },
|
|
{ "TxPD_FC", 0, 12 },
|
|
{ "PCIE_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS", 0x5734, 0 },
|
|
{ "TxNPH_FC", 12, 8 },
|
|
{ "TxNPD_FC", 0, 12 },
|
|
{ "PCIE_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS", 0x5738, 0 },
|
|
{ "TxCPLH_FC", 12, 8 },
|
|
{ "TxCPLD_FC", 0, 12 },
|
|
{ "PCIE_CORE_QUEUE_STATUS", 0x573c, 0 },
|
|
{ "RxQueue_Not_Empty", 2, 1 },
|
|
{ "TxRetryBuf_Not_Empty", 1, 1 },
|
|
{ "RxTLP_FC_Not_Returned", 0, 1 },
|
|
{ "PCIE_CORE_VC_TRANSMIT_ARBITRATION_1", 0x5740, 0 },
|
|
{ "VC3_WRR", 24, 8 },
|
|
{ "VC2_WRR", 16, 8 },
|
|
{ "VC1_WRR", 8, 8 },
|
|
{ "VC0_WRR", 0, 8 },
|
|
{ "PCIE_CORE_VC_TRANSMIT_ARBITRATION_2", 0x5744, 0 },
|
|
{ "VC7_WRR", 24, 8 },
|
|
{ "VC6_WRR", 16, 8 },
|
|
{ "VC5_WRR", 8, 8 },
|
|
{ "VC4_WRR", 0, 8 },
|
|
{ "PCIE_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL", 0x5748, 0 },
|
|
{ "VC0_Rx_Ordering", 31, 1 },
|
|
{ "VC0_TLP_Ordering", 30, 1 },
|
|
{ "VC0_PTLP_Queue_Mode", 21, 3 },
|
|
{ "VC0_PH_Credits", 12, 8 },
|
|
{ "VC0_PD_Credits", 0, 12 },
|
|
{ "PCIE_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL", 0x574c, 0 },
|
|
{ "VC0_NPTLP_Queue_Mode", 21, 3 },
|
|
{ "VC0_NPH_Credits", 12, 8 },
|
|
{ "VC0_NPD_Credits", 0, 12 },
|
|
{ "PCIE_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL", 0x5750, 0 },
|
|
{ "VC0_CPLTLP_Queue_Mode", 21, 3 },
|
|
{ "VC0_CPLH_Credits", 12, 8 },
|
|
{ "VC0_CPLD_Credits", 0, 12 },
|
|
{ "PCIE_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL", 0x5754, 0 },
|
|
{ "VC1_TLP_Ordering", 30, 1 },
|
|
{ "VC1_PTLP_Queue_Mode", 21, 3 },
|
|
{ "VC1_PH_Credits", 12, 8 },
|
|
{ "VC1_PD_Credits", 0, 12 },
|
|
{ "PCIE_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL", 0x5758, 0 },
|
|
{ "VC1_NPTLP_Queue_Mode", 21, 3 },
|
|
{ "VC1_NPH_Credits", 12, 8 },
|
|
{ "VC1_NPD_Credits", 0, 12 },
|
|
{ "PCIE_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL", 0x575c, 0 },
|
|
{ "VC1_CPLTLP_Queue_Mode", 21, 3 },
|
|
{ "VC1_CPLH_Credits", 12, 8 },
|
|
{ "VC1_CPLD_Credits", 0, 12 },
|
|
{ "PCIE_CORE_LINK_WIDTH_SPEED_CHANGE", 0x580c, 0 },
|
|
{ "Sel_DeEmphasis", 20, 1 },
|
|
{ "TxCmplRcv", 19, 1 },
|
|
{ "PhyTxSwing", 18, 1 },
|
|
{ "DirSpdChange", 17, 1 },
|
|
{ "Num_Lanes", 8, 9 },
|
|
{ "NFTS_Gen2_3", 0, 8 },
|
|
{ "PCIE_CORE_PHY_STATUS", 0x5810, 0 },
|
|
{ "PCIE_CORE_PHY_CONTROL", 0x5814, 0 },
|
|
{ "PCIE_CORE_GEN3_CONTROL", 0x5890, 0 },
|
|
{ "DC_Balance_Disable", 18, 1 },
|
|
{ "DLLP_Delay_Disable", 17, 1 },
|
|
{ "Eql_Disable", 16, 1 },
|
|
{ "Eql_Redo_Disable", 11, 1 },
|
|
{ "Eql_EIEOS_CntRst_Disable", 10, 1 },
|
|
{ "Eql_PH2_PH3_Disable", 9, 1 },
|
|
{ "Disable_Scrambler", 8, 1 },
|
|
{ "PCIE_CORE_GEN3_EQ_FS_LF", 0x5894, 0 },
|
|
{ "Full_Swing", 6, 6 },
|
|
{ "Low_Frequency", 0, 6 },
|
|
{ "PCIE_CORE_GEN3_EQ_PRESET_COEFF", 0x5898, 0 },
|
|
{ "PostCursor", 12, 6 },
|
|
{ "Cursor", 6, 6 },
|
|
{ "PreCursor", 0, 6 },
|
|
{ "PCIE_CORE_GEN3_EQ_PRESET_INDEX", 0x589c, 0 },
|
|
{ "PCIE_CORE_GEN3_EQ_STATUS", 0x58a4, 0 },
|
|
{ "PCIE_CORE_GEN3_EQ_CONTROL", 0x58a8, 0 },
|
|
{ "Include_Initial_FOM", 24, 1 },
|
|
{ "Preset_Request_Vector", 8, 16 },
|
|
{ "Phase23_2ms_Timeout_Disable", 5, 1 },
|
|
{ "After24ms", 4, 1 },
|
|
{ "Feedback_Mode", 0, 4 },
|
|
{ "PCIE_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK", 0x58ac, 0 },
|
|
{ "WinAperture_CPlus1", 14, 4 },
|
|
{ "WinAperture_CMins1", 10, 4 },
|
|
{ "Convergence_WinDepth", 5, 5 },
|
|
{ "EQMasterPhase_MinTime", 0, 5 },
|
|
{ "PCIE_CORE_PIPE_CONTROL", 0x58b8, 0 },
|
|
{ "PCIE_CORE_DBI_RO_WE", 0x58bc, 0 },
|
|
{ "PCIE_DMA_CFG", 0x5940, 0 },
|
|
{ "MaxPyldSize", 28, 3 },
|
|
{ "MaxReqCnt", 20, 8 },
|
|
{ "MaxRdReqSize", 17, 3 },
|
|
{ "MaxRspCnt", 8, 9 },
|
|
{ "SeqChkDis", 7, 1 },
|
|
{ "MinTag", 0, 7 },
|
|
{ "PCIE_DMA_STAT", 0x5944, 0 },
|
|
{ "RspCnt", 20, 12 },
|
|
{ "RdReqCnt", 12, 8 },
|
|
{ "WrReqCnt", 0, 11 },
|
|
{ "PCIE_DMA_STAT2", 0x5948, 0 },
|
|
{ "CookieCnt", 24, 4 },
|
|
{ "RdSeqNumUpdCnt", 20, 4 },
|
|
{ "SIReqCnt", 16, 4 },
|
|
{ "WrEOPMatchSOP", 12, 1 },
|
|
{ "WrSOPCnt", 8, 4 },
|
|
{ "RdSOPCnt", 0, 8 },
|
|
{ "PCIE_DMA_STAT3", 0x594c, 0 },
|
|
{ "AtmReqSOPCnt", 24, 8 },
|
|
{ "AtmEOPMatchSOP", 17, 1 },
|
|
{ "RspEOPMatchSOP", 16, 1 },
|
|
{ "RspErrCnt", 8, 8 },
|
|
{ "RspSOPCnt", 0, 8 },
|
|
{ "PCIE_DMA_CFG", 0x5950, 0 },
|
|
{ "MaxPyldSize", 28, 3 },
|
|
{ "MaxReqCnt", 20, 8 },
|
|
{ "MaxRdReqSize", 17, 3 },
|
|
{ "MaxRspCnt", 8, 9 },
|
|
{ "SeqChkDis", 7, 1 },
|
|
{ "MinTag", 0, 7 },
|
|
{ "PCIE_DMA_STAT", 0x5954, 0 },
|
|
{ "RspCnt", 20, 12 },
|
|
{ "RdReqCnt", 12, 8 },
|
|
{ "WrReqCnt", 0, 11 },
|
|
{ "PCIE_DMA_STAT2", 0x5958, 0 },
|
|
{ "CookieCnt", 24, 4 },
|
|
{ "RdSeqNumUpdCnt", 20, 4 },
|
|
{ "SIReqCnt", 16, 4 },
|
|
{ "WrEOPMatchSOP", 12, 1 },
|
|
{ "WrSOPCnt", 8, 4 },
|
|
{ "RdSOPCnt", 0, 8 },
|
|
{ "PCIE_DMA_STAT3", 0x595c, 0 },
|
|
{ "AtmReqSOPCnt", 24, 8 },
|
|
{ "AtmEOPMatchSOP", 17, 1 },
|
|
{ "RspEOPMatchSOP", 16, 1 },
|
|
{ "RspErrCnt", 8, 8 },
|
|
{ "RspSOPCnt", 0, 8 },
|
|
{ "PCIE_DMA_CFG", 0x5960, 0 },
|
|
{ "MaxPyldSize", 28, 3 },
|
|
{ "MaxReqCnt", 20, 8 },
|
|
{ "MaxRdReqSize", 17, 3 },
|
|
{ "MaxRspCnt", 8, 9 },
|
|
{ "SeqChkDis", 7, 1 },
|
|
{ "MinTag", 0, 7 },
|
|
{ "PCIE_DMA_STAT", 0x5964, 0 },
|
|
{ "RspCnt", 20, 12 },
|
|
{ "RdReqCnt", 12, 8 },
|
|
{ "WrReqCnt", 0, 11 },
|
|
{ "PCIE_DMA_STAT2", 0x5968, 0 },
|
|
{ "CookieCnt", 24, 4 },
|
|
{ "RdSeqNumUpdCnt", 20, 4 },
|
|
{ "SIReqCnt", 16, 4 },
|
|
{ "WrEOPMatchSOP", 12, 1 },
|
|
{ "WrSOPCnt", 8, 4 },
|
|
{ "RdSOPCnt", 0, 8 },
|
|
{ "PCIE_DMA_STAT3", 0x596c, 0 },
|
|
{ "AtmReqSOPCnt", 24, 8 },
|
|
{ "AtmEOPMatchSOP", 17, 1 },
|
|
{ "RspEOPMatchSOP", 16, 1 },
|
|
{ "RspErrCnt", 8, 8 },
|
|
{ "RspSOPCnt", 0, 8 },
|
|
{ "PCIE_DMA_CFG", 0x5970, 0 },
|
|
{ "MaxPyldSize", 28, 3 },
|
|
{ "MaxReqCnt", 20, 8 },
|
|
{ "MaxRdReqSize", 17, 3 },
|
|
{ "MaxRspCnt", 8, 9 },
|
|
{ "SeqChkDis", 7, 1 },
|
|
{ "MinTag", 0, 7 },
|
|
{ "PCIE_DMA_STAT", 0x5974, 0 },
|
|
{ "RspCnt", 20, 12 },
|
|
{ "RdReqCnt", 12, 8 },
|
|
{ "WrReqCnt", 0, 11 },
|
|
{ "PCIE_DMA_STAT2", 0x5978, 0 },
|
|
{ "CookieCnt", 24, 4 },
|
|
{ "RdSeqNumUpdCnt", 20, 4 },
|
|
{ "SIReqCnt", 16, 4 },
|
|
{ "WrEOPMatchSOP", 12, 1 },
|
|
{ "WrSOPCnt", 8, 4 },
|
|
{ "RdSOPCnt", 0, 8 },
|
|
{ "PCIE_DMA_STAT3", 0x597c, 0 },
|
|
{ "AtmReqSOPCnt", 24, 8 },
|
|
{ "AtmEOPMatchSOP", 17, 1 },
|
|
{ "RspEOPMatchSOP", 16, 1 },
|
|
{ "RspErrCnt", 8, 8 },
|
|
{ "RspSOPCnt", 0, 8 },
|
|
{ "PCIE_CMD_CFG", 0x5980, 0 },
|
|
{ "MaxRdReqSize", 17, 3 },
|
|
{ "MaxRspCnt", 8, 8 },
|
|
{ "UseCmdPool", 7, 1 },
|
|
{ "MinTag", 0, 7 },
|
|
{ "PCIE_CMD_STAT", 0x5984, 0 },
|
|
{ "RspCnt", 20, 11 },
|
|
{ "RdReqCnt", 12, 5 },
|
|
{ "PCIE_CMD_STAT2", 0x5988, 0 },
|
|
{ "PCIE_CMD_STAT3", 0x598c, 0 },
|
|
{ "RspEOPMatchSOP", 16, 1 },
|
|
{ "RspErrCnt", 8, 8 },
|
|
{ "RspSOPCnt", 0, 8 },
|
|
{ "PCIE_CMD_CFG", 0x5990, 0 },
|
|
{ "MaxRdReqSize", 17, 3 },
|
|
{ "MaxRspCnt", 8, 8 },
|
|
{ "UseCmdPool", 7, 1 },
|
|
{ "MinTag", 0, 7 },
|
|
{ "PCIE_CMD_STAT", 0x5994, 0 },
|
|
{ "RspCnt", 20, 11 },
|
|
{ "RdReqCnt", 12, 5 },
|
|
{ "PCIE_CMD_STAT2", 0x5998, 0 },
|
|
{ "PCIE_CMD_STAT3", 0x599c, 0 },
|
|
{ "RspEOPMatchSOP", 16, 1 },
|
|
{ "RspErrCnt", 8, 8 },
|
|
{ "RspSOPCnt", 0, 8 },
|
|
{ "PCIE_CMD_CFG", 0x59a0, 0 },
|
|
{ "MaxRdReqSize", 17, 3 },
|
|
{ "MaxRspCnt", 8, 8 },
|
|
{ "UseCmdPool", 7, 1 },
|
|
{ "MinTag", 0, 7 },
|
|
{ "PCIE_CMD_STAT", 0x59a4, 0 },
|
|
{ "RspCnt", 20, 11 },
|
|
{ "RdReqCnt", 12, 5 },
|
|
{ "PCIE_CMD_STAT2", 0x59a8, 0 },
|
|
{ "PCIE_CMD_STAT3", 0x59ac, 0 },
|
|
{ "RspEOPMatchSOP", 16, 1 },
|
|
{ "RspErrCnt", 8, 8 },
|
|
{ "RspSOPCnt", 0, 8 },
|
|
{ "PCIE_HMA_CFG", 0x59b0, 0 },
|
|
{ "MaxPyldSize", 28, 3 },
|
|
{ "MaxReqCnt", 20, 5 },
|
|
{ "MaxRdReqSize", 17, 3 },
|
|
{ "MaxRspCnt", 8, 5 },
|
|
{ "SeqChkDis", 7, 1 },
|
|
{ "MinTag", 0, 7 },
|
|
{ "PCIE_HMA_STAT", 0x59b4, 0 },
|
|
{ "RspCnt", 20, 9 },
|
|
{ "RdReqCnt", 12, 6 },
|
|
{ "WrReqCnt", 0, 9 },
|
|
{ "PCIE_HMA_STAT2", 0x59b8, 0 },
|
|
{ "CookieCnt", 24, 4 },
|
|
{ "RdSeqNumUpdCnt", 20, 4 },
|
|
{ "WrEOPMatchSOP", 12, 1 },
|
|
{ "WrSOPCnt", 8, 4 },
|
|
{ "RdSOPCnt", 0, 8 },
|
|
{ "PCIE_HMA_STAT3", 0x59bc, 0 },
|
|
{ "RspEOPMatchSOP", 16, 1 },
|
|
{ "RspErrCnt", 8, 8 },
|
|
{ "RspSOPCnt", 0, 8 },
|
|
{ "PCIE_CGEN", 0x59c0, 0 },
|
|
{ "VPD_Dynamic_CGEN", 26, 1 },
|
|
{ "MA_Dynamic_CGEN", 25, 1 },
|
|
{ "Tagq_Dynamic_CGEN", 24, 1 },
|
|
{ "ReqCtl_Dynamic_CGEN", 23, 1 },
|
|
{ "RspDataProc_Dynamic_CGEN", 22, 1 },
|
|
{ "RspRdq_Dynamic_CGEN", 21, 1 },
|
|
{ "RspIPif_Dynamic_CGEN", 20, 1 },
|
|
{ "HMA_Static_CGEN", 19, 1 },
|
|
{ "HMA_Dynamic_CGEN", 18, 1 },
|
|
{ "CMD_Static_CGEN", 16, 1 },
|
|
{ "CMD_Dynamic_CGEN", 15, 1 },
|
|
{ "DMA_Static_CGEN", 13, 1 },
|
|
{ "DMA_Dynamic_CGEN", 12, 1 },
|
|
{ "VFID_SleepStatus", 10, 1 },
|
|
{ "VC1_SleepStatus", 9, 1 },
|
|
{ "STI_SleepStatus", 8, 1 },
|
|
{ "VFID_SleepReq", 2, 1 },
|
|
{ "VC1_SleepReq", 1, 1 },
|
|
{ "STI_SleepReq", 0, 1 },
|
|
{ "PCIE_MA_RSP", 0x59c4, 0 },
|
|
{ "TimerValue", 8, 24 },
|
|
{ "MAReqTimerEn", 1, 1 },
|
|
{ "TimerEn", 0, 1 },
|
|
{ "PCIE_HPRD", 0x59c8, 0 },
|
|
{ "NPH_CreditsAvailVC0", 19, 2 },
|
|
{ "NPD_CreditsAvailVC0", 17, 2 },
|
|
{ "NPH_CreditsAvailVC1", 15, 2 },
|
|
{ "NPD_CreditsAvailVC1", 13, 2 },
|
|
{ "NPH_CreditsRequired", 11, 2 },
|
|
{ "NPD_CreditsRequired", 9, 2 },
|
|
{ "ReqBurstCount", 5, 4 },
|
|
{ "ReqBurstFrequency", 1, 4 },
|
|
{ "EnableVC1", 0, 1 },
|
|
{ "PCIE_PERR_GROUP", 0x59d0, 0 },
|
|
{ "MST_DataPathPerr", 25, 1 },
|
|
{ "MST_RspRdQPerr", 24, 1 },
|
|
{ "IP_RxPerr", 23, 1 },
|
|
{ "IP_BackTxPerr", 22, 1 },
|
|
{ "IP_FrontTxPerr", 21, 1 },
|
|
{ "TRGT1_FIDLkUpHdrPerr", 20, 1 },
|
|
{ "TRGT1_AlindDataPerr", 19, 1 },
|
|
{ "TRGT1_UnAlinDataPerr", 18, 1 },
|
|
{ "TRGT1_ReqDataPerr", 17, 1 },
|
|
{ "TRGT1_ReqHdrPerr", 16, 1 },
|
|
{ "IPRxData_VC1Perr", 15, 1 },
|
|
{ "IPRxData_VC0Perr", 14, 1 },
|
|
{ "IPRxHdr_VC1Perr", 13, 1 },
|
|
{ "IPRxHdr_VC0Perr", 12, 1 },
|
|
{ "MA_RspDataPerr", 11, 1 },
|
|
{ "MA_CplTagQPerr", 10, 1 },
|
|
{ "MA_ReqTagQPerr", 9, 1 },
|
|
{ "PIOReq_BAR2CtlPerr", 8, 1 },
|
|
{ "PIOReq_MEMCtlPerr", 7, 1 },
|
|
{ "PIOReq_PLMCtlPerr", 6, 1 },
|
|
{ "PIOReq_BAR2DataPerr", 5, 1 },
|
|
{ "PIOReq_MEMDataPerr", 4, 1 },
|
|
{ "PIOReq_PLMDataPerr", 3, 1 },
|
|
{ "PIOCpl_CtlPerr", 2, 1 },
|
|
{ "PIOCpl_DataPerr", 1, 1 },
|
|
{ "PIOCpl_PLMRspPerr", 0, 1 },
|
|
{ "PCIE_RSP_ERR_INT_LOG_EN", 0x59d4, 0 },
|
|
{ "CplStatusIntEn", 12, 1 },
|
|
{ "TimeoutIntEn", 11, 1 },
|
|
{ "DisabledIntEn", 10, 1 },
|
|
{ "RspDropFLRIntEn", 9, 1 },
|
|
{ "ReqUnderFLRIntEn", 8, 1 },
|
|
{ "CplStatusLogEn", 4, 1 },
|
|
{ "TimeoutLogEn", 3, 1 },
|
|
{ "DisabledLogEn", 2, 1 },
|
|
{ "RspDropFLRLogEn", 1, 1 },
|
|
{ "ReqUnderFLRLogEn", 0, 1 },
|
|
{ "PCIE_RSP_ERR_LOG1", 0x59d8, 0 },
|
|
{ "Tag", 25, 7 },
|
|
{ "CID", 22, 3 },
|
|
{ "ChNum", 19, 3 },
|
|
{ "ByteLen", 6, 13 },
|
|
{ "Reason", 3, 3 },
|
|
{ "CplStatus", 0, 3 },
|
|
{ "PCIE_RSP_ERR_LOG2", 0x59dc, 0 },
|
|
{ "Valid", 31, 1 },
|
|
{ "Addr10b", 8, 10 },
|
|
{ "VFID", 0, 8 },
|
|
{ "PCIE_REVISION", 0x5a00, 0 },
|
|
{ "PCIE_PDEBUG_INDEX", 0x5a04, 0 },
|
|
{ "PDEBUGSelH", 16, 6 },
|
|
{ "PDEBUGSelL", 0, 6 },
|
|
{ "PCIE_PDEBUG_DATA_HIGH", 0x5a08, 0 },
|
|
{ "PCIE_PDEBUG_DATA_LOW", 0x5a0c, 0 },
|
|
{ "PCIE_CDEBUG_INDEX", 0x5a10, 0 },
|
|
{ "CDEBUGSelH", 16, 8 },
|
|
{ "CDEBUGSelL", 0, 8 },
|
|
{ "PCIE_CDEBUG_DATA_HIGH", 0x5a14, 0 },
|
|
{ "PCIE_CDEBUG_DATA_LOW", 0x5a18, 0 },
|
|
{ "PCIE_BUS_MST_STAT_0", 0x5a60, 0 },
|
|
{ "PCIE_BUS_MST_STAT_1", 0x5a64, 0 },
|
|
{ "PCIE_BUS_MST_STAT_2", 0x5a68, 0 },
|
|
{ "PCIE_BUS_MST_STAT_3", 0x5a6c, 0 },
|
|
{ "PCIE_BUS_MST_STAT_4", 0x5a70, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_0", 0x5a80, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_1", 0x5a84, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_2", 0x5a88, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_3", 0x5a8c, 0 },
|
|
{ "PCIE_RSP_ERR_STAT_4", 0x5a90, 0 },
|
|
{ "PCIE_DBI_TIMEOUT_CTL", 0x5a94, 0 },
|
|
{ "PCIE_DBI_TIMEOUT_STATUS0", 0x5a98, 0 },
|
|
{ "PCIE_DBI_TIMEOUT_STATUS1", 0x5a9c, 0 },
|
|
{ "Valid", 31, 1 },
|
|
{ "Source", 16, 2 },
|
|
{ "Write", 12, 4 },
|
|
{ "CS2", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VFVld", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "PCIE_PB_CTL", 0x5b94, 0 },
|
|
{ "PB_Sel", 16, 8 },
|
|
{ "PB_SelReg", 8, 8 },
|
|
{ "PB_Func", 0, 3 },
|
|
{ "PCIE_PB_DATA", 0x5b98, 0 },
|
|
{ "PCIE_CHANGESET", 0x59fc, 0 },
|
|
{ "PCIE_CUR_LINK", 0x5b9c, 0 },
|
|
{ "CfgInitCoeffDoneSeen", 22, 1 },
|
|
{ "CfgInitCoeffDone", 21, 1 },
|
|
{ "xmlh_link_up", 20, 1 },
|
|
{ "pm_linkst_in_l0s", 19, 1 },
|
|
{ "pm_linkst_in_l1", 18, 1 },
|
|
{ "pm_linkst_in_l2", 17, 1 },
|
|
{ "pm_linkst_l2_exit", 16, 1 },
|
|
{ "xmlh_in_rl0s", 15, 1 },
|
|
{ "xmlh_ltssm_state_rcvry_eq", 14, 1 },
|
|
{ "NegotiatedWidth", 8, 6 },
|
|
{ "ActiveLanes", 0, 8 },
|
|
{ "PCIE_PHY_REQRXPWR", 0x5ba0, 0 },
|
|
{ "LnH_RxStateDone", 31, 1 },
|
|
{ "LnH_RxStateReq", 30, 1 },
|
|
{ "LnH_RxPwrState", 28, 2 },
|
|
{ "LnG_RxStateDone", 27, 1 },
|
|
{ "LnG_RxStateReq", 26, 1 },
|
|
{ "LnG_RxPwrState", 24, 2 },
|
|
{ "LnF_RxStateDone", 23, 1 },
|
|
{ "LnF_RxStateReq", 22, 1 },
|
|
{ "LnF_RxPwrState", 20, 2 },
|
|
{ "LnE_RxStateDone", 19, 1 },
|
|
{ "LnE_RxStateReq", 18, 1 },
|
|
{ "LnE_RxPwrState", 16, 2 },
|
|
{ "LnD_RxStateDone", 15, 1 },
|
|
{ "LnD_RxStateReq", 14, 1 },
|
|
{ "LnD_RxPwrState", 12, 2 },
|
|
{ "LnC_RxStateDone", 11, 1 },
|
|
{ "LnC_RxStateReq", 10, 1 },
|
|
{ "LnC_RxPwrState", 8, 2 },
|
|
{ "LnB_RxStateDone", 7, 1 },
|
|
{ "LnB_RxStateReq", 6, 1 },
|
|
{ "LnB_RxPwrState", 4, 2 },
|
|
{ "LnA_RxStateDone", 3, 1 },
|
|
{ "LnA_RxStateReq", 2, 1 },
|
|
{ "LnA_RxPwrState", 0, 2 },
|
|
{ "PCIE_PHY_CURRXPWR", 0x5ba4, 0 },
|
|
{ "LnH_RxPwrState", 28, 3 },
|
|
{ "LnG_RxPwrState", 24, 3 },
|
|
{ "LnF_RxPwrState", 20, 3 },
|
|
{ "LnE_RxPwrState", 16, 3 },
|
|
{ "LnD_RxPwrState", 12, 3 },
|
|
{ "LnC_RxPwrState", 8, 3 },
|
|
{ "LnB_RxPwrState", 4, 3 },
|
|
{ "LnA_RxPwrState", 0, 3 },
|
|
{ "PCIE_PHY_GEN3_AE0", 0x5ba8, 0 },
|
|
{ "LnD_STAT", 28, 3 },
|
|
{ "LnD_CMD", 24, 3 },
|
|
{ "LnC_STAT", 20, 3 },
|
|
{ "LnC_CMD", 16, 3 },
|
|
{ "LnB_STAT", 12, 3 },
|
|
{ "LnB_CMD", 8, 3 },
|
|
{ "LnA_STAT", 4, 3 },
|
|
{ "LnA_CMD", 0, 3 },
|
|
{ "PCIE_PHY_GEN3_AE1", 0x5bac, 0 },
|
|
{ "LnH_STAT", 28, 3 },
|
|
{ "LnH_CMD", 24, 3 },
|
|
{ "LnG_STAT", 20, 3 },
|
|
{ "LnG_CMD", 16, 3 },
|
|
{ "LnF_STAT", 12, 3 },
|
|
{ "LnF_CMD", 8, 3 },
|
|
{ "LnE_STAT", 4, 3 },
|
|
{ "LnE_CMD", 0, 3 },
|
|
{ "PCIE_PHY_FS_LF0", 0x5bb0, 0 },
|
|
{ "Lane1LF", 24, 6 },
|
|
{ "Lane1FS", 16, 6 },
|
|
{ "Lane0LF", 8, 6 },
|
|
{ "Lane0FS", 0, 6 },
|
|
{ "PCIE_PHY_FS_LF1", 0x5bb4, 0 },
|
|
{ "Lane3LF", 24, 6 },
|
|
{ "Lane3FS", 16, 6 },
|
|
{ "Lane2LF", 8, 6 },
|
|
{ "Lane2FS", 0, 6 },
|
|
{ "PCIE_PHY_FS_LF2", 0x5bb8, 0 },
|
|
{ "Lane5LF", 24, 6 },
|
|
{ "Lane5FS", 16, 6 },
|
|
{ "Lane4LF", 8, 6 },
|
|
{ "Lane4FS", 0, 6 },
|
|
{ "PCIE_PHY_FS_LF3", 0x5bbc, 0 },
|
|
{ "Lane7LF", 24, 6 },
|
|
{ "Lane7FS", 16, 6 },
|
|
{ "Lane6LF", 8, 6 },
|
|
{ "Lane6FS", 0, 6 },
|
|
{ "PCIE_PHY_PRESET_REQ", 0x5bc0, 0 },
|
|
{ "CoeffDone", 16, 1 },
|
|
{ "CoeffLane", 8, 3 },
|
|
{ "CoeffStart", 0, 1 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5bc4, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5bc8, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5bcc, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5bd0, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5bd4, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5bd8, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5bdc, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5be0, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5be4, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5be8, 0 },
|
|
{ "PCIE_PHY_PRESET_COEFF", 0x5bec, 0 },
|
|
{ "PCIE_PHY_INDIR_REQ", 0x5bf0, 0 },
|
|
{ "Enable", 31, 1 },
|
|
{ "RegAddr", 0, 16 },
|
|
{ "PCIE_PHY_INDIR_DATA", 0x5bf4, 0 },
|
|
{ "PCIE_STATIC_SPARE1", 0x5bf8, 0 },
|
|
{ "PCIE_STATIC_SPARE2", 0x5bfc, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_dbg_regs[] = {
|
|
{ "DBG_DBG0_CFG", 0x6000, 0 },
|
|
{ "ModuleSelect", 12, 8 },
|
|
{ "RegSelect", 4, 8 },
|
|
{ "ClkSelect", 0, 4 },
|
|
{ "DBG_DBG0_EN", 0x6004, 0 },
|
|
{ "SDRHalfWord0", 8, 1 },
|
|
{ "DDREn", 4, 1 },
|
|
{ "PortEn", 0, 1 },
|
|
{ "DBG_DBG1_CFG", 0x6008, 0 },
|
|
{ "ModuleSelect", 12, 8 },
|
|
{ "RegSelect", 4, 8 },
|
|
{ "ClkSelect", 0, 4 },
|
|
{ "DBG_DBG1_EN", 0x600c, 0 },
|
|
{ "Clk_en_on_dbg1", 20, 1 },
|
|
{ "SDRHalfWord0", 8, 1 },
|
|
{ "DDREn", 4, 1 },
|
|
{ "PortEn", 0, 1 },
|
|
{ "DBG_GPIO_EN", 0x6010, 0 },
|
|
{ "GPIO15_OEn", 31, 1 },
|
|
{ "GPIO14_OEn", 30, 1 },
|
|
{ "GPIO13_OEn", 29, 1 },
|
|
{ "GPIO12_OEn", 28, 1 },
|
|
{ "GPIO11_OEn", 27, 1 },
|
|
{ "GPIO10_OEn", 26, 1 },
|
|
{ "GPIO9_OEn", 25, 1 },
|
|
{ "GPIO8_OEn", 24, 1 },
|
|
{ "GPIO7_OEn", 23, 1 },
|
|
{ "GPIO6_OEn", 22, 1 },
|
|
{ "GPIO5_OEn", 21, 1 },
|
|
{ "GPIO4_OEn", 20, 1 },
|
|
{ "GPIO3_OEn", 19, 1 },
|
|
{ "GPIO2_OEn", 18, 1 },
|
|
{ "GPIO1_OEn", 17, 1 },
|
|
{ "GPIO0_OEn", 16, 1 },
|
|
{ "GPIO15_Out_Val", 15, 1 },
|
|
{ "GPIO14_Out_Val", 14, 1 },
|
|
{ "GPIO13_Out_Val", 13, 1 },
|
|
{ "GPIO12_Out_Val", 12, 1 },
|
|
{ "GPIO11_Out_Val", 11, 1 },
|
|
{ "GPIO10_Out_Val", 10, 1 },
|
|
{ "GPIO9_Out_Val", 9, 1 },
|
|
{ "GPIO8_Out_Val", 8, 1 },
|
|
{ "GPIO7_Out_Val", 7, 1 },
|
|
{ "GPIO6_Out_Val", 6, 1 },
|
|
{ "GPIO5_Out_Val", 5, 1 },
|
|
{ "GPIO4_Out_Val", 4, 1 },
|
|
{ "GPIO3_Out_Val", 3, 1 },
|
|
{ "GPIO2_Out_Val", 2, 1 },
|
|
{ "GPIO1_Out_Val", 1, 1 },
|
|
{ "GPIO0_Out_Val", 0, 1 },
|
|
{ "DBG_GPIO_IN", 0x6014, 0 },
|
|
{ "GPIO15_CHG_DET", 31, 1 },
|
|
{ "GPIO14_CHG_DET", 30, 1 },
|
|
{ "GPIO13_CHG_DET", 29, 1 },
|
|
{ "GPIO12_CHG_DET", 28, 1 },
|
|
{ "GPIO11_CHG_DET", 27, 1 },
|
|
{ "GPIO10_CHG_DET", 26, 1 },
|
|
{ "GPIO9_CHG_DET", 25, 1 },
|
|
{ "GPIO8_CHG_DET", 24, 1 },
|
|
{ "GPIO7_CHG_DET", 23, 1 },
|
|
{ "GPIO6_CHG_DET", 22, 1 },
|
|
{ "GPIO5_CHG_DET", 21, 1 },
|
|
{ "GPIO4_CHG_DET", 20, 1 },
|
|
{ "GPIO3_CHG_DET", 19, 1 },
|
|
{ "GPIO2_CHG_DET", 18, 1 },
|
|
{ "GPIO1_CHG_DET", 17, 1 },
|
|
{ "GPIO0_CHG_DET", 16, 1 },
|
|
{ "GPIO15_IN", 15, 1 },
|
|
{ "GPIO14_IN", 14, 1 },
|
|
{ "GPIO13_IN", 13, 1 },
|
|
{ "GPIO12_IN", 12, 1 },
|
|
{ "GPIO11_IN", 11, 1 },
|
|
{ "GPIO10_IN", 10, 1 },
|
|
{ "GPIO9_IN", 9, 1 },
|
|
{ "GPIO8_IN", 8, 1 },
|
|
{ "GPIO7_IN", 7, 1 },
|
|
{ "GPIO6_IN", 6, 1 },
|
|
{ "GPIO5_IN", 5, 1 },
|
|
{ "GPIO4_IN", 4, 1 },
|
|
{ "GPIO3_IN", 3, 1 },
|
|
{ "GPIO2_IN", 2, 1 },
|
|
{ "GPIO1_IN", 1, 1 },
|
|
{ "GPIO0_IN", 0, 1 },
|
|
{ "DBG_GPIO_EN_NEW", 0x6100, 0 },
|
|
{ "GPIO16_OEn", 7, 1 },
|
|
{ "GPIO17_OEn", 6, 1 },
|
|
{ "GPIO18_OEn", 5, 1 },
|
|
{ "GPIO19_OEn", 4, 1 },
|
|
{ "GPIO16_Out_Val", 3, 1 },
|
|
{ "GPIO17_Out_Val", 2, 1 },
|
|
{ "GPIO18_Out_Val", 1, 1 },
|
|
{ "GPIO19_Out_Val", 0, 1 },
|
|
{ "DBG_GPIO_IN_NEW", 0x6104, 0 },
|
|
{ "GPIO16_CHG_DET", 7, 1 },
|
|
{ "GPIO17_CHG_DET", 6, 1 },
|
|
{ "GPIO18_CHG_DET", 5, 1 },
|
|
{ "GPIO19_CHG_DET", 4, 1 },
|
|
{ "GPIO19_IN", 3, 1 },
|
|
{ "GPIO18_IN", 2, 1 },
|
|
{ "GPIO17_IN", 1, 1 },
|
|
{ "GPIO16_IN", 0, 1 },
|
|
{ "DBG_INT_ENABLE", 0x6018, 0 },
|
|
{ "GPIO19", 29, 1 },
|
|
{ "GPIO18", 28, 1 },
|
|
{ "GPIO17", 27, 1 },
|
|
{ "GPIO16", 26, 1 },
|
|
{ "IBM_FDL_FAIL_int_enbl", 25, 1 },
|
|
{ "pll_lock_lost_int_enbl", 22, 1 },
|
|
{ "C_LOCK", 21, 1 },
|
|
{ "M_LOCK", 20, 1 },
|
|
{ "U_LOCK", 19, 1 },
|
|
{ "PCIe_LOCK", 18, 1 },
|
|
{ "KX_LOCK", 17, 1 },
|
|
{ "KR_LOCK", 16, 1 },
|
|
{ "GPIO15", 15, 1 },
|
|
{ "GPIO14", 14, 1 },
|
|
{ "GPIO13", 13, 1 },
|
|
{ "GPIO12", 12, 1 },
|
|
{ "GPIO11", 11, 1 },
|
|
{ "GPIO10", 10, 1 },
|
|
{ "GPIO9", 9, 1 },
|
|
{ "GPIO8", 8, 1 },
|
|
{ "GPIO7", 7, 1 },
|
|
{ "GPIO6", 6, 1 },
|
|
{ "GPIO5", 5, 1 },
|
|
{ "GPIO4", 4, 1 },
|
|
{ "GPIO3", 3, 1 },
|
|
{ "GPIO2", 2, 1 },
|
|
{ "GPIO1", 1, 1 },
|
|
{ "GPIO0", 0, 1 },
|
|
{ "DBG_INT_CAUSE", 0x601c, 0 },
|
|
{ "GPIO19", 29, 1 },
|
|
{ "GPIO18", 28, 1 },
|
|
{ "GPIO17", 27, 1 },
|
|
{ "GPIO16", 26, 1 },
|
|
{ "IBM_FDL_FAIL_int_cause", 25, 1 },
|
|
{ "pll_lock_lost_int_cause", 22, 1 },
|
|
{ "C_LOCK", 21, 1 },
|
|
{ "M_LOCK", 20, 1 },
|
|
{ "U_LOCK", 19, 1 },
|
|
{ "PCIe_LOCK", 18, 1 },
|
|
{ "KX_LOCK", 17, 1 },
|
|
{ "KR_LOCK", 16, 1 },
|
|
{ "GPIO15", 15, 1 },
|
|
{ "GPIO14", 14, 1 },
|
|
{ "GPIO13", 13, 1 },
|
|
{ "GPIO12", 12, 1 },
|
|
{ "GPIO11", 11, 1 },
|
|
{ "GPIO10", 10, 1 },
|
|
{ "GPIO9", 9, 1 },
|
|
{ "GPIO8", 8, 1 },
|
|
{ "GPIO7", 7, 1 },
|
|
{ "GPIO6", 6, 1 },
|
|
{ "GPIO5", 5, 1 },
|
|
{ "GPIO4", 4, 1 },
|
|
{ "GPIO3", 3, 1 },
|
|
{ "GPIO2", 2, 1 },
|
|
{ "GPIO1", 1, 1 },
|
|
{ "GPIO0", 0, 1 },
|
|
{ "DBG_DBG0_RST_VALUE", 0x6020, 0 },
|
|
{ "DBG_PLL_OCLK_PAD_EN", 0x6028, 0 },
|
|
{ "PCIE_OCLK_En", 20, 1 },
|
|
{ "KX_OCLK_En", 16, 1 },
|
|
{ "U_OCLK_En", 12, 1 },
|
|
{ "KR_OCLK_En", 8, 1 },
|
|
{ "M_OCLK_En", 4, 1 },
|
|
{ "C_OCLK_En", 0, 1 },
|
|
{ "DBG_PLL_LOCK", 0x602c, 0 },
|
|
{ "P_LOCK", 20, 1 },
|
|
{ "KX_LOCK", 16, 1 },
|
|
{ "U_LOCK", 12, 1 },
|
|
{ "KR_LOCK", 8, 1 },
|
|
{ "M_LOCK", 4, 1 },
|
|
{ "C_LOCK", 0, 1 },
|
|
{ "DBG_GPIO_ACT_LOW", 0x6030, 0 },
|
|
{ "GPIO19_ACT_LOW", 25, 1 },
|
|
{ "GPIO18_ACT_LOW", 24, 1 },
|
|
{ "GPIO17_ACT_LOW", 23, 1 },
|
|
{ "GPIO16_ACT_LOW", 22, 1 },
|
|
{ "P_LOCK_ACT_LOW", 21, 1 },
|
|
{ "C_LOCK_ACT_LOW", 20, 1 },
|
|
{ "M_LOCK_ACT_LOW", 19, 1 },
|
|
{ "U_LOCK_ACT_LOW", 18, 1 },
|
|
{ "KR_LOCK_ACT_LOW", 17, 1 },
|
|
{ "KX_LOCK_ACT_LOW", 16, 1 },
|
|
{ "GPIO15_ACT_LOW", 15, 1 },
|
|
{ "GPIO14_ACT_LOW", 14, 1 },
|
|
{ "GPIO13_ACT_LOW", 13, 1 },
|
|
{ "GPIO12_ACT_LOW", 12, 1 },
|
|
{ "GPIO11_ACT_LOW", 11, 1 },
|
|
{ "GPIO10_ACT_LOW", 10, 1 },
|
|
{ "GPIO9_ACT_LOW", 9, 1 },
|
|
{ "GPIO8_ACT_LOW", 8, 1 },
|
|
{ "GPIO7_ACT_LOW", 7, 1 },
|
|
{ "GPIO6_ACT_LOW", 6, 1 },
|
|
{ "GPIO5_ACT_LOW", 5, 1 },
|
|
{ "GPIO4_ACT_LOW", 4, 1 },
|
|
{ "GPIO3_ACT_LOW", 3, 1 },
|
|
{ "GPIO2_ACT_LOW", 2, 1 },
|
|
{ "GPIO1_ACT_LOW", 1, 1 },
|
|
{ "GPIO0_ACT_LOW", 0, 1 },
|
|
{ "DBG_EFUSE_BYTE0_3", 0x6034, 0 },
|
|
{ "DBG_EFUSE_BYTE4_7", 0x6038, 0 },
|
|
{ "DBG_EFUSE_BYTE8_11", 0x603c, 0 },
|
|
{ "DBG_EFUSE_BYTE12_15", 0x6040, 0 },
|
|
{ "DBG_EXTRA_STATIC_BITS_CONF", 0x6058, 0 },
|
|
{ "STATIC_M_PLL_RESET", 30, 1 },
|
|
{ "STATIC_M_PLL_SLEEP", 29, 1 },
|
|
{ "STATIC_M_PLL_BYPASS", 28, 1 },
|
|
{ "STATIC_MPLL_CLK_SEL", 27, 1 },
|
|
{ "STATIC_U_PLL_SLEEP", 26, 1 },
|
|
{ "STATIC_C_PLL_SLEEP", 25, 1 },
|
|
{ "STATIC_LVDS_CLKOUT_SEL", 23, 2 },
|
|
{ "STATIC_LVDS_CLKOUT_EN", 22, 1 },
|
|
{ "STATIC_CCLK_FREQ_SEL", 20, 2 },
|
|
{ "STATIC_UCLK_FREQ_SEL", 18, 2 },
|
|
{ "ExPHYClk_sel_en", 17, 1 },
|
|
{ "ExPHYClk_sel", 15, 2 },
|
|
{ "STATIC_U_PLL_BYPASS", 14, 1 },
|
|
{ "STATIC_C_PLL_BYPASS", 13, 1 },
|
|
{ "STATIC_KR_PLL_BYPASS", 12, 1 },
|
|
{ "STATIC_KX_PLL_BYPASS", 11, 1 },
|
|
{ "STATIC_KX_PLL_V", 7, 4 },
|
|
{ "STATIC_KR_PLL_V", 3, 4 },
|
|
{ "DBG_STATIC_OCLK_MUXSEL_CONF", 0x605c, 0 },
|
|
{ "T5_P_OCLK_MUXSEL", 13, 4 },
|
|
{ "M_OCLK_MUXSEL", 12, 1 },
|
|
{ "C_OCLK_MUXSEL", 10, 2 },
|
|
{ "U_OCLK_MUXSEL", 8, 2 },
|
|
{ "P_OCLK_MUXSEL", 6, 2 },
|
|
{ "KX_OCLK_MUXSEL", 3, 3 },
|
|
{ "KR_OCLK_MUXSEL", 0, 3 },
|
|
{ "DBG_TRACE0_CONF_COMPREG0", 0x6060, 0 },
|
|
{ "DBG_TRACE0_CONF_COMPREG1", 0x6064, 0 },
|
|
{ "DBG_TRACE1_CONF_COMPREG0", 0x6068, 0 },
|
|
{ "DBG_TRACE1_CONF_COMPREG1", 0x606c, 0 },
|
|
{ "DBG_TRACE0_CONF_MASKREG0", 0x6070, 0 },
|
|
{ "DBG_TRACE0_CONF_MASKREG1", 0x6074, 0 },
|
|
{ "DBG_TRACE1_CONF_MASKREG0", 0x6078, 0 },
|
|
{ "DBG_TRACE1_CONF_MASKREG1", 0x607c, 0 },
|
|
{ "DBG_TRACE_COUNTER", 0x6080, 0 },
|
|
{ "Counter1", 16, 16 },
|
|
{ "Counter0", 0, 16 },
|
|
{ "DBG_STATIC_REFCLK_PERIOD", 0x6084, 0 },
|
|
{ "DBG_TRACE_CONF", 0x6088, 0 },
|
|
{ "dbg_trace_operate_with_trg", 5, 1 },
|
|
{ "dbg_trace_operate_en", 4, 1 },
|
|
{ "dbg_operate_indv_combined", 3, 1 },
|
|
{ "dbg_operate_order_of_trigger", 2, 1 },
|
|
{ "dbg_operate_sgl_dbl_trigger", 1, 1 },
|
|
{ "dbg_operate0_or_1", 0, 1 },
|
|
{ "DBG_TRACE_RDEN", 0x608c, 0 },
|
|
{ "RD_ADDR1", 11, 9 },
|
|
{ "RD_ADDR0", 2, 9 },
|
|
{ "Rd_en1", 1, 1 },
|
|
{ "Rd_en0", 0, 1 },
|
|
{ "DBG_TRACE_WRADDR", 0x6090, 0 },
|
|
{ "Wr_pointer_addr1", 16, 9 },
|
|
{ "Wr_pointer_addr0", 0, 9 },
|
|
{ "DBG_TRACE0_DATA_OUT", 0x6094, 0 },
|
|
{ "DBG_TRACE1_DATA_OUT", 0x6098, 0 },
|
|
{ "DBG_FUSE_SENSE_DONE", 0x609c, 0 },
|
|
{ "STATIC_JTAG_VersionNr", 5, 4 },
|
|
{ "PSRO_sel", 1, 4 },
|
|
{ "FUSE_DONE_SENSE", 0, 1 },
|
|
{ "DBG_TVSENSE_EN", 0x60a8, 0 },
|
|
{ "MCIMPED1_out", 29, 1 },
|
|
{ "MCIMPED2_out", 28, 1 },
|
|
{ "TVSENSE_SNSOUT", 17, 9 },
|
|
{ "TVSENSE_OUTPUTVALID", 16, 1 },
|
|
{ "TVSENSE_SLEEP", 10, 1 },
|
|
{ "TVSENSE_SENSV", 9, 1 },
|
|
{ "TVSENSE_RST", 8, 1 },
|
|
{ "TVSENSE_RATIO", 0, 8 },
|
|
{ "DBG_CUST_EFUSE_OUT_EN", 0x60ac, 0 },
|
|
{ "DBG_CUST_EFUSE_SEL1_EN", 0x60b0, 0 },
|
|
{ "DBG_CUST_EFUSE_SEL2_EN", 0x60b4, 0 },
|
|
{ "DBG_FEENABLE", 29, 1 },
|
|
{ "DBG_FEF", 23, 6 },
|
|
{ "DBG_FEMIMICN", 22, 1 },
|
|
{ "DBG_FEGATEC", 21, 1 },
|
|
{ "DBG_FEPROGP", 20, 1 },
|
|
{ "DBG_FEREADCLK", 19, 1 },
|
|
{ "DBG_FERSEL", 3, 16 },
|
|
{ "DBG_FETIME", 0, 3 },
|
|
{ "DBG_T5_STATIC_M_PLL_CONF1", 0x60b8, 0 },
|
|
{ "T5_STATIC_M_PLL_MULTFRAC", 8, 24 },
|
|
{ "T5_STATIC_M_PLL_FFSLEWRATE", 0, 8 },
|
|
{ "DBG_T5_STATIC_M_PLL_CONF2", 0x60bc, 0 },
|
|
{ "T5_STATIC_M_PLL_DCO_BYPASS", 23, 1 },
|
|
{ "T5_STATIC_M_PLL_SDORDER", 21, 2 },
|
|
{ "T5_STATIC_M_PLL_FFENABLE", 20, 1 },
|
|
{ "T5_STATIC_M_PLL_STOPCLKB", 19, 1 },
|
|
{ "T5_STATIC_M_PLL_STOPCLKA", 18, 1 },
|
|
{ "T5_STATIC_M_PLL_SLEEP", 17, 1 },
|
|
{ "T5_STATIC_M_PLL_BYPASS", 16, 1 },
|
|
{ "T5_STATIC_M_PLL_LOCKTUNE", 0, 16 },
|
|
{ "DBG_T5_STATIC_M_PLL_CONF3", 0x60c0, 0 },
|
|
{ "T5_STATIC_M_PLL_MULTPRE", 30, 2 },
|
|
{ "T5_STATIC_M_PLL_LOCKSEL", 28, 2 },
|
|
{ "T5_STATIC_M_PLL_FFTUNE", 12, 16 },
|
|
{ "T5_STATIC_M_PLL_RANGEPRE", 10, 2 },
|
|
{ "T5_STATIC_M_PLL_RANGEB", 5, 5 },
|
|
{ "T5_STATIC_M_PLL_RANGEA", 0, 5 },
|
|
{ "DBG_T5_STATIC_M_PLL_CONF4", 0x60c4, 0 },
|
|
{ "DBG_T5_STATIC_M_PLL_CONF5", 0x60c8, 0 },
|
|
{ "T5_STATIC_M_PLL_VCVTUNE", 24, 3 },
|
|
{ "T5_STATIC_M_PLL_RESET", 23, 1 },
|
|
{ "T5_STATIC_MPLL_REFCLK_SEL", 22, 1 },
|
|
{ "T5_STATIC_M_PLL_LFTUNE_32_40", 13, 9 },
|
|
{ "T5_STATIC_M_PLL_PREDIV", 8, 5 },
|
|
{ "T5_STATIC_M_PLL_MULT", 0, 8 },
|
|
{ "DBG_T5_STATIC_M_PLL_CONF6", 0x60cc, 0 },
|
|
{ "T5_STATIC_PHY0RecRst_", 5, 1 },
|
|
{ "T5_STATIC_PHY1RecRst_", 4, 1 },
|
|
{ "T5_STATIC_SWMC0Rst_", 3, 1 },
|
|
{ "T5_STATIC_SWMC0CfgRst_", 2, 1 },
|
|
{ "T5_STATIC_SWMC1Rst_", 1, 1 },
|
|
{ "T5_STATIC_SWMC1CfgRst_", 0, 1 },
|
|
{ "DBG_T5_STATIC_C_PLL_CONF1", 0x60d0, 0 },
|
|
{ "T5_STATIC_C_PLL_MULTFRAC", 8, 24 },
|
|
{ "T5_STATIC_C_PLL_FFSLEWRATE", 0, 8 },
|
|
{ "DBG_T5_STATIC_C_PLL_CONF2", 0x60d4, 0 },
|
|
{ "T5_STATIC_C_PLL_DCO_BYPASS", 23, 1 },
|
|
{ "T5_STATIC_C_PLL_SDORDER", 21, 2 },
|
|
{ "T5_STATIC_C_PLL_FFENABLE", 20, 1 },
|
|
{ "T5_STATIC_C_PLL_STOPCLKB", 19, 1 },
|
|
{ "T5_STATIC_C_PLL_STOPCLKA", 18, 1 },
|
|
{ "T5_STATIC_C_PLL_SLEEP", 17, 1 },
|
|
{ "T5_STATIC_C_PLL_BYPASS", 16, 1 },
|
|
{ "T5_STATIC_C_PLL_LOCKTUNE", 0, 16 },
|
|
{ "DBG_T5_STATIC_C_PLL_CONF3", 0x60d8, 0 },
|
|
{ "T5_STATIC_C_PLL_MULTPRE", 30, 2 },
|
|
{ "T5_STATIC_C_PLL_LOCKSEL", 28, 2 },
|
|
{ "T5_STATIC_C_PLL_FFTUNE", 12, 16 },
|
|
{ "T5_STATIC_C_PLL_RANGEPRE", 10, 2 },
|
|
{ "T5_STATIC_C_PLL_RANGEB", 5, 5 },
|
|
{ "T5_STATIC_C_PLL_RANGEA", 0, 5 },
|
|
{ "DBG_T5_STATIC_C_PLL_CONF4", 0x60dc, 0 },
|
|
{ "DBG_T5_STATIC_C_PLL_CONF5", 0x60e0, 0 },
|
|
{ "T5_STATIC_C_PLL_VCVTUNE", 22, 3 },
|
|
{ "T5_STATIC_C_PLL_LFTUNE_32_40", 13, 9 },
|
|
{ "T5_STATIC_C_PLL_PREDIV", 8, 5 },
|
|
{ "T5_STATIC_C_PLL_MULT", 0, 8 },
|
|
{ "DBG_T5_STATIC_U_PLL_CONF1", 0x60e4, 0 },
|
|
{ "T5_STATIC_U_PLL_MULTFRAC", 8, 24 },
|
|
{ "T5_STATIC_U_PLL_FFSLEWRATE", 0, 8 },
|
|
{ "DBG_T5_STATIC_U_PLL_CONF2", 0x60e8, 0 },
|
|
{ "T5_STATIC_U_PLL_DCO_BYPASS", 23, 1 },
|
|
{ "T5_STATIC_U_PLL_SDORDER", 21, 2 },
|
|
{ "T5_STATIC_U_PLL_FFENABLE", 20, 1 },
|
|
{ "T5_STATIC_U_PLL_STOPCLKB", 19, 1 },
|
|
{ "T5_STATIC_U_PLL_STOPCLKA", 18, 1 },
|
|
{ "T5_STATIC_U_PLL_SLEEP", 17, 1 },
|
|
{ "T5_STATIC_U_PLL_BYPASS", 16, 1 },
|
|
{ "T5_STATIC_U_PLL_LOCKTUNE", 0, 16 },
|
|
{ "DBG_T5_STATIC_U_PLL_CONF3", 0x60ec, 0 },
|
|
{ "T5_STATIC_U_PLL_MULTPRE", 30, 2 },
|
|
{ "T5_STATIC_U_PLL_LOCKSEL", 28, 2 },
|
|
{ "T5_STATIC_U_PLL_FFTUNE", 12, 16 },
|
|
{ "T5_STATIC_U_PLL_RANGEPRE", 10, 2 },
|
|
{ "T5_STATIC_U_PLL_RANGEB", 5, 5 },
|
|
{ "T5_STATIC_U_PLL_RANGEA", 0, 5 },
|
|
{ "DBG_T5_STATIC_U_PLL_CONF4", 0x60f0, 0 },
|
|
{ "DBG_T5_STATIC_U_PLL_CONF5", 0x60f4, 0 },
|
|
{ "T5_STATIC_U_PLL_VCVTUNE", 22, 3 },
|
|
{ "T5_STATIC_U_PLL_LFTUNE_32_40", 13, 9 },
|
|
{ "T5_STATIC_U_PLL_PREDIV", 8, 5 },
|
|
{ "T5_STATIC_U_PLL_MULT", 0, 8 },
|
|
{ "DBG_T5_STATIC_KR_PLL_CONF1", 0x60f8, 0 },
|
|
{ "T5_STATIC_KR_PLL_BYPASS", 30, 1 },
|
|
{ "T5_STATIC_KR_PLL_VBOOSTDIV", 27, 3 },
|
|
{ "T5_STATIC_KR_PLL_CPISEL", 24, 3 },
|
|
{ "T5_STATIC_KR_PLL_CCALMETHOD", 23, 1 },
|
|
{ "T5_STATIC_KR_PLL_CCALLOAD", 22, 1 },
|
|
{ "T5_STATIC_KR_PLL_CCALFMIN", 21, 1 },
|
|
{ "T5_STATIC_KR_PLL_CCALFMAX", 20, 1 },
|
|
{ "T5_STATIC_KR_PLL_CCALCVHOLD", 19, 1 },
|
|
{ "T5_STATIC_KR_PLL_CCALBANDSEL", 15, 4 },
|
|
{ "T5_STATIC_KR_PLL_BGOFFSET", 11, 4 },
|
|
{ "T5_STATIC_KR_PLL_P", 8, 3 },
|
|
{ "T5_STATIC_KR_PLL_N2", 4, 4 },
|
|
{ "T5_STATIC_KR_PLL_N1", 0, 4 },
|
|
{ "DBG_T5_STATIC_KR_PLL_CONF2", 0x60fc, 0 },
|
|
{ "T5_STATIC_KR_PLL_M", 11, 9 },
|
|
{ "T5_STATIC_KR_PLL_ANALOGTUNE", 0, 11 },
|
|
{ "DBG_T5_STATIC_KX_PLL_CONF1", 0x6108, 0 },
|
|
{ "T5_STATIC_KX_PLL_BYPASS", 30, 1 },
|
|
{ "T5_STATIC_KX_PLL_VBOOSTDIV", 27, 3 },
|
|
{ "T5_STATIC_KX_PLL_CPISEL", 24, 3 },
|
|
{ "T5_STATIC_KX_PLL_CCALMETHOD", 23, 1 },
|
|
{ "T5_STATIC_KX_PLL_CCALLOAD", 22, 1 },
|
|
{ "T5_STATIC_KX_PLL_CCALFMIN", 21, 1 },
|
|
{ "T5_STATIC_KX_PLL_CCALFMAX", 20, 1 },
|
|
{ "T5_STATIC_KX_PLL_CCALCVHOLD", 19, 1 },
|
|
{ "T5_STATIC_KX_PLL_CCALBANDSEL", 15, 4 },
|
|
{ "T5_STATIC_KX_PLL_BGOFFSET", 11, 4 },
|
|
{ "T5_STATIC_KX_PLL_P", 8, 3 },
|
|
{ "T5_STATIC_KX_PLL_N2", 4, 4 },
|
|
{ "T5_STATIC_KX_PLL_N1", 0, 4 },
|
|
{ "DBG_T5_STATIC_KX_PLL_CONF2", 0x610c, 0 },
|
|
{ "T5_STATIC_KX_PLL_M", 11, 9 },
|
|
{ "T5_STATIC_KX_PLL_ANALOGTUNE", 0, 11 },
|
|
{ "DBG_T5_STATIC_C_DFS_CONF", 0x6110, 0 },
|
|
{ "STATIC_C_DFS_RANGEA", 8, 5 },
|
|
{ "STATIC_C_DFS_RANGEB", 3, 5 },
|
|
{ "STATIC_C_DFS_FFTUNE4", 2, 1 },
|
|
{ "STATIC_C_DFS_FFTUNE5", 1, 1 },
|
|
{ "STATIC_C_DFS_ENABLE", 0, 1 },
|
|
{ "DBG_T5_STATIC_U_DFS_CONF", 0x6114, 0 },
|
|
{ "STATIC_U_DFS_RANGEA", 8, 5 },
|
|
{ "STATIC_U_DFS_RANGEB", 3, 5 },
|
|
{ "STATIC_U_DFS_FFTUNE4", 2, 1 },
|
|
{ "STATIC_U_DFS_FFTUNE5", 1, 1 },
|
|
{ "STATIC_U_DFS_ENABLE", 0, 1 },
|
|
{ "DBG_GPIO_PE_EN", 0x6118, 0 },
|
|
{ "GPIO19_PE_En", 19, 1 },
|
|
{ "GPIO18_PE_En", 18, 1 },
|
|
{ "GPIO17_PE_En", 17, 1 },
|
|
{ "GPIO16_PE_En", 16, 1 },
|
|
{ "GPIO15_PE_En", 15, 1 },
|
|
{ "GPIO14_PE_En", 14, 1 },
|
|
{ "GPIO13_PE_En", 13, 1 },
|
|
{ "GPIO12_PE_En", 12, 1 },
|
|
{ "GPIO11_PE_En", 11, 1 },
|
|
{ "GPIO10_PE_En", 10, 1 },
|
|
{ "GPIO9_PE_En", 9, 1 },
|
|
{ "GPIO8_PE_En", 8, 1 },
|
|
{ "GPIO7_PE_En", 7, 1 },
|
|
{ "GPIO6_PE_En", 6, 1 },
|
|
{ "GPIO5_PE_En", 5, 1 },
|
|
{ "GPIO4_PE_En", 4, 1 },
|
|
{ "GPIO3_PE_En", 3, 1 },
|
|
{ "GPIO2_PE_En", 2, 1 },
|
|
{ "GPIO1_PE_En", 1, 1 },
|
|
{ "GPIO0_PE_En", 0, 1 },
|
|
{ "DBG_GPIO_PS_EN", 0x611c, 0 },
|
|
{ "GPIO19_PS_En", 19, 1 },
|
|
{ "GPIO18_PS_En", 18, 1 },
|
|
{ "GPIO17_PS_En", 17, 1 },
|
|
{ "GPIO16_PS_En", 16, 1 },
|
|
{ "GPIO15_PS_En", 15, 1 },
|
|
{ "GPIO14_PS_En", 14, 1 },
|
|
{ "GPIO13_PS_En", 13, 1 },
|
|
{ "GPIO12_PS_En", 12, 1 },
|
|
{ "GPIO11_PS_En", 11, 1 },
|
|
{ "GPIO10_PS_En", 10, 1 },
|
|
{ "GPIO9_PS_En", 9, 1 },
|
|
{ "GPIO8_PS_En", 8, 1 },
|
|
{ "GPIO7_PS_En", 7, 1 },
|
|
{ "GPIO6_PS_En", 6, 1 },
|
|
{ "GPIO5_PS_En", 5, 1 },
|
|
{ "GPIO4_PS_En", 4, 1 },
|
|
{ "GPIO3_PS_En", 3, 1 },
|
|
{ "GPIO2_PS_En", 2, 1 },
|
|
{ "GPIO1_PS_En", 1, 1 },
|
|
{ "GPIO0_PS_En", 0, 1 },
|
|
{ "DBG_EFUSE_BYTE16_19", 0x6120, 0 },
|
|
{ "DBG_EFUSE_BYTE20_23", 0x6124, 0 },
|
|
{ "DBG_EFUSE_BYTE24_27", 0x6128, 0 },
|
|
{ "DBG_EFUSE_BYTE28_31", 0x612c, 0 },
|
|
{ "DBG_EFUSE_BYTE32_35", 0x6130, 0 },
|
|
{ "DBG_EFUSE_BYTE36_39", 0x6134, 0 },
|
|
{ "DBG_EFUSE_BYTE40_43", 0x6138, 0 },
|
|
{ "DBG_EFUSE_BYTE44_47", 0x613c, 0 },
|
|
{ "DBG_EFUSE_BYTE48_51", 0x6140, 0 },
|
|
{ "DBG_EFUSE_BYTE52_55", 0x6144, 0 },
|
|
{ "DBG_EFUSE_BYTE56_59", 0x6148, 0 },
|
|
{ "DBG_EFUSE_BYTE60_63", 0x614c, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_ma_regs[] = {
|
|
{ "MA_CLIENT0_RD_LATENCY_THRESHOLD", 0x7700, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT0_WR_LATENCY_THRESHOLD", 0x7704, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT1_RD_LATENCY_THRESHOLD", 0x7708, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT1_WR_LATENCY_THRESHOLD", 0x770c, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT2_RD_LATENCY_THRESHOLD", 0x7710, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT2_WR_LATENCY_THRESHOLD", 0x7714, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT3_RD_LATENCY_THRESHOLD", 0x7718, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT3_WR_LATENCY_THRESHOLD", 0x771c, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT4_RD_LATENCY_THRESHOLD", 0x7720, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT4_WR_LATENCY_THRESHOLD", 0x7724, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT5_RD_LATENCY_THRESHOLD", 0x7728, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT5_WR_LATENCY_THRESHOLD", 0x772c, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT6_RD_LATENCY_THRESHOLD", 0x7730, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT6_WR_LATENCY_THRESHOLD", 0x7734, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT7_RD_LATENCY_THRESHOLD", 0x7738, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT7_WR_LATENCY_THRESHOLD", 0x773c, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT8_RD_LATENCY_THRESHOLD", 0x7740, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT8_WR_LATENCY_THRESHOLD", 0x7744, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT9_RD_LATENCY_THRESHOLD", 0x7748, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT9_WR_LATENCY_THRESHOLD", 0x774c, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT10_RD_LATENCY_THRESHOLD", 0x7750, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT10_WR_LATENCY_THRESHOLD", 0x7754, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT11_RD_LATENCY_THRESHOLD", 0x7758, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT11_WR_LATENCY_THRESHOLD", 0x775c, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT12_RD_LATENCY_THRESHOLD", 0x7760, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_CLIENT12_WR_LATENCY_THRESHOLD", 0x7764, 0 },
|
|
{ "THRESHOLD1", 17, 15 },
|
|
{ "THRESHOLD1_EN", 16, 1 },
|
|
{ "THRESHOLD0", 1, 15 },
|
|
{ "THRESHOLD0_EN", 0, 1 },
|
|
{ "MA_SGE_TH0_DEBUG_CNT", 0x7768, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_SGE_TH1_DEBUG_CNT", 0x776c, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_ULPTX_DEBUG_CNT", 0x7770, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_ULPRX_DEBUG_CNT", 0x7774, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_ULPTXRX_DEBUG_CNT", 0x7778, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_TP_TH0_DEBUG_CNT", 0x777c, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_TP_TH1_DEBUG_CNT", 0x7780, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_LE_DEBUG_CNT", 0x7784, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_CIM_DEBUG_CNT", 0x7788, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_PCIE_DEBUG_CNT", 0x778c, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_PMTX_DEBUG_CNT", 0x7790, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_PMRX_DEBUG_CNT", 0x7794, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_HMA_DEBUG_CNT", 0x7798, 0 },
|
|
{ "DBG_READ_DATA_CNT", 24, 8 },
|
|
{ "DBG_READ_REQ_CNT", 16, 8 },
|
|
{ "DBG_WRITE_DATA_CNT", 8, 8 },
|
|
{ "DBG_WRITE_REQ_CNT", 0, 8 },
|
|
{ "MA_EDRAM0_BAR", 0x77c0, 0 },
|
|
{ "EDRAM0_BASE", 16, 12 },
|
|
{ "EDRAM0_SIZE", 0, 12 },
|
|
{ "MA_EDRAM1_BAR", 0x77c4, 0 },
|
|
{ "EDRAM1_BASE", 16, 12 },
|
|
{ "EDRAM1_SIZE", 0, 12 },
|
|
{ "MA_EXT_MEMORY0_BAR", 0x77c8, 0 },
|
|
{ "EXT_MEM0_BASE", 16, 12 },
|
|
{ "EXT_MEM0_SIZE", 0, 12 },
|
|
{ "MA_HOST_MEMORY_BAR", 0x77cc, 0 },
|
|
{ "HMA_BASE", 16, 12 },
|
|
{ "HMA_SIZE", 0, 12 },
|
|
{ "MA_EXT_MEM_PAGE_SIZE", 0x77d0, 0 },
|
|
{ "BRC_MODE1", 6, 1 },
|
|
{ "EXT_MEM_PAGE_SIZE1", 4, 2 },
|
|
{ "BRC_MODE", 2, 1 },
|
|
{ "EXT_MEM_PAGE_SIZE", 0, 2 },
|
|
{ "MA_ARB_CTRL", 0x77d4, 0 },
|
|
{ "DIS_BANK_FAIR", 2, 1 },
|
|
{ "DIS_PAGE_HINT", 1, 1 },
|
|
{ "DIS_ADV_ARB", 0, 1 },
|
|
{ "MA_TARGET_MEM_ENABLE", 0x77d8, 0 },
|
|
{ "HMA_MUX", 5, 1 },
|
|
{ "EXT_MEM1_ENABLE", 4, 1 },
|
|
{ "HMA_ENABLE", 3, 1 },
|
|
{ "EXT_MEM0_ENABLE", 2, 1 },
|
|
{ "EDRAM1_ENABLE", 1, 1 },
|
|
{ "EDRAM0_ENABLE", 0, 1 },
|
|
{ "MA_INT_ENABLE", 0x77dc, 0 },
|
|
{ "MEM_TO_INT_ENABLE", 2, 1 },
|
|
{ "MEM_PERR_INT_ENABLE", 1, 1 },
|
|
{ "MEM_WRAP_INT_ENABLE", 0, 1 },
|
|
{ "MA_INT_CAUSE", 0x77e0, 0 },
|
|
{ "MEM_TO_INT_CAUSE", 2, 1 },
|
|
{ "MEM_PERR_INT_CAUSE", 1, 1 },
|
|
{ "MEM_WRAP_INT_CAUSE", 0, 1 },
|
|
{ "MA_INT_WRAP_STATUS", 0x77e4, 0 },
|
|
{ "MEM_WRAP_ADDRESS", 4, 28 },
|
|
{ "MEM_WRAP_CLIENT_NUM", 0, 4 },
|
|
{ "MA_TP_THREAD1_MAPPER", 0x77e8, 0 },
|
|
{ "MA_SGE_THREAD1_MAPPER", 0x77ec, 0 },
|
|
{ "MA_PARITY_ERROR_ENABLE1", 0x77f0, 0 },
|
|
{ "TP_DMARBT_PAR_ERROR_EN", 31, 1 },
|
|
{ "LOGIC_FIFO_PAR_ERROR_EN", 30, 1 },
|
|
{ "ARB3_PAR_WRQUEUE_ERROR_EN", 29, 1 },
|
|
{ "ARB2_PAR_WRQUEUE_ERROR_EN", 28, 1 },
|
|
{ "ARB1_PAR_WRQUEUE_ERROR_EN", 27, 1 },
|
|
{ "ARB0_PAR_WRQUEUE_ERROR_EN", 26, 1 },
|
|
{ "ARB3_PAR_RDQUEUE_ERROR_EN", 25, 1 },
|
|
{ "ARB2_PAR_RDQUEUE_ERROR_EN", 24, 1 },
|
|
{ "ARB1_PAR_RDQUEUE_ERROR_EN", 23, 1 },
|
|
{ "ARB0_PAR_RDQUEUE_ERROR_EN", 22, 1 },
|
|
{ "CL10_PAR_WRQUEUE_ERROR_EN", 21, 1 },
|
|
{ "CL9_PAR_WRQUEUE_ERROR_EN", 20, 1 },
|
|
{ "CL8_PAR_WRQUEUE_ERROR_EN", 19, 1 },
|
|
{ "CL7_PAR_WRQUEUE_ERROR_EN", 18, 1 },
|
|
{ "CL6_PAR_WRQUEUE_ERROR_EN", 17, 1 },
|
|
{ "CL5_PAR_WRQUEUE_ERROR_EN", 16, 1 },
|
|
{ "CL4_PAR_WRQUEUE_ERROR_EN", 15, 1 },
|
|
{ "CL3_PAR_WRQUEUE_ERROR_EN", 14, 1 },
|
|
{ "CL2_PAR_WRQUEUE_ERROR_EN", 13, 1 },
|
|
{ "CL1_PAR_WRQUEUE_ERROR_EN", 12, 1 },
|
|
{ "CL0_PAR_WRQUEUE_ERROR_EN", 11, 1 },
|
|
{ "CL10_PAR_RDQUEUE_ERROR_EN", 10, 1 },
|
|
{ "CL9_PAR_RDQUEUE_ERROR_EN", 9, 1 },
|
|
{ "CL8_PAR_RDQUEUE_ERROR_EN", 8, 1 },
|
|
{ "CL7_PAR_RDQUEUE_ERROR_EN", 7, 1 },
|
|
{ "CL6_PAR_RDQUEUE_ERROR_EN", 6, 1 },
|
|
{ "CL5_PAR_RDQUEUE_ERROR_EN", 5, 1 },
|
|
{ "CL4_PAR_RDQUEUE_ERROR_EN", 4, 1 },
|
|
{ "CL3_PAR_RDQUEUE_ERROR_EN", 3, 1 },
|
|
{ "CL2_PAR_RDQUEUE_ERROR_EN", 2, 1 },
|
|
{ "CL1_PAR_RDQUEUE_ERROR_EN", 1, 1 },
|
|
{ "CL0_PAR_RDQUEUE_ERROR_EN", 0, 1 },
|
|
{ "MA_PARITY_ERROR_STATUS1", 0x77f4, 0 },
|
|
{ "TP_DMARBT_PAR_ERROR", 31, 1 },
|
|
{ "LOGIC_FIFO_PAR_ERROR", 30, 1 },
|
|
{ "ARB3_PAR_WRQUEUE_ERROR", 29, 1 },
|
|
{ "ARB2_PAR_WRQUEUE_ERROR", 28, 1 },
|
|
{ "ARB1_PAR_WRQUEUE_ERROR", 27, 1 },
|
|
{ "ARB0_PAR_WRQUEUE_ERROR", 26, 1 },
|
|
{ "ARB3_PAR_RDQUEUE_ERROR", 25, 1 },
|
|
{ "ARB2_PAR_RDQUEUE_ERROR", 24, 1 },
|
|
{ "ARB1_PAR_RDQUEUE_ERROR", 23, 1 },
|
|
{ "ARB0_PAR_RDQUEUE_ERROR", 22, 1 },
|
|
{ "CL10_PAR_WRQUEUE_ERROR", 21, 1 },
|
|
{ "CL9_PAR_WRQUEUE_ERROR", 20, 1 },
|
|
{ "CL8_PAR_WRQUEUE_ERROR", 19, 1 },
|
|
{ "CL7_PAR_WRQUEUE_ERROR", 18, 1 },
|
|
{ "CL6_PAR_WRQUEUE_ERROR", 17, 1 },
|
|
{ "CL5_PAR_WRQUEUE_ERROR", 16, 1 },
|
|
{ "CL4_PAR_WRQUEUE_ERROR", 15, 1 },
|
|
{ "CL3_PAR_WRQUEUE_ERROR", 14, 1 },
|
|
{ "CL2_PAR_WRQUEUE_ERROR", 13, 1 },
|
|
{ "CL1_PAR_WRQUEUE_ERROR", 12, 1 },
|
|
{ "CL0_PAR_WRQUEUE_ERROR", 11, 1 },
|
|
{ "CL10_PAR_RDQUEUE_ERROR", 10, 1 },
|
|
{ "CL9_PAR_RDQUEUE_ERROR", 9, 1 },
|
|
{ "CL8_PAR_RDQUEUE_ERROR", 8, 1 },
|
|
{ "CL7_PAR_RDQUEUE_ERROR", 7, 1 },
|
|
{ "CL6_PAR_RDQUEUE_ERROR", 6, 1 },
|
|
{ "CL5_PAR_RDQUEUE_ERROR", 5, 1 },
|
|
{ "CL4_PAR_RDQUEUE_ERROR", 4, 1 },
|
|
{ "CL3_PAR_RDQUEUE_ERROR", 3, 1 },
|
|
{ "CL2_PAR_RDQUEUE_ERROR", 2, 1 },
|
|
{ "CL1_PAR_RDQUEUE_ERROR", 1, 1 },
|
|
{ "CL0_PAR_RDQUEUE_ERROR", 0, 1 },
|
|
{ "MA_SGE_PCIE_COHERANCY_CTRL", 0x77f8, 0 },
|
|
{ "BONUS_REG", 6, 26 },
|
|
{ "COHERANCY_CMD_TYPE", 4, 2 },
|
|
{ "COHERANCY_THREAD_NUM", 1, 3 },
|
|
{ "COHERANCY_ENABLE", 0, 1 },
|
|
{ "MA_ERROR_ENABLE", 0x77fc, 0 },
|
|
{ "FUTURE_EXPANSION", 1, 31 },
|
|
{ "UE_ENABLE", 0, 1 },
|
|
{ "MA_PARITY_ERROR_ENABLE2", 0x7800, 0 },
|
|
{ "ARB4_PAR_WRQUEUE_ERROR_EN", 1, 1 },
|
|
{ "ARB4_PAR_RDQUEUE_ERROR_EN", 0, 1 },
|
|
{ "MA_PARITY_ERROR_STATUS2", 0x7804, 0 },
|
|
{ "ARB4_PAR_WRQUEUE_ERROR", 1, 1 },
|
|
{ "ARB4_PAR_RDQUEUE_ERROR", 0, 1 },
|
|
{ "MA_EXT_MEMORY1_BAR", 0x7808, 0 },
|
|
{ "EXT_MEM1_BASE", 16, 12 },
|
|
{ "EXT_MEM1_SIZE", 0, 12 },
|
|
{ "MA_PMTX_THROTTLE", 0x780c, 0 },
|
|
{ "FL_ENABLE", 31, 1 },
|
|
{ "FL_LIMIT", 0, 8 },
|
|
{ "MA_PMRX_THROTTLE", 0x7810, 0 },
|
|
{ "FL_ENABLE", 31, 1 },
|
|
{ "FL_LIMIT", 0, 8 },
|
|
{ "MA_SGE_TH0_WRDATA_CNT", 0x7814, 0 },
|
|
{ "MA_SGE_TH1_WRDATA_CNT", 0x7818, 0 },
|
|
{ "MA_ULPTX_WRDATA_CNT", 0x781c, 0 },
|
|
{ "MA_ULPRX_WRDATA_CNT", 0x7820, 0 },
|
|
{ "MA_ULPTXRX_WRDATA_CNT", 0x7824, 0 },
|
|
{ "MA_TP_TH0_WRDATA_CNT", 0x7828, 0 },
|
|
{ "MA_TP_TH1_WRDATA_CNT", 0x782c, 0 },
|
|
{ "MA_LE_WRDATA_CNT", 0x7830, 0 },
|
|
{ "MA_CIM_WRDATA_CNT", 0x7834, 0 },
|
|
{ "MA_PCIE_WRDATA_CNT", 0x7838, 0 },
|
|
{ "MA_PMTX_WRDATA_CNT", 0x783c, 0 },
|
|
{ "MA_PMRX_WRDATA_CNT", 0x7840, 0 },
|
|
{ "MA_HMA_WRDATA_CNT", 0x7844, 0 },
|
|
{ "MA_SGE_TH0_RDDATA_CNT", 0x7848, 0 },
|
|
{ "MA_SGE_TH1_RDDATA_CNT", 0x784c, 0 },
|
|
{ "MA_ULPTX_RDDATA_CNT", 0x7850, 0 },
|
|
{ "MA_ULPRX_RDDATA_CNT", 0x7854, 0 },
|
|
{ "MA_ULPTXRX_RDDATA_CNT", 0x7858, 0 },
|
|
{ "MA_TP_TH0_RDDATA_CNT", 0x785c, 0 },
|
|
{ "MA_TP_TH1_RDDATA_CNT", 0x7860, 0 },
|
|
{ "MA_LE_RDDATA_CNT", 0x7864, 0 },
|
|
{ "MA_CIM_RDDATA_CNT", 0x7868, 0 },
|
|
{ "MA_PCIE_RDDATA_CNT", 0x786c, 0 },
|
|
{ "MA_PMTX_RDDATA_CNT", 0x7870, 0 },
|
|
{ "MA_PMRX_RDDATA_CNT", 0x7874, 0 },
|
|
{ "MA_HMA_RDDATA_CNT", 0x7878, 0 },
|
|
{ "MA_EDRAM0_WRDATA_CNT1", 0x787c, 0 },
|
|
{ "MA_EDRAM0_WRDATA_CNT0", 0x7880, 0 },
|
|
{ "MA_EDRAM1_WRDATA_CNT1", 0x7884, 0 },
|
|
{ "MA_EDRAM1_WRDATA_CNT0", 0x7888, 0 },
|
|
{ "MA_EXT_MEMORY0_WRDATA_CNT1", 0x788c, 0 },
|
|
{ "MA_EXT_MEMORY0_WRDATA_CNT0", 0x7890, 0 },
|
|
{ "MA_HOST_MEMORY_WRDATA_CNT1", 0x7894, 0 },
|
|
{ "MA_HOST_MEMORY_WRDATA_CNT0", 0x7898, 0 },
|
|
{ "MA_EXT_MEMORY1_WRDATA_CNT1", 0x789c, 0 },
|
|
{ "MA_EXT_MEMORY1_WRDATA_CNT0", 0x78a0, 0 },
|
|
{ "MA_EDRAM0_RDDATA_CNT1", 0x78a4, 0 },
|
|
{ "MA_EDRAM0_RDDATA_CNT0", 0x78a8, 0 },
|
|
{ "MA_EDRAM1_RDDATA_CNT1", 0x78ac, 0 },
|
|
{ "MA_EDRAM1_RDDATA_CNT0", 0x78b0, 0 },
|
|
{ "MA_EXT_MEMORY0_RDDATA_CNT1", 0x78b4, 0 },
|
|
{ "MA_EXT_MEMORY0_RDDATA_CNT0", 0x78b8, 0 },
|
|
{ "MA_HOST_MEMORY_RDDATA_CNT1", 0x78bc, 0 },
|
|
{ "MA_HOST_MEMORY_RDDATA_CNT0", 0x78c0, 0 },
|
|
{ "MA_EXT_MEMORY1_RDDATA_CNT1", 0x78c4, 0 },
|
|
{ "MA_EXT_MEMORY1_RDDATA_CNT0", 0x78c8, 0 },
|
|
{ "MA_TIMEOUT_CFG", 0x78cc, 0 },
|
|
{ "CLR", 31, 1 },
|
|
{ "CNT_LOCK", 30, 1 },
|
|
{ "WRN", 24, 1 },
|
|
{ "DIR", 23, 1 },
|
|
{ "TYPE", 22, 1 },
|
|
{ "CLIENT", 16, 4 },
|
|
{ "DELAY", 0, 16 },
|
|
{ "MA_TIMEOUT_CNT", 0x78d0, 0 },
|
|
{ "DIR", 23, 1 },
|
|
{ "TYPE", 22, 1 },
|
|
{ "CLIENT", 16, 4 },
|
|
{ "CNT_VAL", 0, 16 },
|
|
{ "MA_WRITE_TIMEOUT_ERROR_ENABLE", 0x78d4, 0 },
|
|
{ "FUTURE_CEXPANSION", 29, 3 },
|
|
{ "CL12_WR_CMD_TO_EN", 28, 1 },
|
|
{ "CL11_WR_CMD_TO_EN", 27, 1 },
|
|
{ "CL10_WR_CMD_TO_EN", 26, 1 },
|
|
{ "CL9_WR_CMD_TO_EN", 25, 1 },
|
|
{ "CL8_WR_CMD_TO_EN", 24, 1 },
|
|
{ "CL7_WR_CMD_TO_EN", 23, 1 },
|
|
{ "CL6_WR_CMD_TO_EN", 22, 1 },
|
|
{ "CL5_WR_CMD_TO_EN", 21, 1 },
|
|
{ "CL4_WR_CMD_TO_EN", 20, 1 },
|
|
{ "CL3_WR_CMD_TO_EN", 19, 1 },
|
|
{ "CL2_WR_CMD_TO_EN", 18, 1 },
|
|
{ "CL1_WR_CMD_TO_EN", 17, 1 },
|
|
{ "CL0_WR_CMD_TO_EN", 16, 1 },
|
|
{ "FUTURE_DEXPANSION", 13, 3 },
|
|
{ "CL12_WR_DATA_TO_EN", 12, 1 },
|
|
{ "CL11_WR_DATA_TO_EN", 11, 1 },
|
|
{ "CL10_WR_DATA_TO_EN", 10, 1 },
|
|
{ "CL9_WR_DATA_TO_EN", 9, 1 },
|
|
{ "CL8_WR_DATA_TO_EN", 8, 1 },
|
|
{ "CL7_WR_DATA_TO_EN", 7, 1 },
|
|
{ "CL6_WR_DATA_TO_EN", 6, 1 },
|
|
{ "CL5_WR_DATA_TO_EN", 5, 1 },
|
|
{ "CL4_WR_DATA_TO_EN", 4, 1 },
|
|
{ "CL3_WR_DATA_TO_EN", 3, 1 },
|
|
{ "CL2_WR_DATA_TO_EN", 2, 1 },
|
|
{ "CL1_WR_DATA_TO_EN", 1, 1 },
|
|
{ "CL0_WR_DATA_TO_EN", 0, 1 },
|
|
{ "MA_WRITE_TIMEOUT_ERROR_STATUS", 0x78d8, 0 },
|
|
{ "FUTURE_CEXPANSION", 29, 3 },
|
|
{ "CL12_WR_CMD_TO_ERROR", 28, 1 },
|
|
{ "CL11_WR_CMD_TO_ERROR", 27, 1 },
|
|
{ "CL10_WR_CMD_TO_ERROR", 26, 1 },
|
|
{ "CL9_WR_CMD_TO_ERROR", 25, 1 },
|
|
{ "CL8_WR_CMD_TO_ERROR", 24, 1 },
|
|
{ "CL7_WR_CMD_TO_ERROR", 23, 1 },
|
|
{ "CL6_WR_CMD_TO_ERROR", 22, 1 },
|
|
{ "CL5_WR_CMD_TO_ERROR", 21, 1 },
|
|
{ "CL4_WR_CMD_TO_ERROR", 20, 1 },
|
|
{ "CL3_WR_CMD_TO_ERROR", 19, 1 },
|
|
{ "CL2_WR_CMD_TO_ERROR", 18, 1 },
|
|
{ "CL1_WR_CMD_TO_ERROR", 17, 1 },
|
|
{ "CL0_WR_CMD_TO_ERROR", 16, 1 },
|
|
{ "FUTURE_DEXPANSION", 13, 3 },
|
|
{ "CL12_WR_DATA_TO_ERROR", 12, 1 },
|
|
{ "CL11_WR_DATA_TO_ERROR", 11, 1 },
|
|
{ "CL10_WR_DATA_TO_ERROR", 10, 1 },
|
|
{ "CL9_WR_DATA_TO_ERROR", 9, 1 },
|
|
{ "CL8_WR_DATA_TO_ERROR", 8, 1 },
|
|
{ "CL7_WR_DATA_TO_ERROR", 7, 1 },
|
|
{ "CL6_WR_DATA_TO_ERROR", 6, 1 },
|
|
{ "CL5_WR_DATA_TO_ERROR", 5, 1 },
|
|
{ "CL4_WR_DATA_TO_ERROR", 4, 1 },
|
|
{ "CL3_WR_DATA_TO_ERROR", 3, 1 },
|
|
{ "CL2_WR_DATA_TO_ERROR", 2, 1 },
|
|
{ "CL1_WR_DATA_TO_ERROR", 1, 1 },
|
|
{ "CL0_WR_DATA_TO_ERROR", 0, 1 },
|
|
{ "MA_READ_TIMEOUT_ERROR_ENABLE", 0x78dc, 0 },
|
|
{ "FUTURE_CEXPANSION", 29, 3 },
|
|
{ "CL12_RD_CMD_TO_EN", 28, 1 },
|
|
{ "CL11_RD_CMD_TO_EN", 27, 1 },
|
|
{ "CL10_RD_CMD_TO_EN", 26, 1 },
|
|
{ "CL9_RD_CMD_TO_EN", 25, 1 },
|
|
{ "CL8_RD_CMD_TO_EN", 24, 1 },
|
|
{ "CL7_RD_CMD_TO_EN", 23, 1 },
|
|
{ "CL6_RD_CMD_TO_EN", 22, 1 },
|
|
{ "CL5_RD_CMD_TO_EN", 21, 1 },
|
|
{ "CL4_RD_CMD_TO_EN", 20, 1 },
|
|
{ "CL3_RD_CMD_TO_EN", 19, 1 },
|
|
{ "CL2_RD_CMD_TO_EN", 18, 1 },
|
|
{ "CL1_RD_CMD_TO_EN", 17, 1 },
|
|
{ "CL0_RD_CMD_TO_EN", 16, 1 },
|
|
{ "FUTURE_DEXPANSION", 13, 3 },
|
|
{ "CL12_RD_DATA_TO_EN", 12, 1 },
|
|
{ "CL11_RD_DATA_TO_EN", 11, 1 },
|
|
{ "CL10_RD_DATA_TO_EN", 10, 1 },
|
|
{ "CL9_RD_DATA_TO_EN", 9, 1 },
|
|
{ "CL8_RD_DATA_TO_EN", 8, 1 },
|
|
{ "CL7_RD_DATA_TO_EN", 7, 1 },
|
|
{ "CL6_RD_DATA_TO_EN", 6, 1 },
|
|
{ "CL5_RD_DATA_TO_EN", 5, 1 },
|
|
{ "CL4_RD_DATA_TO_EN", 4, 1 },
|
|
{ "CL3_RD_DATA_TO_EN", 3, 1 },
|
|
{ "CL2_RD_DATA_TO_EN", 2, 1 },
|
|
{ "CL1_RD_DATA_TO_EN", 1, 1 },
|
|
{ "CL0_RD_DATA_TO_EN", 0, 1 },
|
|
{ "MA_READ_TIMEOUT_ERROR_STATUS", 0x78e0, 0 },
|
|
{ "FUTURE_CEXPANSION", 29, 3 },
|
|
{ "CL12_RD_CMD_TO_ERROR", 28, 1 },
|
|
{ "CL11_RD_CMD_TO_ERROR", 27, 1 },
|
|
{ "CL10_RD_CMD_TO_ERROR", 26, 1 },
|
|
{ "CL9_RD_CMD_TO_ERROR", 25, 1 },
|
|
{ "CL8_RD_CMD_TO_ERROR", 24, 1 },
|
|
{ "CL7_RD_CMD_TO_ERROR", 23, 1 },
|
|
{ "CL6_RD_CMD_TO_ERROR", 22, 1 },
|
|
{ "CL5_RD_CMD_TO_ERROR", 21, 1 },
|
|
{ "CL4_RD_CMD_TO_ERROR", 20, 1 },
|
|
{ "CL3_RD_CMD_TO_ERROR", 19, 1 },
|
|
{ "CL2_RD_CMD_TO_ERROR", 18, 1 },
|
|
{ "CL1_RD_CMD_TO_ERROR", 17, 1 },
|
|
{ "CL0_RD_CMD_TO_ERROR", 16, 1 },
|
|
{ "FUTURE_DEXPANSION", 13, 3 },
|
|
{ "CL12_RD_DATA_TO_ERROR", 12, 1 },
|
|
{ "CL11_RD_DATA_TO_ERROR", 11, 1 },
|
|
{ "CL10_RD_DATA_TO_ERROR", 10, 1 },
|
|
{ "CL9_RD_DATA_TO_ERROR", 9, 1 },
|
|
{ "CL8_RD_DATA_TO_ERROR", 8, 1 },
|
|
{ "CL7_RD_DATA_TO_ERROR", 7, 1 },
|
|
{ "CL6_RD_DATA_TO_ERROR", 6, 1 },
|
|
{ "CL5_RD_DATA_TO_ERROR", 5, 1 },
|
|
{ "CL4_RD_DATA_TO_ERROR", 4, 1 },
|
|
{ "CL3_RD_DATA_TO_ERROR", 3, 1 },
|
|
{ "CL2_RD_DATA_TO_ERROR", 2, 1 },
|
|
{ "CL1_RD_DATA_TO_ERROR", 1, 1 },
|
|
{ "CL0_RD_DATA_TO_ERROR", 0, 1 },
|
|
{ "MA_BKP_CNT_SEL", 0x78e4, 0 },
|
|
{ "TYPE", 30, 2 },
|
|
{ "CLIENT", 24, 4 },
|
|
{ "MA_BKP_CNT", 0x78e8, 0 },
|
|
{ "MA_WRT_ARB", 0x78ec, 0 },
|
|
{ "WRT_EN", 31, 1 },
|
|
{ "WR_TIM", 16, 8 },
|
|
{ "RD_WIN", 8, 8 },
|
|
{ "WR_WIN", 0, 8 },
|
|
{ "MA_IF_PARITY_ERROR_ENABLE", 0x78f0, 0 },
|
|
{ "FUTURE_DEXPANSION", 13, 19 },
|
|
{ "CL12_IF_PAR_EN", 12, 1 },
|
|
{ "CL11_IF_PAR_EN", 11, 1 },
|
|
{ "CL10_IF_PAR_EN", 10, 1 },
|
|
{ "CL9_IF_PAR_EN", 9, 1 },
|
|
{ "CL8_IF_PAR_EN", 8, 1 },
|
|
{ "CL7_IF_PAR_EN", 7, 1 },
|
|
{ "CL6_IF_PAR_EN", 6, 1 },
|
|
{ "CL5_IF_PAR_EN", 5, 1 },
|
|
{ "CL4_IF_PAR_EN", 4, 1 },
|
|
{ "CL3_IF_PAR_EN", 3, 1 },
|
|
{ "CL2_IF_PAR_EN", 2, 1 },
|
|
{ "CL1_IF_PAR_EN", 1, 1 },
|
|
{ "CL0_IF_PAR_EN", 0, 1 },
|
|
{ "MA_IF_PARITY_ERROR_STATUS", 0x78f4, 0 },
|
|
{ "FUTURE_DEXPANSION", 13, 19 },
|
|
{ "CL12_IF_PAR_ERROR", 12, 1 },
|
|
{ "CL11_IF_PAR_ERROR", 11, 1 },
|
|
{ "CL10_IF_PAR_ERROR", 10, 1 },
|
|
{ "CL9_IF_PAR_ERROR", 9, 1 },
|
|
{ "CL8_IF_PAR_ERROR", 8, 1 },
|
|
{ "CL7_IF_PAR_ERROR", 7, 1 },
|
|
{ "CL6_IF_PAR_ERROR", 6, 1 },
|
|
{ "CL5_IF_PAR_ERROR", 5, 1 },
|
|
{ "CL4_IF_PAR_ERROR", 4, 1 },
|
|
{ "CL3_IF_PAR_ERROR", 3, 1 },
|
|
{ "CL2_IF_PAR_ERROR", 2, 1 },
|
|
{ "CL1_IF_PAR_ERROR", 1, 1 },
|
|
{ "CL0_IF_PAR_ERROR", 0, 1 },
|
|
{ "MA_LOCAL_DEBUG_CFG", 0x78f8, 0 },
|
|
{ "DEBUG_OR", 15, 1 },
|
|
{ "DEBUG_HI", 14, 1 },
|
|
{ "DEBUG_RPT", 13, 1 },
|
|
{ "DEBUGPAGE", 10, 3 },
|
|
{ "DEBUGSELH", 5, 5 },
|
|
{ "DEBUGSELL", 0, 5 },
|
|
{ "MA_LOCAL_DEBUG_RPT", 0x78fc, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_cim_regs[] = {
|
|
{ "CIM_BOOT_CFG", 0x7b00, 0 },
|
|
{ "BootAddr", 8, 24 },
|
|
{ "uPGen", 2, 6 },
|
|
{ "BootSdram", 1, 1 },
|
|
{ "uPCRst", 0, 1 },
|
|
{ "CIM_BOOT_LEN", 0x7bf0, 0 },
|
|
{ "BootLen", 4, 28 },
|
|
{ "CIM_FLASH_BASE_ADDR", 0x7b04, 0 },
|
|
{ "FlashBaseAddr", 6, 18 },
|
|
{ "CIM_FLASH_ADDR_SIZE", 0x7b08, 0 },
|
|
{ "FlashAddrSize", 4, 20 },
|
|
{ "CIM_EEPROM_BASE_ADDR", 0x7b0c, 0 },
|
|
{ "EEPROMBaseAddr", 6, 18 },
|
|
{ "CIM_EEPROM_ADDR_SIZE", 0x7b10, 0 },
|
|
{ "EEPROMAddrSize", 4, 20 },
|
|
{ "CIM_SDRAM_BASE_ADDR", 0x7b14, 0 },
|
|
{ "SdramBaseAddr", 6, 26 },
|
|
{ "CIM_SDRAM_ADDR_SIZE", 0x7b18, 0 },
|
|
{ "SdramAddrSize", 4, 28 },
|
|
{ "CIM_EXTMEM2_BASE_ADDR", 0x7b1c, 0 },
|
|
{ "ExtMem2BaseAddr", 6, 26 },
|
|
{ "CIM_EXTMEM2_ADDR_SIZE", 0x7b20, 0 },
|
|
{ "ExtMem2AddrSize", 4, 28 },
|
|
{ "CIM_UP_SPARE_INT", 0x7b24, 0 },
|
|
{ "TDebugInt", 4, 1 },
|
|
{ "BootVecSel", 3, 1 },
|
|
{ "uPSpareInt", 0, 3 },
|
|
{ "CIM_HOST_INT_ENABLE", 0x7b28, 0 },
|
|
{ "ma_cim_IntfPerr", 28, 1 },
|
|
{ "PLCIM_MstRspDataParErr", 27, 1 },
|
|
{ "NCSI2CIMIntfParErr", 26, 1 },
|
|
{ "SGE2CIMIntfParErr", 25, 1 },
|
|
{ "ULP2CIMIntfParErr", 24, 1 },
|
|
{ "TP2CIMIntfParErr", 23, 1 },
|
|
{ "OBQSGERx1ParErr", 22, 1 },
|
|
{ "OBQSGERx0ParErr", 21, 1 },
|
|
{ "TieQOutParErrIntEn", 20, 1 },
|
|
{ "TieQInParErrIntEn", 19, 1 },
|
|
{ "MBHostParErr", 18, 1 },
|
|
{ "MBuPParErr", 17, 1 },
|
|
{ "IBQTP0ParErr", 16, 1 },
|
|
{ "IBQTP1ParErr", 15, 1 },
|
|
{ "IBQULPParErr", 14, 1 },
|
|
{ "IBQSGELOParErr", 13, 1 },
|
|
{ "IBQSGEHIParErr", 12, 1 },
|
|
{ "IBQNCSIParErr", 11, 1 },
|
|
{ "OBQULP0ParErr", 10, 1 },
|
|
{ "OBQULP1ParErr", 9, 1 },
|
|
{ "OBQULP2ParErr", 8, 1 },
|
|
{ "OBQULP3ParErr", 7, 1 },
|
|
{ "OBQSGEParErr", 6, 1 },
|
|
{ "OBQNCSIParErr", 5, 1 },
|
|
{ "Timer1IntEn", 3, 1 },
|
|
{ "Timer0IntEn", 2, 1 },
|
|
{ "PrefDropIntEn", 1, 1 },
|
|
{ "CIM_HOST_INT_CAUSE", 0x7b2c, 0 },
|
|
{ "ma_cim_IntfPerr", 28, 1 },
|
|
{ "PLCIM_MstRspDataParErr", 27, 1 },
|
|
{ "NCSI2CIMIntfParErr", 26, 1 },
|
|
{ "SGE2CIMIntfParErr", 25, 1 },
|
|
{ "ULP2CIMIntfParErr", 24, 1 },
|
|
{ "TP2CIMIntfParErr", 23, 1 },
|
|
{ "OBQSGERx1ParErr", 22, 1 },
|
|
{ "OBQSGERx0ParErr", 21, 1 },
|
|
{ "TieQOutParErrInt", 20, 1 },
|
|
{ "TieQInParErrInt", 19, 1 },
|
|
{ "MBHostParErr", 18, 1 },
|
|
{ "IBQTP0ParErr", 16, 1 },
|
|
{ "IBQTP1ParErr", 15, 1 },
|
|
{ "IBQULPParErr", 14, 1 },
|
|
{ "IBQSGELOParErr", 13, 1 },
|
|
{ "IBQSGEHIParErr", 12, 1 },
|
|
{ "IBQNCSIParErr", 11, 1 },
|
|
{ "OBQULP0ParErr", 10, 1 },
|
|
{ "OBQULP1ParErr", 9, 1 },
|
|
{ "OBQULP2ParErr", 8, 1 },
|
|
{ "OBQULP3ParErr", 7, 1 },
|
|
{ "OBQSGEParErr", 6, 1 },
|
|
{ "OBQNCSIParErr", 5, 1 },
|
|
{ "Timer1Int", 3, 1 },
|
|
{ "Timer0Int", 2, 1 },
|
|
{ "PrefDropInt", 1, 1 },
|
|
{ "uPAccNonZero", 0, 1 },
|
|
{ "CIM_HOST_UPACC_INT_ENABLE", 0x7b30, 0 },
|
|
{ "EEPROMWRIntEn", 30, 1 },
|
|
{ "TimeOutMAIntEn", 29, 1 },
|
|
{ "TimeOutIntEn", 28, 1 },
|
|
{ "RspOvrLookupIntEn", 27, 1 },
|
|
{ "ReqOvrLookupIntEn", 26, 1 },
|
|
{ "BlkWrPlIntEn", 25, 1 },
|
|
{ "BlkRdPlIntEn", 24, 1 },
|
|
{ "SglWrPlIntEn", 23, 1 },
|
|
{ "SglRdPlIntEn", 22, 1 },
|
|
{ "BlkWrCtlIntEn", 21, 1 },
|
|
{ "BlkRdCtlIntEn", 20, 1 },
|
|
{ "SglWrCtlIntEn", 19, 1 },
|
|
{ "SglRdCtlIntEn", 18, 1 },
|
|
{ "BlkWrEEPROMIntEn", 17, 1 },
|
|
{ "BlkRdEEPROMIntEn", 16, 1 },
|
|
{ "SglWrEEPROMIntEn", 15, 1 },
|
|
{ "SglRdEEPROMIntEn", 14, 1 },
|
|
{ "BlkWrFlashIntEn", 13, 1 },
|
|
{ "BlkRdFlashIntEn", 12, 1 },
|
|
{ "SglWrFlashIntEn", 11, 1 },
|
|
{ "SglRdFlashIntEn", 10, 1 },
|
|
{ "BlkWrBootIntEn", 9, 1 },
|
|
{ "BlkRdBootIntEn", 8, 1 },
|
|
{ "SglWrBootIntEn", 7, 1 },
|
|
{ "SglRdBootIntEn", 6, 1 },
|
|
{ "IllWrBEIntEn", 5, 1 },
|
|
{ "IllRdBEIntEn", 4, 1 },
|
|
{ "IllRdIntEn", 3, 1 },
|
|
{ "IllWrIntEn", 2, 1 },
|
|
{ "IllTransIntEn", 1, 1 },
|
|
{ "RsvdSpaceIntEn", 0, 1 },
|
|
{ "CIM_HOST_UPACC_INT_CAUSE", 0x7b34, 0 },
|
|
{ "EEPROMWRInt", 30, 1 },
|
|
{ "TimeOutMAInt", 29, 1 },
|
|
{ "TimeOutInt", 28, 1 },
|
|
{ "RspOvrLookupInt", 27, 1 },
|
|
{ "ReqOvrLookupInt", 26, 1 },
|
|
{ "BlkWrPlInt", 25, 1 },
|
|
{ "BlkRdPlInt", 24, 1 },
|
|
{ "SglWrPlInt", 23, 1 },
|
|
{ "SglRdPlInt", 22, 1 },
|
|
{ "BlkWrCtlInt", 21, 1 },
|
|
{ "BlkRdCtlInt", 20, 1 },
|
|
{ "SglWrCtlInt", 19, 1 },
|
|
{ "SglRdCtlInt", 18, 1 },
|
|
{ "BlkWrEEPROMInt", 17, 1 },
|
|
{ "BlkRdEEPROMInt", 16, 1 },
|
|
{ "SglWrEEPROMInt", 15, 1 },
|
|
{ "SglRdEEPROMInt", 14, 1 },
|
|
{ "BlkWrFlashInt", 13, 1 },
|
|
{ "BlkRdFlashInt", 12, 1 },
|
|
{ "SglWrFlashInt", 11, 1 },
|
|
{ "SglRdFlashInt", 10, 1 },
|
|
{ "BlkWrBootInt", 9, 1 },
|
|
{ "BlkRdBootInt", 8, 1 },
|
|
{ "SglWrBootInt", 7, 1 },
|
|
{ "SglRdBootInt", 6, 1 },
|
|
{ "IllWrBEInt", 5, 1 },
|
|
{ "IllRdBEInt", 4, 1 },
|
|
{ "IllRdInt", 3, 1 },
|
|
{ "IllWrInt", 2, 1 },
|
|
{ "IllTransInt", 1, 1 },
|
|
{ "RsvdSpaceInt", 0, 1 },
|
|
{ "CIM_UP_INT_ENABLE", 0x7b38, 0 },
|
|
{ "ma_cim_IntfPerr", 28, 1 },
|
|
{ "PLCIM_MstRspDataParErr", 27, 1 },
|
|
{ "NCSI2CIMIntfParErr", 26, 1 },
|
|
{ "SGE2CIMIntfParErr", 25, 1 },
|
|
{ "ULP2CIMIntfParErr", 24, 1 },
|
|
{ "TP2CIMIntfParErr", 23, 1 },
|
|
{ "OBQSGERx1ParErr", 22, 1 },
|
|
{ "OBQSGERx0ParErr", 21, 1 },
|
|
{ "TieQOutParErrIntEn", 20, 1 },
|
|
{ "TieQInParErrIntEn", 19, 1 },
|
|
{ "MBHostParErr", 18, 1 },
|
|
{ "MBuPParErr", 17, 1 },
|
|
{ "IBQTP0ParErr", 16, 1 },
|
|
{ "IBQTP1ParErr", 15, 1 },
|
|
{ "IBQULPParErr", 14, 1 },
|
|
{ "IBQSGELOParErr", 13, 1 },
|
|
{ "IBQSGEHIParErr", 12, 1 },
|
|
{ "IBQNCSIParErr", 11, 1 },
|
|
{ "OBQULP0ParErr", 10, 1 },
|
|
{ "OBQULP1ParErr", 9, 1 },
|
|
{ "OBQULP2ParErr", 8, 1 },
|
|
{ "OBQULP3ParErr", 7, 1 },
|
|
{ "OBQSGEParErr", 6, 1 },
|
|
{ "OBQNCSIParErr", 5, 1 },
|
|
{ "MstPlIntEn", 4, 1 },
|
|
{ "Timer1IntEn", 3, 1 },
|
|
{ "Timer0IntEn", 2, 1 },
|
|
{ "PrefDropIntEn", 1, 1 },
|
|
{ "CIM_UP_INT_CAUSE", 0x7b3c, 0 },
|
|
{ "ma_cim_IntfPerr", 28, 1 },
|
|
{ "PLCIM_MstRspDataParErr", 27, 1 },
|
|
{ "NCSI2CIMIntfParErr", 26, 1 },
|
|
{ "SGE2CIMIntfParErr", 25, 1 },
|
|
{ "ULP2CIMIntfParErr", 24, 1 },
|
|
{ "TP2CIMIntfParErr", 23, 1 },
|
|
{ "OBQSGERx1ParErr", 22, 1 },
|
|
{ "OBQSGERx0ParErr", 21, 1 },
|
|
{ "TieQOutParErrInt", 20, 1 },
|
|
{ "TieQInParErrInt", 19, 1 },
|
|
{ "MBHostParErr", 18, 1 },
|
|
{ "IBQTP0ParErr", 16, 1 },
|
|
{ "IBQTP1ParErr", 15, 1 },
|
|
{ "IBQULPParErr", 14, 1 },
|
|
{ "IBQSGELOParErr", 13, 1 },
|
|
{ "IBQSGEHIParErr", 12, 1 },
|
|
{ "IBQNCSIParErr", 11, 1 },
|
|
{ "OBQULP0ParErr", 10, 1 },
|
|
{ "OBQULP1ParErr", 9, 1 },
|
|
{ "OBQULP2ParErr", 8, 1 },
|
|
{ "OBQULP3ParErr", 7, 1 },
|
|
{ "OBQSGEParErr", 6, 1 },
|
|
{ "OBQNCSIParErr", 5, 1 },
|
|
{ "MstPlInt", 4, 1 },
|
|
{ "Timer1Int", 3, 1 },
|
|
{ "Timer0Int", 2, 1 },
|
|
{ "PrefDropInt", 1, 1 },
|
|
{ "uPAccNonZero", 0, 1 },
|
|
{ "CIM_UP_ACC_INT_ENABLE", 0x7b40, 0 },
|
|
{ "EEPROMWRIntEn", 30, 1 },
|
|
{ "TimeOutMAIntEn", 29, 1 },
|
|
{ "TimeOutIntEn", 28, 1 },
|
|
{ "RspOvrLookupIntEn", 27, 1 },
|
|
{ "ReqOvrLookupIntEn", 26, 1 },
|
|
{ "BlkWrPlIntEn", 25, 1 },
|
|
{ "BlkRdPlIntEn", 24, 1 },
|
|
{ "SglWrPlIntEn", 23, 1 },
|
|
{ "SglRdPlIntEn", 22, 1 },
|
|
{ "BlkWrCtlIntEn", 21, 1 },
|
|
{ "BlkRdCtlIntEn", 20, 1 },
|
|
{ "SglWrCtlIntEn", 19, 1 },
|
|
{ "SglRdCtlIntEn", 18, 1 },
|
|
{ "BlkWrEEPROMIntEn", 17, 1 },
|
|
{ "BlkRdEEPROMIntEn", 16, 1 },
|
|
{ "SglWrEEPROMIntEn", 15, 1 },
|
|
{ "SglRdEEPROMIntEn", 14, 1 },
|
|
{ "BlkWrFlashIntEn", 13, 1 },
|
|
{ "BlkRdFlashIntEn", 12, 1 },
|
|
{ "SglWrFlashIntEn", 11, 1 },
|
|
{ "SglRdFlashIntEn", 10, 1 },
|
|
{ "BlkWrBootIntEn", 9, 1 },
|
|
{ "BlkRdBootIntEn", 8, 1 },
|
|
{ "SglWrBootIntEn", 7, 1 },
|
|
{ "SglRdBootIntEn", 6, 1 },
|
|
{ "IllWrBEIntEn", 5, 1 },
|
|
{ "IllRdBEIntEn", 4, 1 },
|
|
{ "IllRdIntEn", 3, 1 },
|
|
{ "IllWrIntEn", 2, 1 },
|
|
{ "IllTransIntEn", 1, 1 },
|
|
{ "RsvdSpaceIntEn", 0, 1 },
|
|
{ "CIM_UP_ACC_INT_CAUSE", 0x7b44, 0 },
|
|
{ "EEPROMWRInt", 30, 1 },
|
|
{ "TimeOutMAInt", 29, 1 },
|
|
{ "TimeOutInt", 28, 1 },
|
|
{ "RspOvrLookupInt", 27, 1 },
|
|
{ "ReqOvrLookupInt", 26, 1 },
|
|
{ "BlkWrPlInt", 25, 1 },
|
|
{ "BlkRdPlInt", 24, 1 },
|
|
{ "SglWrPlInt", 23, 1 },
|
|
{ "SglRdPlInt", 22, 1 },
|
|
{ "BlkWrCtlInt", 21, 1 },
|
|
{ "BlkRdCtlInt", 20, 1 },
|
|
{ "SglWrCtlInt", 19, 1 },
|
|
{ "SglRdCtlInt", 18, 1 },
|
|
{ "BlkWrEEPROMInt", 17, 1 },
|
|
{ "BlkRdEEPROMInt", 16, 1 },
|
|
{ "SglWrEEPROMInt", 15, 1 },
|
|
{ "SglRdEEPROMInt", 14, 1 },
|
|
{ "BlkWrFlashInt", 13, 1 },
|
|
{ "BlkRdFlashInt", 12, 1 },
|
|
{ "SglWrFlashInt", 11, 1 },
|
|
{ "SglRdFlashInt", 10, 1 },
|
|
{ "BlkWrBootInt", 9, 1 },
|
|
{ "BlkRdBootInt", 8, 1 },
|
|
{ "SglWrBootInt", 7, 1 },
|
|
{ "SglRdBootInt", 6, 1 },
|
|
{ "IllWrBEInt", 5, 1 },
|
|
{ "IllRdBEInt", 4, 1 },
|
|
{ "IllRdInt", 3, 1 },
|
|
{ "IllWrInt", 2, 1 },
|
|
{ "IllTransInt", 1, 1 },
|
|
{ "RsvdSpaceInt", 0, 1 },
|
|
{ "CIM_QUEUE_CONFIG_REF", 0x7b48, 0 },
|
|
{ "OBQSelect", 4, 1 },
|
|
{ "IBQSelect", 3, 1 },
|
|
{ "QueNumSelect", 0, 3 },
|
|
{ "CIM_QUEUE_CONFIG_CTRL", 0x7b4c, 0 },
|
|
{ "QueSize", 24, 6 },
|
|
{ "QueBase", 16, 6 },
|
|
{ "QueDbg8BEn", 9, 1 },
|
|
{ "QueFullThrsh", 0, 9 },
|
|
{ "CIM_HOST_ACC_CTRL", 0x7b50, 0 },
|
|
{ "HostBusy", 17, 1 },
|
|
{ "HostWrite", 16, 1 },
|
|
{ "HostAddr", 0, 16 },
|
|
{ "CIM_HOST_ACC_DATA", 0x7b54, 0 },
|
|
{ "CIM_CDEBUGDATA", 0x7b58, 0 },
|
|
{ "CDebugDataH", 16, 16 },
|
|
{ "CDebugDataL", 0, 16 },
|
|
{ "CIM_IBQ_DBG_CFG", 0x7b60, 0 },
|
|
{ "IbqDbgAddr", 16, 12 },
|
|
{ "IbqDbgWr", 2, 1 },
|
|
{ "IbqDbgBusy", 1, 1 },
|
|
{ "IbqDbgEn", 0, 1 },
|
|
{ "CIM_OBQ_DBG_CFG", 0x7b64, 0 },
|
|
{ "ObqDbgAddr", 16, 12 },
|
|
{ "ObqDbgWr", 2, 1 },
|
|
{ "ObqDbgBusy", 1, 1 },
|
|
{ "ObqDbgEn", 0, 1 },
|
|
{ "CIM_IBQ_DBG_DATA", 0x7b68, 0 },
|
|
{ "CIM_OBQ_DBG_DATA", 0x7b6c, 0 },
|
|
{ "CIM_DEBUGCFG", 0x7b70, 0 },
|
|
{ "POLADbgRdPtr", 23, 9 },
|
|
{ "PILADbgRdPtr", 14, 9 },
|
|
{ "LAMaskTrig", 13, 1 },
|
|
{ "LADbgEn", 12, 1 },
|
|
{ "LAFillOnce", 11, 1 },
|
|
{ "LAMaskStop", 10, 1 },
|
|
{ "DebugSelH", 5, 5 },
|
|
{ "DebugSelL", 0, 5 },
|
|
{ "CIM_DEBUGSTS", 0x7b74, 0 },
|
|
{ "LAReset", 31, 1 },
|
|
{ "POLADbgWrPtr", 16, 9 },
|
|
{ "PILADbgWrPtr", 0, 9 },
|
|
{ "CIM_PO_LA_DEBUGDATA", 0x7b78, 0 },
|
|
{ "CIM_PI_LA_DEBUGDATA", 0x7b7c, 0 },
|
|
{ "CIM_PO_LA_MADEBUGDATA", 0x7b80, 0 },
|
|
{ "CIM_PI_LA_MADEBUGDATA", 0x7b84, 0 },
|
|
{ "CIM_PO_LA_PIFSMDEBUGDATA", 0x7b8c, 0 },
|
|
{ "CIM_MEM_ZONE0_VA", 0x7b90, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE0_BA", 0x7b94, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE0_LEN", 0x7b98, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE1_VA", 0x7b9c, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE1_BA", 0x7ba0, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE1_LEN", 0x7ba4, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE2_VA", 0x7ba8, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE2_BA", 0x7bac, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE2_LEN", 0x7bb0, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE3_VA", 0x7bb4, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE3_BA", 0x7bb8, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE3_LEN", 0x7bbc, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE4_VA", 0x7bc0, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE4_BA", 0x7bc4, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE4_LEN", 0x7bc8, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE5_VA", 0x7bcc, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE5_BA", 0x7bd0, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE5_LEN", 0x7bd4, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE6_VA", 0x7bd8, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE6_BA", 0x7bdc, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE6_LEN", 0x7be0, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_MEM_ZONE7_VA", 0x7be4, 0 },
|
|
{ "MEM_ZONE_VA", 4, 28 },
|
|
{ "CIM_MEM_ZONE7_BA", 0x7be8, 0 },
|
|
{ "MEM_ZONE_BA", 6, 26 },
|
|
{ "PBT_enable", 5, 1 },
|
|
{ "ZONE_DST", 0, 2 },
|
|
{ "CIM_MEM_ZONE7_LEN", 0x7bec, 0 },
|
|
{ "MEM_ZONE_LEN", 4, 28 },
|
|
{ "CIM_GLB_TIMER_CTL", 0x7bf4, 0 },
|
|
{ "Timer1En", 4, 1 },
|
|
{ "Timer0En", 3, 1 },
|
|
{ "TimerEn", 1, 1 },
|
|
{ "CIM_GLB_TIMER", 0x7bf8, 0 },
|
|
{ "CIM_GLB_TIMER_TICK", 0x7bfc, 0 },
|
|
{ "CIM_TIMER0", 0x7c00, 0 },
|
|
{ "CIM_TIMER1", 0x7c04, 0 },
|
|
{ "CIM_DEBUG_ADDR_TIMEOUT", 0x7c08, 0 },
|
|
{ "DAddrTimeOut", 2, 30 },
|
|
{ "CIM_DEBUG_ADDR_ILLEGAL", 0x7c0c, 0 },
|
|
{ "DAddrIllegal", 2, 30 },
|
|
{ "CIM_DEBUG_PIF_CAUSE_MASK", 0x7c10, 0 },
|
|
{ "CIM_DEBUG_PIF_UPACC_CAUSE_MASK", 0x7c14, 0 },
|
|
{ "CIM_DEBUG_UP_CAUSE_MASK", 0x7c18, 0 },
|
|
{ "CIM_DEBUG_UP_UPACC_CAUSE_MASK", 0x7c1c, 0 },
|
|
{ "CIM_PERR_INJECT", 0x7c20, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "CIM_PERR_ENABLE", 0x7c24, 0 },
|
|
{ "CIM_EEPROM_BUSY_BIT", 0x7c28, 0 },
|
|
{ "CIM_MA_TIMER_EN", 0x7c2c, 0 },
|
|
{ "CIM_UP_PO_SINGLE_OUTSTANDING", 0x7c30, 0 },
|
|
{ "CIM_CIM_DEBUG_SPARE", 0x7c34, 0 },
|
|
{ "CIM_UP_OPERATION_FREQ", 0x7c38, 0 },
|
|
{ "CIM_CIM_IBQ_ERR_CODE", 0x7c3c, 0 },
|
|
{ "CIM_ULP_TX_PKT_ERR_CODE", 16, 8 },
|
|
{ "CIM_SGE1_PKT_ERR_CODE", 8, 8 },
|
|
{ "CIM_SGE0_PKT_ERR_CODE", 0, 8 },
|
|
{ "CIM_IBQ_DBG_WAIT_COUNTER", 0x7c40, 0 },
|
|
{ "CIM_PIO_UP_MST_CFG_SEL", 0x7c44, 0 },
|
|
{ "CIM_CGEN", 0x7c48, 0 },
|
|
{ "CIM_QUEUE_FEATURE_DISABLE", 0x7c4c, 0 },
|
|
{ "obq_throuttle_on_eop", 4, 1 },
|
|
{ "obq_read_ctl_perf_mode_disable", 3, 1 },
|
|
{ "obq_wait_for_eop_flush_disable", 2, 1 },
|
|
{ "ibq_rra_dsbl", 1, 1 },
|
|
{ "ibq_skid_fifo_eop_flsh_dsbl", 0, 1 },
|
|
{ "CIM_CGEN_GLOBAL", 0x7c50, 0 },
|
|
{ "CIM_DPSLP_EN", 0x7c54, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e240, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e244, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e248, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e24c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e250, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e254, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e258, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e25c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e260, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e264, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e268, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e26c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e270, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e274, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e278, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e27c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1e280, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1e284, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1e288, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1e28c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1e290, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e640, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e644, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e648, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e64c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e650, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e654, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e658, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e65c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e660, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e664, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e668, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e66c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e670, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e674, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e678, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1e67c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1e680, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1e684, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1e688, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1e68c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1e690, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea40, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea44, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea48, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea4c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea50, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea54, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea58, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea5c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea60, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea64, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea68, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea6c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea70, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea74, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea78, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ea7c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1ea80, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1ea84, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1ea88, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1ea8c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1ea90, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee40, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee44, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee48, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee4c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee50, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee54, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee58, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee5c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee60, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee64, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee68, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee6c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee70, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee74, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee78, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1ee7c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1ee80, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1ee84, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1ee88, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1ee8c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1ee90, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f240, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f244, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f248, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f24c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f250, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f254, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f258, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f25c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f260, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f264, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f268, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f26c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f270, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f274, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f278, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f27c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1f280, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1f284, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1f288, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1f28c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1f290, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f640, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f644, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f648, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f64c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f650, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f654, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f658, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f65c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f660, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f664, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f668, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f66c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f670, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f674, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f678, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1f67c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1f680, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1f684, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1f688, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1f68c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1f690, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa40, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa44, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa48, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa4c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa50, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa54, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa58, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa5c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa60, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa64, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa68, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa6c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa70, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa74, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa78, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fa7c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1fa80, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1fa84, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1fa88, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1fa8c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1fa90, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe40, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe44, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe48, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe4c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe50, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe54, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe58, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe5c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe60, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe64, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe68, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe6c, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe70, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe74, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe78, 0 },
|
|
{ "CIM_PF_MAILBOX_DATA", 0x1fe7c, 0 },
|
|
{ "CIM_PF_MAILBOX_CTRL", 0x1fe80, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ "CIM_PF_MAILBOX_ACC_STATUS", 0x1fe84, 0 },
|
|
{ "MBWrBusy", 31, 1 },
|
|
{ "CIM_PF_HOST_INT_ENABLE", 0x1fe88, 0 },
|
|
{ "MBMsgRdyIntEn", 19, 1 },
|
|
{ "CIM_PF_HOST_INT_CAUSE", 0x1fe8c, 0 },
|
|
{ "MBMsgRdyInt", 19, 1 },
|
|
{ "CIM_PF_MAILBOX_CTRL_SHADOW_COPY", 0x1fe90, 0 },
|
|
{ "MBGeneric", 4, 28 },
|
|
{ "MBMsgValid", 3, 1 },
|
|
{ "MBIntReq", 2, 1 },
|
|
{ "MBOwner", 0, 2 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_tp_regs[] = {
|
|
{ "TP_IN_CONFIG", 0x7d00, 0 },
|
|
{ "VLANExtEnPort3", 31, 1 },
|
|
{ "VLANExtEnPort2", 30, 1 },
|
|
{ "VLANExtEnPort1", 29, 1 },
|
|
{ "VLANExtEnPort0", 28, 1 },
|
|
{ "TcpOptParserDisCh3", 27, 1 },
|
|
{ "TcpOptParserDisCh2", 26, 1 },
|
|
{ "TcpOptParserDisCh1", 25, 1 },
|
|
{ "TcpOptParserDisCh0", 24, 1 },
|
|
{ "CrcPassPrt3", 23, 1 },
|
|
{ "CrcPassPrt2", 22, 1 },
|
|
{ "CrcPassPrt1", 21, 1 },
|
|
{ "CrcPassPrt0", 20, 1 },
|
|
{ "VepaMode", 19, 1 },
|
|
{ "FipUpEn", 18, 1 },
|
|
{ "FcoeUpEn", 17, 1 },
|
|
{ "FcoeEnable", 16, 1 },
|
|
{ "IPv6Enable", 15, 1 },
|
|
{ "NICMode", 14, 1 },
|
|
{ "VnTagDefaultVal", 13, 1 },
|
|
{ "ECheckUDPLen", 12, 1 },
|
|
{ "EReportUdpHdrLen", 11, 1 },
|
|
{ "FcoeFPMA", 10, 1 },
|
|
{ "VnTagEnable", 9, 1 },
|
|
{ "VnTagEthEnable", 8, 1 },
|
|
{ "CChecksumCheckIP", 7, 1 },
|
|
{ "CChecksumCheckUDP", 6, 1 },
|
|
{ "CChecksumCheckTCP", 5, 1 },
|
|
{ "CTag", 4, 1 },
|
|
{ "CDemux", 3, 1 },
|
|
{ "EthUpEn", 2, 1 },
|
|
{ "CEthernet", 1, 1 },
|
|
{ "CTunnel", 0, 1 },
|
|
{ "TP_OUT_CONFIG", 0x7d04, 0 },
|
|
{ "PortQfcEn", 28, 4 },
|
|
{ "EPktDistChn3", 23, 1 },
|
|
{ "EPktDistChn2", 22, 1 },
|
|
{ "EPktDistChn1", 21, 1 },
|
|
{ "EPktDistChn0", 20, 1 },
|
|
{ "TtlMode", 19, 1 },
|
|
{ "EQfcDmac", 18, 1 },
|
|
{ "ELpbkIncMpsStat", 17, 1 },
|
|
{ "IPIDSplitMode", 16, 1 },
|
|
{ "EChecksumInsertTCP", 11, 1 },
|
|
{ "EChecksumInsertIP", 10, 1 },
|
|
{ "EVnTagEn", 9, 1 },
|
|
{ "ECPL", 8, 1 },
|
|
{ "EPriority", 7, 1 },
|
|
{ "EEthernet", 6, 1 },
|
|
{ "CChecksumInsertTCP", 5, 1 },
|
|
{ "CChecksumInsertIP", 4, 1 },
|
|
{ "CCPL", 2, 1 },
|
|
{ "CEthernet", 0, 1 },
|
|
{ "TP_GLOBAL_CONFIG", 0x7d08, 0 },
|
|
{ "SYNCookieParams", 26, 6 },
|
|
{ "RXFlowControlDisable", 25, 1 },
|
|
{ "TXPacingEnable", 24, 1 },
|
|
{ "AttackFilterEnable", 23, 1 },
|
|
{ "SYNCookieNoOptions", 22, 1 },
|
|
{ "ProtectedMode", 21, 1 },
|
|
{ "PingDrop", 20, 1 },
|
|
{ "FragmentDrop", 19, 1 },
|
|
{ "FiveTupleLookup", 17, 2 },
|
|
{ "OfdMpsStats", 16, 1 },
|
|
{ "DontFragment", 15, 1 },
|
|
{ "IPIdentSplit", 14, 1 },
|
|
{ "RssSynSteerEnable", 12, 1 },
|
|
{ "IssFromCplEnable", 11, 1 },
|
|
{ "RssLoopbackEnable", 10, 1 },
|
|
{ "TCAMServerUse", 8, 2 },
|
|
{ "IPTTL", 0, 8 },
|
|
{ "TP_DB_CONFIG", 0x7d0c, 0 },
|
|
{ "DBMaxOpCnt", 24, 8 },
|
|
{ "CxMaxOpCntDisable", 23, 1 },
|
|
{ "CxMaxOpCnt", 16, 7 },
|
|
{ "TxMaxOpCntDisable", 15, 1 },
|
|
{ "TxMaxOpCnt", 8, 7 },
|
|
{ "RxMaxOpCntDisable", 7, 1 },
|
|
{ "RxMaxOpCnt", 0, 7 },
|
|
{ "TP_CMM_TCB_BASE", 0x7d10, 0 },
|
|
{ "TP_CMM_MM_BASE", 0x7d14, 0 },
|
|
{ "TP_CMM_TIMER_BASE", 0x7d18, 0 },
|
|
{ "TP_CMM_MM_FLST_SIZE", 0x7d1c, 0 },
|
|
{ "RxPoolSize", 16, 16 },
|
|
{ "TxPoolSize", 0, 16 },
|
|
{ "TP_PMM_TX_BASE", 0x7d20, 0 },
|
|
{ "TP_PMM_DEFRAG_BASE", 0x7d24, 0 },
|
|
{ "TP_PMM_RX_BASE", 0x7d28, 0 },
|
|
{ "TP_PMM_RX_PAGE_SIZE", 0x7d2c, 0 },
|
|
{ "TP_PMM_RX_MAX_PAGE", 0x7d30, 0 },
|
|
{ "PMRxNumChn", 31, 1 },
|
|
{ "PMRxMaxPage", 0, 21 },
|
|
{ "TP_PMM_TX_PAGE_SIZE", 0x7d34, 0 },
|
|
{ "TP_PMM_TX_MAX_PAGE", 0x7d38, 0 },
|
|
{ "PMTxNumChn", 30, 2 },
|
|
{ "PMTxMaxPage", 0, 21 },
|
|
{ "TP_TCP_OPTIONS", 0x7d40, 0 },
|
|
{ "MTUDefault", 16, 16 },
|
|
{ "MTUEnable", 10, 1 },
|
|
{ "SACKTx", 9, 1 },
|
|
{ "SACKRx", 8, 1 },
|
|
{ "SACKMode", 4, 2 },
|
|
{ "WindowScaleMode", 2, 2 },
|
|
{ "TimestampsMode", 0, 2 },
|
|
{ "TP_DACK_CONFIG", 0x7d44, 0 },
|
|
{ "AutoState3", 30, 2 },
|
|
{ "AutoState2", 28, 2 },
|
|
{ "AutoState1", 26, 2 },
|
|
{ "ByteThreshold", 8, 18 },
|
|
{ "MSSThreshold", 4, 3 },
|
|
{ "AutoCareful", 2, 1 },
|
|
{ "AutoEnable", 1, 1 },
|
|
{ "Mode", 0, 1 },
|
|
{ "TP_PC_CONFIG", 0x7d48, 0 },
|
|
{ "CMCacheDisable", 31, 1 },
|
|
{ "EnableOcspiFull", 30, 1 },
|
|
{ "EnableFLMErrorDDP", 29, 1 },
|
|
{ "LockTid", 28, 1 },
|
|
{ "DisableInvPend", 27, 1 },
|
|
{ "EnableFilterCount", 26, 1 },
|
|
{ "RddpCongEn", 25, 1 },
|
|
{ "EnableOnFlyPDU", 24, 1 },
|
|
{ "EnableMinRcvWnd", 23, 1 },
|
|
{ "EnableMaxRcvWnd", 22, 1 },
|
|
{ "TxDataAckRateEnable", 21, 1 },
|
|
{ "TxDeferEnable", 20, 1 },
|
|
{ "RxCongestionMode", 19, 1 },
|
|
{ "HearbeatOnceDACK", 18, 1 },
|
|
{ "HearbeatOnceHeap", 17, 1 },
|
|
{ "HearbeatDACK", 16, 1 },
|
|
{ "TxCongestionMode", 15, 1 },
|
|
{ "AcceptLatestRcvAdv", 14, 1 },
|
|
{ "DisableSYNData", 13, 1 },
|
|
{ "DisableWindowPSH", 12, 1 },
|
|
{ "DisableFINOldData", 11, 1 },
|
|
{ "EnableFLMError", 10, 1 },
|
|
{ "EnableOptMtu", 9, 1 },
|
|
{ "FilterPeerFIN", 8, 1 },
|
|
{ "EnableFeedbackSend", 7, 1 },
|
|
{ "EnableRDMAError", 6, 1 },
|
|
{ "EnableFilterNat", 5, 1 },
|
|
{ "DisableHeldFIN", 4, 1 },
|
|
{ "EnableOfdoVLAN", 3, 1 },
|
|
{ "DisableTimeWait", 2, 1 },
|
|
{ "EnableVlanCheck", 1, 1 },
|
|
{ "TxDataAckPageEnable", 0, 1 },
|
|
{ "TP_PC_CONFIG2", 0x7d4c, 0 },
|
|
{ "EnableMtuVfMode", 31, 1 },
|
|
{ "EnableMibVfMode", 30, 1 },
|
|
{ "DisableLbkCheck", 29, 1 },
|
|
{ "EnableUrgDdpOff", 28, 1 },
|
|
{ "EnableFilterLpbk", 27, 1 },
|
|
{ "DisableTblMmgr", 26, 1 },
|
|
{ "CngRecSndNxt", 25, 1 },
|
|
{ "EnableLbkChn", 24, 1 },
|
|
{ "EnableLroEcn", 23, 1 },
|
|
{ "EnablePcmdCheck", 22, 1 },
|
|
{ "EnableELbkAFull", 21, 1 },
|
|
{ "EnableCLbkAFull", 20, 1 },
|
|
{ "EnableOespiFull", 19, 1 },
|
|
{ "DisableHitCheck", 18, 1 },
|
|
{ "EnableRssErrCheck", 17, 1 },
|
|
{ "DisableNewPshFlag", 16, 1 },
|
|
{ "EnableRddpRcvAdvClr", 15, 1 },
|
|
{ "EnableFinDdpOff", 14, 1 },
|
|
{ "EnableArpMiss", 13, 1 },
|
|
{ "EnableRstPaws", 12, 1 },
|
|
{ "EnableIPv6RSS", 11, 1 },
|
|
{ "EnableNonOfdHybRss", 10, 1 },
|
|
{ "EnableUDP4TupRss", 9, 1 },
|
|
{ "EnableRxPktTmstpRss", 8, 1 },
|
|
{ "EnableEPCMDAFull", 7, 1 },
|
|
{ "EnableCPCMDAFull", 6, 1 },
|
|
{ "EnableEHdrAFull", 5, 1 },
|
|
{ "EnableCHdrAFull", 4, 1 },
|
|
{ "EnableEMacAFull", 3, 1 },
|
|
{ "EnableNonOfdTidRss", 2, 1 },
|
|
{ "EnableNonOfdTcbRss", 1, 1 },
|
|
{ "EnableTnlOfdClosed", 0, 1 },
|
|
{ "TP_TCP_BACKOFF_REG0", 0x7d50, 0 },
|
|
{ "TimerBackoffIndex3", 24, 8 },
|
|
{ "TimerBackoffIndex2", 16, 8 },
|
|
{ "TimerBackoffIndex1", 8, 8 },
|
|
{ "TimerBackoffIndex0", 0, 8 },
|
|
{ "TP_TCP_BACKOFF_REG1", 0x7d54, 0 },
|
|
{ "TimerBackoffIndex7", 24, 8 },
|
|
{ "TimerBackoffIndex6", 16, 8 },
|
|
{ "TimerBackoffIndex5", 8, 8 },
|
|
{ "TimerBackoffIndex4", 0, 8 },
|
|
{ "TP_TCP_BACKOFF_REG2", 0x7d58, 0 },
|
|
{ "TimerBackoffIndex11", 24, 8 },
|
|
{ "TimerBackoffIndex10", 16, 8 },
|
|
{ "TimerBackoffIndex9", 8, 8 },
|
|
{ "TimerBackoffIndex8", 0, 8 },
|
|
{ "TP_TCP_BACKOFF_REG3", 0x7d5c, 0 },
|
|
{ "TimerBackoffIndex15", 24, 8 },
|
|
{ "TimerBackoffIndex14", 16, 8 },
|
|
{ "TimerBackoffIndex13", 8, 8 },
|
|
{ "TimerBackoffIndex12", 0, 8 },
|
|
{ "TP_PARA_REG0", 0x7d60, 0 },
|
|
{ "LimTxThresh", 28, 4 },
|
|
{ "InitCwndIdle", 27, 1 },
|
|
{ "InitCwnd", 24, 3 },
|
|
{ "DupAckThresh", 20, 4 },
|
|
{ "ChnErrEnable", 14, 1 },
|
|
{ "SetTimeEnable", 13, 1 },
|
|
{ "CplErrEnable", 12, 1 },
|
|
{ "FastTnlCnt", 11, 1 },
|
|
{ "FastTblCnt", 10, 1 },
|
|
{ "TpTcamKey", 9, 1 },
|
|
{ "SwsMode", 8, 1 },
|
|
{ "TsmpMode", 6, 2 },
|
|
{ "ByteCountLimit", 4, 2 },
|
|
{ "SwsShove", 3, 1 },
|
|
{ "TblTimer", 2, 1 },
|
|
{ "RxtPace", 1, 1 },
|
|
{ "SwsTimer", 0, 1 },
|
|
{ "TP_PARA_REG1", 0x7d64, 0 },
|
|
{ "InitRwnd", 16, 16 },
|
|
{ "InitialSSThresh", 0, 16 },
|
|
{ "TP_PARA_REG2", 0x7d68, 0 },
|
|
{ "MaxRxData", 16, 16 },
|
|
{ "RxCoalesceSize", 0, 16 },
|
|
{ "TP_PARA_REG3", 0x7d6c, 0 },
|
|
{ "EnableTnlCngLpbk", 31, 1 },
|
|
{ "EnableTnlCngFifo", 30, 1 },
|
|
{ "EnableTnlCngHdr", 29, 1 },
|
|
{ "EnableTnlCngSge", 28, 1 },
|
|
{ "RxMacCheck", 27, 1 },
|
|
{ "RxSynFilter", 26, 1 },
|
|
{ "CngCtrlECN", 25, 1 },
|
|
{ "RxDdpOffInit", 24, 1 },
|
|
{ "TunnelCngDrop3", 23, 1 },
|
|
{ "TunnelCngDrop2", 22, 1 },
|
|
{ "TunnelCngDrop1", 21, 1 },
|
|
{ "TunnelCngDrop0", 20, 1 },
|
|
{ "TxDataAckIdx", 16, 4 },
|
|
{ "RxFragEnable", 12, 3 },
|
|
{ "TxPaceFixedStrict", 11, 1 },
|
|
{ "TxPaceAutoStrict", 10, 1 },
|
|
{ "TxPaceFixed", 9, 1 },
|
|
{ "TxPaceAuto", 8, 1 },
|
|
{ "RxChnTunnel", 7, 1 },
|
|
{ "RxUrgTunnel", 6, 1 },
|
|
{ "RxUrgMode", 5, 1 },
|
|
{ "TxUrgMode", 4, 1 },
|
|
{ "CngCtrlMode", 2, 2 },
|
|
{ "RxCoalesceEnable", 1, 1 },
|
|
{ "RxCoalescePshEn", 0, 1 },
|
|
{ "TP_PARA_REG4", 0x7d70, 0 },
|
|
{ "IdleCwndHighSpeed", 28, 1 },
|
|
{ "RxmtCwndHighSpeed", 27, 1 },
|
|
{ "OverdriveHighSpeed", 25, 2 },
|
|
{ "ByteCountHighSpeed", 24, 1 },
|
|
{ "IdleCwndNewReno", 20, 1 },
|
|
{ "RxmtCwndNewReno", 19, 1 },
|
|
{ "OverdriveNewReno", 17, 2 },
|
|
{ "ByteCountNewReno", 16, 1 },
|
|
{ "IdleCwndTahoe", 12, 1 },
|
|
{ "RxmtCwndTahoe", 11, 1 },
|
|
{ "OverdriveTahoe", 9, 2 },
|
|
{ "ByteCountTahoe", 8, 1 },
|
|
{ "IdleCwndReno", 4, 1 },
|
|
{ "RxmtCwndReno", 3, 1 },
|
|
{ "OverdriveReno", 1, 2 },
|
|
{ "ByteCountReno", 0, 1 },
|
|
{ "TP_PARA_REG5", 0x7d74, 0 },
|
|
{ "IndicateSize", 16, 16 },
|
|
{ "MaxProxySize", 12, 4 },
|
|
{ "EnableReadPdu", 11, 1 },
|
|
{ "EnableReadAhead", 10, 1 },
|
|
{ "EmptyRqEnable", 9, 1 },
|
|
{ "SchdEnable", 8, 1 },
|
|
{ "EnableXoffPdu", 7, 1 },
|
|
{ "EnableNewFar", 6, 1 },
|
|
{ "EnableFragCheck", 5, 1 },
|
|
{ "RearmDdpOffset", 4, 1 },
|
|
{ "ResetDdpOffset", 3, 1 },
|
|
{ "OnFlyDDPEnable", 2, 1 },
|
|
{ "DackTimerSpin", 1, 1 },
|
|
{ "PushTimerEnable", 0, 1 },
|
|
{ "TP_PARA_REG6", 0x7d78, 0 },
|
|
{ "TxPDUSizeAdj", 24, 8 },
|
|
{ "DisablePDUAck", 20, 1 },
|
|
{ "EnableCSav", 19, 1 },
|
|
{ "EnableDeferPDU", 18, 1 },
|
|
{ "EnableFlush", 17, 1 },
|
|
{ "EnableBytePersist", 16, 1 },
|
|
{ "DisableTmoCng", 15, 1 },
|
|
{ "EnableReadAhead", 14, 1 },
|
|
{ "AllowExeption", 13, 1 },
|
|
{ "EnableDeferACK", 12, 1 },
|
|
{ "EnableESnd", 11, 1 },
|
|
{ "EnableCSnd", 10, 1 },
|
|
{ "EnablePDUE", 9, 1 },
|
|
{ "EnablePDUC", 8, 1 },
|
|
{ "EnableBUFI", 7, 1 },
|
|
{ "EnableBUFE", 6, 1 },
|
|
{ "EnableDefer", 5, 1 },
|
|
{ "EnableClearRxmtOos", 4, 1 },
|
|
{ "DisablePDUCng", 3, 1 },
|
|
{ "DisablePDUTimeout", 2, 1 },
|
|
{ "DisablePDURxmt", 1, 1 },
|
|
{ "DisablePDUxmt", 0, 1 },
|
|
{ "TP_PARA_REG7", 0x7d7c, 0 },
|
|
{ "PMMaxXferLen1", 16, 16 },
|
|
{ "PMMaxXferLen0", 0, 16 },
|
|
{ "TP_ENG_CONFIG", 0x7d80, 0 },
|
|
{ "TableLatencyDone", 28, 4 },
|
|
{ "TableLatencyStart", 24, 4 },
|
|
{ "EngineLatencyDelta", 16, 4 },
|
|
{ "EngineLatencyMmgr", 12, 4 },
|
|
{ "EngineLatencyWireIp6", 8, 4 },
|
|
{ "EngineLatencyWire", 4, 4 },
|
|
{ "EngineLatencyBase", 0, 4 },
|
|
{ "TP_ERR_CONFIG", 0x7d8c, 0 },
|
|
{ "TnlErrorFPMA", 31, 1 },
|
|
{ "TnlErrorPing", 30, 1 },
|
|
{ "TnlErrorCsum", 29, 1 },
|
|
{ "TnlErrorCsumIP", 28, 1 },
|
|
{ "TnlErrorTcpOpt", 25, 1 },
|
|
{ "TnlErrorPktLen", 24, 1 },
|
|
{ "TnlErrorTcpHdrLen", 23, 1 },
|
|
{ "TnlErrorIpHdrLen", 22, 1 },
|
|
{ "TnlErrorEthHdrLen", 21, 1 },
|
|
{ "TnlErrorAttack", 20, 1 },
|
|
{ "TnlErrorFrag", 19, 1 },
|
|
{ "TnlErrorIpVer", 18, 1 },
|
|
{ "TnlErrorMac", 17, 1 },
|
|
{ "TnlErrorAny", 16, 1 },
|
|
{ "DropErrorFPMA", 15, 1 },
|
|
{ "DropErrorPing", 14, 1 },
|
|
{ "DropErrorCsum", 13, 1 },
|
|
{ "DropErrorCsumIP", 12, 1 },
|
|
{ "DropErrorTcpOpt", 9, 1 },
|
|
{ "DropErrorPktLen", 8, 1 },
|
|
{ "DropErrorTcpHdrLen", 7, 1 },
|
|
{ "DropErrorIpHdrLen", 6, 1 },
|
|
{ "DropErrorEthHdrLen", 5, 1 },
|
|
{ "DropErrorAttack", 4, 1 },
|
|
{ "DropErrorFrag", 3, 1 },
|
|
{ "DropErrorIpVer", 2, 1 },
|
|
{ "DropErrorMac", 1, 1 },
|
|
{ "DropErrorAny", 0, 1 },
|
|
{ "TP_TIMER_RESOLUTION", 0x7d90, 0 },
|
|
{ "TimerResolution", 16, 8 },
|
|
{ "TimestampResolution", 8, 8 },
|
|
{ "DelayedACKResolution", 0, 8 },
|
|
{ "TP_MSL", 0x7d94, 0 },
|
|
{ "TP_RXT_MIN", 0x7d98, 0 },
|
|
{ "TP_RXT_MAX", 0x7d9c, 0 },
|
|
{ "TP_PERS_MIN", 0x7da0, 0 },
|
|
{ "TP_PERS_MAX", 0x7da4, 0 },
|
|
{ "TP_KEEP_IDLE", 0x7da8, 0 },
|
|
{ "TP_KEEP_INTVL", 0x7dac, 0 },
|
|
{ "TP_INIT_SRTT", 0x7db0, 0 },
|
|
{ "MaxRtt", 16, 16 },
|
|
{ "InitSrtt", 0, 16 },
|
|
{ "TP_DACK_TIMER", 0x7db4, 0 },
|
|
{ "TP_FINWAIT2_TIMER", 0x7db8, 0 },
|
|
{ "TP_FAST_FINWAIT2_TIMER", 0x7dbc, 0 },
|
|
{ "TP_SHIFT_CNT", 0x7dc0, 0 },
|
|
{ "SynShiftMax", 24, 8 },
|
|
{ "RxtShiftMaxR1", 20, 4 },
|
|
{ "RxtShiftMaxR2", 16, 4 },
|
|
{ "PerShiftBackoffMax", 12, 4 },
|
|
{ "PerShiftMax", 8, 4 },
|
|
{ "KeepaliveMaxR1", 4, 4 },
|
|
{ "KeepaliveMaxR2", 0, 4 },
|
|
{ "TP_TM_CONFIG", 0x7dc4, 0 },
|
|
{ "TP_TIME_LO", 0x7dc8, 0 },
|
|
{ "TP_TIME_HI", 0x7dcc, 0 },
|
|
{ "TP_PORT_MTU_0", 0x7dd0, 0 },
|
|
{ "Port1MTUValue", 16, 16 },
|
|
{ "Port0MTUValue", 0, 16 },
|
|
{ "TP_PORT_MTU_1", 0x7dd4, 0 },
|
|
{ "Port3MTUValue", 16, 16 },
|
|
{ "Port2MTUValue", 0, 16 },
|
|
{ "TP_PACE_TABLE", 0x7dd8, 0 },
|
|
{ "TP_CCTRL_TABLE", 0x7ddc, 0 },
|
|
{ "RowIndex", 16, 16 },
|
|
{ "RowValue", 0, 16 },
|
|
{ "TP_MTU_TABLE", 0x7de4, 0 },
|
|
{ "MTUIndex", 24, 8 },
|
|
{ "MTUWidth", 16, 4 },
|
|
{ "MTUValue", 0, 14 },
|
|
{ "TP_ULP_TABLE", 0x7de8, 0 },
|
|
{ "ULPType7Field", 28, 4 },
|
|
{ "ULPType6Field", 24, 4 },
|
|
{ "ULPType5Field", 20, 4 },
|
|
{ "ULPType4Field", 16, 4 },
|
|
{ "ULPType3Field", 12, 4 },
|
|
{ "ULPType2Field", 8, 4 },
|
|
{ "ULPType1Field", 4, 4 },
|
|
{ "ULPType0Field", 0, 4 },
|
|
{ "TP_RSS_LKP_TABLE", 0x7dec, 0 },
|
|
{ "LkpTblRowVld", 31, 1 },
|
|
{ "LkpTblRowIdx", 20, 10 },
|
|
{ "LkpTblQueue1", 10, 10 },
|
|
{ "LkpTblQueue0", 0, 10 },
|
|
{ "TP_RSS_CONFIG", 0x7df0, 0 },
|
|
{ "TNL4tupEnIpv6", 31, 1 },
|
|
{ "TNL2tupEnIpv6", 30, 1 },
|
|
{ "TNL4tupEnIpv4", 29, 1 },
|
|
{ "TNL2tupEnIpv4", 28, 1 },
|
|
{ "TNLTcpSel", 27, 1 },
|
|
{ "TNLIp6Sel", 26, 1 },
|
|
{ "TNLVrtSel", 25, 1 },
|
|
{ "TNLMapEn", 24, 1 },
|
|
{ "TNLFcoeMode", 23, 1 },
|
|
{ "TNLFcoeEn", 21, 1 },
|
|
{ "HashXor", 20, 1 },
|
|
{ "OFDHashSave", 19, 1 },
|
|
{ "OFDVrtSel", 18, 1 },
|
|
{ "OFDMapEn", 17, 1 },
|
|
{ "OFDLkpEn", 16, 1 },
|
|
{ "SYN4tupEnIpv6", 15, 1 },
|
|
{ "SYN2tupEnIpv6", 14, 1 },
|
|
{ "SYN4tupEnIpv4", 13, 1 },
|
|
{ "SYN2tupEnIpv4", 12, 1 },
|
|
{ "SYNIp6Sel", 11, 1 },
|
|
{ "SYNVrtSel", 10, 1 },
|
|
{ "SYNMapEn", 9, 1 },
|
|
{ "SYNLkpEn", 8, 1 },
|
|
{ "ChannelEnable", 7, 1 },
|
|
{ "PortEnable", 6, 1 },
|
|
{ "TNLAllLookup", 5, 1 },
|
|
{ "VirtEnable", 4, 1 },
|
|
{ "CongestionEnable", 3, 1 },
|
|
{ "HashToeplitz", 2, 1 },
|
|
{ "UdpEnable", 1, 1 },
|
|
{ "Disable", 0, 1 },
|
|
{ "TP_RSS_CONFIG_TNL", 0x7df4, 0 },
|
|
{ "MaskSize", 28, 4 },
|
|
{ "MaskFilter", 16, 11 },
|
|
{ "UseWireCh", 0, 1 },
|
|
{ "TP_RSS_CONFIG_OFD", 0x7df8, 0 },
|
|
{ "MaskSize", 28, 4 },
|
|
{ "RRCPLMapEn", 20, 1 },
|
|
{ "RRCPLQueWidth", 16, 4 },
|
|
{ "FrmwrQueMask", 12, 4 },
|
|
{ "TP_RSS_CONFIG_SYN", 0x7dfc, 0 },
|
|
{ "MaskSize", 28, 4 },
|
|
{ "UseWireCh", 0, 1 },
|
|
{ "TP_RSS_CONFIG_VRT", 0x7e00, 0 },
|
|
{ "VfRdRg", 25, 1 },
|
|
{ "VfRdEn", 24, 1 },
|
|
{ "VfPerrEn", 23, 1 },
|
|
{ "KeyPerrEn", 22, 1 },
|
|
{ "VfVlanEn", 21, 1 },
|
|
{ "VfFwEn", 20, 1 },
|
|
{ "HashDelay", 16, 4 },
|
|
{ "VfWrAddr", 8, 7 },
|
|
{ "KeyMode", 6, 2 },
|
|
{ "VfWrEn", 5, 1 },
|
|
{ "KeyWrEn", 4, 1 },
|
|
{ "KeyWrAddr", 0, 4 },
|
|
{ "TP_RSS_CONFIG_CNG", 0x7e04, 0 },
|
|
{ "ChnCount3", 31, 1 },
|
|
{ "ChnCount2", 30, 1 },
|
|
{ "ChnCount1", 29, 1 },
|
|
{ "ChnCount0", 28, 1 },
|
|
{ "ChnUndFlow3", 27, 1 },
|
|
{ "ChnUndFlow2", 26, 1 },
|
|
{ "ChnUndFlow1", 25, 1 },
|
|
{ "ChnUndFlow0", 24, 1 },
|
|
{ "ChnOvrFlow3", 23, 1 },
|
|
{ "ChnOvrFlow2", 22, 1 },
|
|
{ "ChnOvrFlow1", 21, 1 },
|
|
{ "ChnOvrFlow0", 20, 1 },
|
|
{ "RstChn3", 19, 1 },
|
|
{ "RstChn2", 18, 1 },
|
|
{ "RstChn1", 17, 1 },
|
|
{ "RstChn0", 16, 1 },
|
|
{ "UpdVld", 15, 1 },
|
|
{ "Xoff", 14, 1 },
|
|
{ "UpdChn3", 13, 1 },
|
|
{ "UpdChn2", 12, 1 },
|
|
{ "UpdChn1", 11, 1 },
|
|
{ "UpdChn0", 10, 1 },
|
|
{ "Queue", 0, 10 },
|
|
{ "TP_LA_TABLE_0", 0x7e10, 0 },
|
|
{ "VirtPort1Table", 16, 16 },
|
|
{ "VirtPort0Table", 0, 16 },
|
|
{ "TP_LA_TABLE_1", 0x7e14, 0 },
|
|
{ "VirtPort3Table", 16, 16 },
|
|
{ "VirtPort2Table", 0, 16 },
|
|
{ "TP_TM_PIO_ADDR", 0x7e18, 0 },
|
|
{ "TP_TM_PIO_DATA", 0x7e1c, 0 },
|
|
{ "TP_MOD_CONFIG", 0x7e24, 0 },
|
|
{ "RxChannelWeight1", 24, 8 },
|
|
{ "RXChannelWeight0", 16, 8 },
|
|
{ "TimerMode", 8, 8 },
|
|
{ "TxChannelXoffEn", 0, 4 },
|
|
{ "TP_TX_MOD_QUEUE_REQ_MAP", 0x7e28, 0 },
|
|
{ "RX_MOD_WEIGHT", 24, 8 },
|
|
{ "TX_MOD_WEIGHT", 16, 8 },
|
|
{ "TX_MOD_QUEUE_REQ_MAP", 0, 16 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT1", 0x7e2c, 0 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT7", 24, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT6", 16, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT5", 8, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT4", 0, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT0", 0x7e30, 0 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT3", 24, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT2", 16, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT1", 8, 8 },
|
|
{ "TP_TX_MOD_QUEUE_WEIGHT0", 0, 8 },
|
|
{ "TP_TX_MOD_CHANNEL_WEIGHT", 0x7e34, 0 },
|
|
{ "CH3", 24, 8 },
|
|
{ "CH2", 16, 8 },
|
|
{ "CH1", 8, 8 },
|
|
{ "CH0", 0, 8 },
|
|
{ "TP_MOD_RATE_LIMIT", 0x7e38, 0 },
|
|
{ "RX_MOD_RATE_LIMIT_INC", 24, 8 },
|
|
{ "RX_MOD_RATE_LIMIT_TICK", 16, 8 },
|
|
{ "TX_MOD_RATE_LIMIT_INC", 8, 8 },
|
|
{ "TX_MOD_RATE_LIMIT_TICK", 0, 8 },
|
|
{ "TP_PIO_ADDR", 0x7e40, 0 },
|
|
{ "TP_PIO_DATA", 0x7e44, 0 },
|
|
{ "TP_RESET", 0x7e4c, 0 },
|
|
{ "FlstInitEnable", 1, 1 },
|
|
{ "TPReset", 0, 1 },
|
|
{ "TP_MIB_INDEX", 0x7e50, 0 },
|
|
{ "TP_MIB_DATA", 0x7e54, 0 },
|
|
{ "TP_SYNC_TIME_HI", 0x7e58, 0 },
|
|
{ "TP_SYNC_TIME_LO", 0x7e5c, 0 },
|
|
{ "TP_CMM_MM_RX_FLST_BASE", 0x7e60, 0 },
|
|
{ "TP_CMM_MM_TX_FLST_BASE", 0x7e64, 0 },
|
|
{ "TP_CMM_MM_PS_FLST_BASE", 0x7e68, 0 },
|
|
{ "TP_CMM_MM_MAX_PSTRUCT", 0x7e6c, 0 },
|
|
{ "TP_INT_ENABLE", 0x7e70, 0 },
|
|
{ "FlmTxFlstEmpty", 30, 1 },
|
|
{ "RssLkpPerr", 29, 1 },
|
|
{ "FlmPerrSet", 28, 1 },
|
|
{ "ProtocolSramPerr", 27, 1 },
|
|
{ "ArpLutPerr", 26, 1 },
|
|
{ "CmRcfOpPerr", 25, 1 },
|
|
{ "CmCachePerr", 24, 1 },
|
|
{ "CmRcfDataPerr", 23, 1 },
|
|
{ "DbL2tLutPerr", 22, 1 },
|
|
{ "DbTxTidPerr", 21, 1 },
|
|
{ "DbExtPerr", 20, 1 },
|
|
{ "DbOpPerr", 19, 1 },
|
|
{ "TmCachePerr", 18, 1 },
|
|
{ "ETpOutCplFifoPerr", 17, 1 },
|
|
{ "ETpOutTcpFifoPerr", 16, 1 },
|
|
{ "ETpOutIpFifoPerr", 15, 1 },
|
|
{ "ETpOutEthFifoPerr", 14, 1 },
|
|
{ "ETpInCplFifoPerr", 13, 1 },
|
|
{ "ETpInTcpOptFifoPerr", 12, 1 },
|
|
{ "ETpInTcpFifoPerr", 11, 1 },
|
|
{ "ETpInIpFifoPerr", 10, 1 },
|
|
{ "ETpInEthFifoPerr", 9, 1 },
|
|
{ "CTpOutCplFifoPerr", 8, 1 },
|
|
{ "CTpOutPldFifoPerr", 7, 1 },
|
|
{ "CTpOutIpFifoPerr", 6, 1 },
|
|
{ "CTpOutEthFifoPerr", 5, 1 },
|
|
{ "CTpInCplFifoPerr", 4, 1 },
|
|
{ "CTpInTcpOpFifoPerr", 3, 1 },
|
|
{ "PduFbkFifoPerr", 2, 1 },
|
|
{ "CmOpExtFifoPerr", 1, 1 },
|
|
{ "DelInvFifoPerr", 0, 1 },
|
|
{ "TP_INT_CAUSE", 0x7e74, 0 },
|
|
{ "FlmTxFlstEmpty", 30, 1 },
|
|
{ "RssLkpPerr", 29, 1 },
|
|
{ "FlmPerrSet", 28, 1 },
|
|
{ "ProtocolSramPerr", 27, 1 },
|
|
{ "ArpLutPerr", 26, 1 },
|
|
{ "CmRcfOpPerr", 25, 1 },
|
|
{ "CmCachePerr", 24, 1 },
|
|
{ "CmRcfDataPerr", 23, 1 },
|
|
{ "DbL2tLutPerr", 22, 1 },
|
|
{ "DbTxTidPerr", 21, 1 },
|
|
{ "DbExtPerr", 20, 1 },
|
|
{ "DbOpPerr", 19, 1 },
|
|
{ "TmCachePerr", 18, 1 },
|
|
{ "ETpOutCplFifoPerr", 17, 1 },
|
|
{ "ETpOutTcpFifoPerr", 16, 1 },
|
|
{ "ETpOutIpFifoPerr", 15, 1 },
|
|
{ "ETpOutEthFifoPerr", 14, 1 },
|
|
{ "ETpInCplFifoPerr", 13, 1 },
|
|
{ "ETpInTcpOptFifoPerr", 12, 1 },
|
|
{ "ETpInTcpFifoPerr", 11, 1 },
|
|
{ "ETpInIpFifoPerr", 10, 1 },
|
|
{ "ETpInEthFifoPerr", 9, 1 },
|
|
{ "CTpOutCplFifoPerr", 8, 1 },
|
|
{ "CTpOutPldFifoPerr", 7, 1 },
|
|
{ "CTpOutIpFifoPerr", 6, 1 },
|
|
{ "CTpOutEthFifoPerr", 5, 1 },
|
|
{ "CTpInCplFifoPerr", 4, 1 },
|
|
{ "CTpInTcpOpFifoPerr", 3, 1 },
|
|
{ "PduFbkFifoPerr", 2, 1 },
|
|
{ "CmOpExtFifoPerr", 1, 1 },
|
|
{ "DelInvFifoPerr", 0, 1 },
|
|
{ "TP_PER_ENABLE", 0x7e78, 0 },
|
|
{ "FlmTxFlstEmpty", 30, 1 },
|
|
{ "RssLkpPerr", 29, 1 },
|
|
{ "FlmPerrSet", 28, 1 },
|
|
{ "ProtocolSramPerr", 27, 1 },
|
|
{ "ArpLutPerr", 26, 1 },
|
|
{ "CmRcfOpPerr", 25, 1 },
|
|
{ "CmCachePerr", 24, 1 },
|
|
{ "CmRcfDataPerr", 23, 1 },
|
|
{ "DbL2tLutPerr", 22, 1 },
|
|
{ "DbTxTidPerr", 21, 1 },
|
|
{ "DbExtPerr", 20, 1 },
|
|
{ "DbOpPerr", 19, 1 },
|
|
{ "TmCachePerr", 18, 1 },
|
|
{ "ETpOutCplFifoPerr", 17, 1 },
|
|
{ "ETpOutTcpFifoPerr", 16, 1 },
|
|
{ "ETpOutIpFifoPerr", 15, 1 },
|
|
{ "ETpOutEthFifoPerr", 14, 1 },
|
|
{ "ETpInCplFifoPerr", 13, 1 },
|
|
{ "ETpInTcpOptFifoPerr", 12, 1 },
|
|
{ "ETpInTcpFifoPerr", 11, 1 },
|
|
{ "ETpInIpFifoPerr", 10, 1 },
|
|
{ "ETpInEthFifoPerr", 9, 1 },
|
|
{ "CTpOutCplFifoPerr", 8, 1 },
|
|
{ "CTpOutPldFifoPerr", 7, 1 },
|
|
{ "CTpOutIpFifoPerr", 6, 1 },
|
|
{ "CTpOutEthFifoPerr", 5, 1 },
|
|
{ "CTpInCplFifoPerr", 4, 1 },
|
|
{ "CTpInTcpOpFifoPerr", 3, 1 },
|
|
{ "PduFbkFifoPerr", 2, 1 },
|
|
{ "CmOpExtFifoPerr", 1, 1 },
|
|
{ "DelInvFifoPerr", 0, 1 },
|
|
{ "TP_FLM_FREE_PS_CNT", 0x7e80, 0 },
|
|
{ "TP_FLM_FREE_RX_CNT", 0x7e84, 0 },
|
|
{ "FreeRxPageChn", 28, 1 },
|
|
{ "FreeRxPageCount", 0, 21 },
|
|
{ "TP_FLM_FREE_TX_CNT", 0x7e88, 0 },
|
|
{ "FreeTxPageChn", 28, 2 },
|
|
{ "FreeTxPageCount", 0, 21 },
|
|
{ "TP_TM_HEAP_PUSH_CNT", 0x7e8c, 0 },
|
|
{ "TP_TM_HEAP_POP_CNT", 0x7e90, 0 },
|
|
{ "TP_TM_DACK_PUSH_CNT", 0x7e94, 0 },
|
|
{ "TP_TM_DACK_POP_CNT", 0x7e98, 0 },
|
|
{ "TP_TM_MOD_PUSH_CNT", 0x7e9c, 0 },
|
|
{ "TP_MOD_POP_CNT", 0x7ea0, 0 },
|
|
{ "TP_TIMER_SEPARATOR", 0x7ea4, 0 },
|
|
{ "TimerSeparator", 16, 16 },
|
|
{ "DisableTimeFreeze", 0, 1 },
|
|
{ "TP_STAMP_TIME", 0x7ea8, 0 },
|
|
{ "TP_DEBUG_FLAGS", 0x7eac, 0 },
|
|
{ "RxTimerCompBuffer", 27, 1 },
|
|
{ "RxTimerDackFirst", 26, 1 },
|
|
{ "RxTimerDack", 25, 1 },
|
|
{ "RxTimerHeartbeat", 24, 1 },
|
|
{ "RxPawsDrop", 23, 1 },
|
|
{ "RxUrgDataDrop", 22, 1 },
|
|
{ "RxFutureData", 21, 1 },
|
|
{ "RxRcvRxmData", 20, 1 },
|
|
{ "RxRcvOooDataFin", 19, 1 },
|
|
{ "RxRcvOooData", 18, 1 },
|
|
{ "RxRcvWndZero", 17, 1 },
|
|
{ "RxRcvWndLtMss", 16, 1 },
|
|
{ "TxDfrFast", 13, 1 },
|
|
{ "TxRxmMisc", 12, 1 },
|
|
{ "TxDupAckInc", 11, 1 },
|
|
{ "TxRxmUrg", 10, 1 },
|
|
{ "TxRxmFin", 9, 1 },
|
|
{ "TxRxmSyn", 8, 1 },
|
|
{ "TxRxmNewReno", 7, 1 },
|
|
{ "TxRxmFast", 6, 1 },
|
|
{ "TxRxmTimer", 5, 1 },
|
|
{ "TxRxmTimerKeepalive", 4, 1 },
|
|
{ "TxRxmTimerPersist", 3, 1 },
|
|
{ "TxRcvAdvShrunk", 2, 1 },
|
|
{ "TxRcvAdvZero", 1, 1 },
|
|
{ "TxRcvAdvLtMss", 0, 1 },
|
|
{ "TP_RX_SCHED", 0x7eb0, 0 },
|
|
{ "CommitReset1", 31, 1 },
|
|
{ "CommitReset0", 30, 1 },
|
|
{ "ForceCong1", 29, 1 },
|
|
{ "ForceCong0", 28, 1 },
|
|
{ "EnableLpbkFull1", 26, 2 },
|
|
{ "EnableLpbkFull0", 24, 2 },
|
|
{ "EnableFifoFull1", 22, 2 },
|
|
{ "EnablePcmdFull1", 20, 2 },
|
|
{ "EnableHdrFull1", 18, 2 },
|
|
{ "EnableFifoFull0", 16, 2 },
|
|
{ "EnablePcmdFull0", 14, 2 },
|
|
{ "EnableHdrFull0", 12, 2 },
|
|
{ "TP_TX_SCHED", 0x7eb4, 0 },
|
|
{ "CommitReset3", 31, 1 },
|
|
{ "CommitReset2", 30, 1 },
|
|
{ "CommitReset1", 29, 1 },
|
|
{ "CommitReset0", 28, 1 },
|
|
{ "ForceCong3", 27, 1 },
|
|
{ "ForceCong2", 26, 1 },
|
|
{ "ForceCong1", 25, 1 },
|
|
{ "ForceCong0", 24, 1 },
|
|
{ "CommitLimit3", 18, 6 },
|
|
{ "CommitLimit2", 12, 6 },
|
|
{ "CommitLimit1", 6, 6 },
|
|
{ "CommitLimit0", 0, 6 },
|
|
{ "TP_FX_SCHED", 0x7eb8, 0 },
|
|
{ "TxChnXoff3", 19, 1 },
|
|
{ "TxChnXoff2", 18, 1 },
|
|
{ "TxChnXoff1", 17, 1 },
|
|
{ "TxChnXoff0", 16, 1 },
|
|
{ "TxModXoff7", 15, 1 },
|
|
{ "TxModXoff6", 14, 1 },
|
|
{ "TxModXoff5", 13, 1 },
|
|
{ "TxModXoff4", 12, 1 },
|
|
{ "TxModXoff3", 11, 1 },
|
|
{ "TxModXoff2", 10, 1 },
|
|
{ "TxModXoff1", 9, 1 },
|
|
{ "TxModXoff0", 8, 1 },
|
|
{ "RxChnXoff3", 7, 1 },
|
|
{ "RxChnXoff2", 6, 1 },
|
|
{ "RxChnXoff1", 5, 1 },
|
|
{ "RxChnXoff0", 4, 1 },
|
|
{ "RxModXoff1", 1, 1 },
|
|
{ "RxModXoff0", 0, 1 },
|
|
{ "TP_TX_ORATE", 0x7ebc, 0 },
|
|
{ "OfdRate3", 24, 8 },
|
|
{ "OfdRate2", 16, 8 },
|
|
{ "OfdRate1", 8, 8 },
|
|
{ "OfdRate0", 0, 8 },
|
|
{ "TP_IX_SCHED0", 0x7ec0, 0 },
|
|
{ "TP_IX_SCHED1", 0x7ec4, 0 },
|
|
{ "TP_IX_SCHED2", 0x7ec8, 0 },
|
|
{ "TP_IX_SCHED3", 0x7ecc, 0 },
|
|
{ "TP_TX_TRATE", 0x7ed0, 0 },
|
|
{ "TnlRate3", 24, 8 },
|
|
{ "TnlRate2", 16, 8 },
|
|
{ "TnlRate1", 8, 8 },
|
|
{ "TnlRate0", 0, 8 },
|
|
{ "TP_DBG_LA_CONFIG", 0x7ed4, 0 },
|
|
{ "DbgLaOpcEnable", 24, 8 },
|
|
{ "DbgLaWhlf", 23, 1 },
|
|
{ "DbgLaWptr", 16, 7 },
|
|
{ "DbgLaMode", 14, 2 },
|
|
{ "DbgLaFatalFreeze", 13, 1 },
|
|
{ "DbgLaEnable", 12, 1 },
|
|
{ "DbgLaRptr", 0, 7 },
|
|
{ "TP_DBG_LA_DATAL", 0x7ed8, 0 },
|
|
{ "TP_DBG_LA_DATAH", 0x7edc, 0 },
|
|
{ "TP_PROTOCOL_CNTRL", 0x7ee8, 0 },
|
|
{ "WriteEnable", 31, 1 },
|
|
{ "TcamEnable", 10, 1 },
|
|
{ "BlockSelect", 8, 2 },
|
|
{ "LineAddress", 1, 7 },
|
|
{ "RequestDone", 0, 1 },
|
|
{ "TP_PROTOCOL_DATA0", 0x7eec, 0 },
|
|
{ "TP_PROTOCOL_DATA1", 0x7ef0, 0 },
|
|
{ "TP_PROTOCOL_DATA2", 0x7ef4, 0 },
|
|
{ "TP_PROTOCOL_DATA3", 0x7ef8, 0 },
|
|
{ "TP_PROTOCOL_DATA4", 0x7efc, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_ulp_tx_regs[] = {
|
|
{ "ULP_TX_CONFIG", 0x8dc0, 0 },
|
|
{ "PHYS_ADDR_RESP_EN", 6, 1 },
|
|
{ "ENDIANESS_CHANGE", 5, 1 },
|
|
{ "ERR_RTAG_EN", 4, 1 },
|
|
{ "TSO_ETHLEN_EN", 3, 1 },
|
|
{ "emsg_more_info", 2, 1 },
|
|
{ "LOSDR", 1, 1 },
|
|
{ "extra_tag_insertion_enable", 0, 1 },
|
|
{ "ULP_TX_PERR_INJECT", 0x8dc4, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "ULP_TX_INT_ENABLE", 0x8dc8, 0 },
|
|
{ "Pbl_bound_err_ch3", 31, 1 },
|
|
{ "Pbl_bound_err_ch2", 30, 1 },
|
|
{ "Pbl_bound_err_ch1", 29, 1 },
|
|
{ "Pbl_bound_err_ch0", 28, 1 },
|
|
{ "sge2ulp_fifo_perr_set3", 27, 1 },
|
|
{ "sge2ulp_fifo_perr_set2", 26, 1 },
|
|
{ "sge2ulp_fifo_perr_set1", 25, 1 },
|
|
{ "sge2ulp_fifo_perr_set0", 24, 1 },
|
|
{ "cim2ulp_fifo_perr_set3", 23, 1 },
|
|
{ "cim2ulp_fifo_perr_set2", 22, 1 },
|
|
{ "cim2ulp_fifo_perr_set1", 21, 1 },
|
|
{ "cim2ulp_fifo_perr_set0", 20, 1 },
|
|
{ "CQE_fifo_perr_set3", 19, 1 },
|
|
{ "CQE_fifo_perr_set2", 18, 1 },
|
|
{ "CQE_fifo_perr_set1", 17, 1 },
|
|
{ "CQE_fifo_perr_set0", 16, 1 },
|
|
{ "pbl_fifo_perr_set3", 15, 1 },
|
|
{ "pbl_fifo_perr_set2", 14, 1 },
|
|
{ "pbl_fifo_perr_set1", 13, 1 },
|
|
{ "pbl_fifo_perr_set0", 12, 1 },
|
|
{ "cmd_fifo_perr_set3", 11, 1 },
|
|
{ "cmd_fifo_perr_set2", 10, 1 },
|
|
{ "cmd_fifo_perr_set1", 9, 1 },
|
|
{ "cmd_fifo_perr_set0", 8, 1 },
|
|
{ "lso_hdr_sram_perr_set3", 7, 1 },
|
|
{ "lso_hdr_sram_perr_set2", 6, 1 },
|
|
{ "lso_hdr_sram_perr_set1", 5, 1 },
|
|
{ "lso_hdr_sram_perr_set0", 4, 1 },
|
|
{ "ULP_TX_INT_CAUSE", 0x8dcc, 0 },
|
|
{ "Pbl_bound_err_ch3", 31, 1 },
|
|
{ "Pbl_bound_err_ch2", 30, 1 },
|
|
{ "Pbl_bound_err_ch1", 29, 1 },
|
|
{ "Pbl_bound_err_ch0", 28, 1 },
|
|
{ "sge2ulp_fifo_perr_set3", 27, 1 },
|
|
{ "sge2ulp_fifo_perr_set2", 26, 1 },
|
|
{ "sge2ulp_fifo_perr_set1", 25, 1 },
|
|
{ "sge2ulp_fifo_perr_set0", 24, 1 },
|
|
{ "cim2ulp_fifo_perr_set3", 23, 1 },
|
|
{ "cim2ulp_fifo_perr_set2", 22, 1 },
|
|
{ "cim2ulp_fifo_perr_set1", 21, 1 },
|
|
{ "cim2ulp_fifo_perr_set0", 20, 1 },
|
|
{ "CQE_fifo_perr_set3", 19, 1 },
|
|
{ "CQE_fifo_perr_set2", 18, 1 },
|
|
{ "CQE_fifo_perr_set1", 17, 1 },
|
|
{ "CQE_fifo_perr_set0", 16, 1 },
|
|
{ "pbl_fifo_perr_set3", 15, 1 },
|
|
{ "pbl_fifo_perr_set2", 14, 1 },
|
|
{ "pbl_fifo_perr_set1", 13, 1 },
|
|
{ "pbl_fifo_perr_set0", 12, 1 },
|
|
{ "cmd_fifo_perr_set3", 11, 1 },
|
|
{ "cmd_fifo_perr_set2", 10, 1 },
|
|
{ "cmd_fifo_perr_set1", 9, 1 },
|
|
{ "cmd_fifo_perr_set0", 8, 1 },
|
|
{ "lso_hdr_sram_perr_set3", 7, 1 },
|
|
{ "lso_hdr_sram_perr_set2", 6, 1 },
|
|
{ "lso_hdr_sram_perr_set1", 5, 1 },
|
|
{ "lso_hdr_sram_perr_set0", 4, 1 },
|
|
{ "ULP_TX_PERR_ENABLE", 0x8dd0, 0 },
|
|
{ "sge2ulp_fifo_perr_set3", 27, 1 },
|
|
{ "sge2ulp_fifo_perr_set2", 26, 1 },
|
|
{ "sge2ulp_fifo_perr_set1", 25, 1 },
|
|
{ "sge2ulp_fifo_perr_set0", 24, 1 },
|
|
{ "cim2ulp_fifo_perr_set3", 23, 1 },
|
|
{ "cim2ulp_fifo_perr_set2", 22, 1 },
|
|
{ "cim2ulp_fifo_perr_set1", 21, 1 },
|
|
{ "cim2ulp_fifo_perr_set0", 20, 1 },
|
|
{ "CQE_fifo_perr_set3", 19, 1 },
|
|
{ "CQE_fifo_perr_set2", 18, 1 },
|
|
{ "CQE_fifo_perr_set1", 17, 1 },
|
|
{ "CQE_fifo_perr_set0", 16, 1 },
|
|
{ "pbl_fifo_perr_set3", 15, 1 },
|
|
{ "pbl_fifo_perr_set2", 14, 1 },
|
|
{ "pbl_fifo_perr_set1", 13, 1 },
|
|
{ "pbl_fifo_perr_set0", 12, 1 },
|
|
{ "cmd_fifo_perr_set3", 11, 1 },
|
|
{ "cmd_fifo_perr_set2", 10, 1 },
|
|
{ "cmd_fifo_perr_set1", 9, 1 },
|
|
{ "cmd_fifo_perr_set0", 8, 1 },
|
|
{ "lso_hdr_sram_perr_set3", 7, 1 },
|
|
{ "lso_hdr_sram_perr_set2", 6, 1 },
|
|
{ "lso_hdr_sram_perr_set1", 5, 1 },
|
|
{ "lso_hdr_sram_perr_set0", 4, 1 },
|
|
{ "ULP_TX_TPT_LLIMIT", 0x8dd4, 0 },
|
|
{ "ULP_TX_TPT_ULIMIT", 0x8dd8, 0 },
|
|
{ "ULP_TX_PBL_LLIMIT", 0x8ddc, 0 },
|
|
{ "ULP_TX_PBL_ULIMIT", 0x8de0, 0 },
|
|
{ "ULP_TX_CPL_PACK_SIZE1", 0x8df8, 0 },
|
|
{ "Ch3Size1", 24, 8 },
|
|
{ "Ch2Size1", 16, 8 },
|
|
{ "Ch1Size1", 8, 8 },
|
|
{ "Ch0Size1", 0, 8 },
|
|
{ "ULP_TX_CPL_PACK_SIZE2", 0x8dfc, 0 },
|
|
{ "Ch3Size2", 24, 8 },
|
|
{ "Ch2Size2", 16, 8 },
|
|
{ "Ch1Size2", 8, 8 },
|
|
{ "Ch0Size2", 0, 8 },
|
|
{ "ULP_TX_ERR_MSG2CIM", 0x8e00, 0 },
|
|
{ "ULP_TX_ERR_TABLE_BASE", 0x8e04, 0 },
|
|
{ "ULP_TX_ERR_CNT_CH0", 0x8e10, 0 },
|
|
{ "ULP_TX_ERR_CNT_CH1", 0x8e14, 0 },
|
|
{ "ULP_TX_ERR_CNT_CH2", 0x8e18, 0 },
|
|
{ "ULP_TX_ERR_CNT_CH3", 0x8e1c, 0 },
|
|
{ "ULP_TX_FC_SOF", 0x8e20, 0 },
|
|
{ "SOF_FS3", 24, 8 },
|
|
{ "SOF_FS2", 16, 8 },
|
|
{ "SOF_3", 8, 8 },
|
|
{ "SOF_2", 0, 8 },
|
|
{ "ULP_TX_FC_EOF", 0x8e24, 0 },
|
|
{ "EOF_LS3", 24, 8 },
|
|
{ "EOF_LS2", 16, 8 },
|
|
{ "EOF_3", 8, 8 },
|
|
{ "EOF_2", 0, 8 },
|
|
{ "ULP_TX_CGEN_GLOBAL", 0x8e28, 0 },
|
|
{ "ULP_TX_CGEN", 0x8e2c, 0 },
|
|
{ "ULP_TX_CGEN_Storage", 8, 4 },
|
|
{ "ULP_TX_CGEN_RDMA", 4, 4 },
|
|
{ "ULP_TX_CGEN_Channel", 0, 4 },
|
|
{ "ULP_TX_MEM_CFG", 0x8e30, 0 },
|
|
{ "ULP_TX_PERR_INJECT_2", 0x8e34, 0 },
|
|
{ "MemSel", 1, 3 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "ULP_TX_INT_ENABLE_2", 0x8e7c, 0 },
|
|
{ "smarbt2ulp_data_perr_set", 12, 1 },
|
|
{ "ulp2tp_data_perr_set", 11, 1 },
|
|
{ "ma2ulp_data_perr_set", 10, 1 },
|
|
{ "sge2ulp_data_perr_set", 9, 1 },
|
|
{ "cim2ulp_data_perr_set", 8, 1 },
|
|
{ "fso_hdr_sram_perr_set3", 7, 1 },
|
|
{ "fso_hdr_sram_perr_set2", 6, 1 },
|
|
{ "fso_hdr_sram_perr_set1", 5, 1 },
|
|
{ "fso_hdr_sram_perr_set0", 4, 1 },
|
|
{ "t10_pi_sram_perr_set3", 3, 1 },
|
|
{ "t10_pi_sram_perr_set2", 2, 1 },
|
|
{ "t10_pi_sram_perr_set1", 1, 1 },
|
|
{ "t10_pi_sram_perr_set0", 0, 1 },
|
|
{ "ULP_TX_INT_CAUSE_2", 0x8e80, 0 },
|
|
{ "smarbt2ulp_data_perr_set", 12, 1 },
|
|
{ "ulp2tp_data_perr_set", 11, 1 },
|
|
{ "ma2ulp_data_perr_set", 10, 1 },
|
|
{ "sge2ulp_data_perr_set", 9, 1 },
|
|
{ "cim2ulp_data_perr_set", 8, 1 },
|
|
{ "fso_hdr_sram_perr_set3", 7, 1 },
|
|
{ "fso_hdr_sram_perr_set2", 6, 1 },
|
|
{ "fso_hdr_sram_perr_set1", 5, 1 },
|
|
{ "fso_hdr_sram_perr_set0", 4, 1 },
|
|
{ "t10_pi_sram_perr_set3", 3, 1 },
|
|
{ "t10_pi_sram_perr_set2", 2, 1 },
|
|
{ "t10_pi_sram_perr_set1", 1, 1 },
|
|
{ "t10_pi_sram_perr_set0", 0, 1 },
|
|
{ "ULP_TX_PERR_ENABLE_2", 0x8e84, 0 },
|
|
{ "smarbt2ulp_data_perr_set", 12, 1 },
|
|
{ "ulp2tp_data_perr_set", 11, 1 },
|
|
{ "ma2ulp_data_perr_set", 10, 1 },
|
|
{ "sge2ulp_data_perr_set", 9, 1 },
|
|
{ "cim2ulp_data_perr_set", 8, 1 },
|
|
{ "fso_hdr_sram_perr_set3", 7, 1 },
|
|
{ "fso_hdr_sram_perr_set2", 6, 1 },
|
|
{ "fso_hdr_sram_perr_set1", 5, 1 },
|
|
{ "fso_hdr_sram_perr_set0", 4, 1 },
|
|
{ "t10_pi_sram_perr_set3", 3, 1 },
|
|
{ "t10_pi_sram_perr_set2", 2, 1 },
|
|
{ "t10_pi_sram_perr_set1", 1, 1 },
|
|
{ "t10_pi_sram_perr_set0", 0, 1 },
|
|
{ "ULP_TX_SE_CNT_ERR", 0x8ea0, 0 },
|
|
{ "ERR_CH3", 12, 4 },
|
|
{ "ERR_CH2", 8, 4 },
|
|
{ "ERR_CH1", 4, 4 },
|
|
{ "ERR_CH0", 0, 4 },
|
|
{ "ULP_TX_SE_CNT_CLR", 0x8ea4, 0 },
|
|
{ "CLR_DROP", 16, 4 },
|
|
{ "CLR_CH3", 12, 4 },
|
|
{ "CLR_CH2", 8, 4 },
|
|
{ "CLR_CH1", 4, 4 },
|
|
{ "CLR_CH0", 0, 4 },
|
|
{ "ULP_TX_SE_CNT_CH0", 0x8ea8, 0 },
|
|
{ "SOP_CNT_ULP2TP", 28, 4 },
|
|
{ "EOP_CNT_ULP2TP", 24, 4 },
|
|
{ "SOP_CNT_LSO_IN", 20, 4 },
|
|
{ "EOP_CNT_LSO_IN", 16, 4 },
|
|
{ "SOP_CNT_ALG_IN", 12, 4 },
|
|
{ "EOP_CNT_ALG_IN", 8, 4 },
|
|
{ "SOP_CNT_CIM2ULP", 4, 4 },
|
|
{ "EOP_CNT_CIM2ULP", 0, 4 },
|
|
{ "ULP_TX_SE_CNT_CH1", 0x8eac, 0 },
|
|
{ "SOP_CNT_ULP2TP", 28, 4 },
|
|
{ "EOP_CNT_ULP2TP", 24, 4 },
|
|
{ "SOP_CNT_LSO_IN", 20, 4 },
|
|
{ "EOP_CNT_LSO_IN", 16, 4 },
|
|
{ "SOP_CNT_ALG_IN", 12, 4 },
|
|
{ "EOP_CNT_ALG_IN", 8, 4 },
|
|
{ "SOP_CNT_CIM2ULP", 4, 4 },
|
|
{ "EOP_CNT_CIM2ULP", 0, 4 },
|
|
{ "ULP_TX_SE_CNT_CH2", 0x8eb0, 0 },
|
|
{ "SOP_CNT_ULP2TP", 28, 4 },
|
|
{ "EOP_CNT_ULP2TP", 24, 4 },
|
|
{ "SOP_CNT_LSO_IN", 20, 4 },
|
|
{ "EOP_CNT_LSO_IN", 16, 4 },
|
|
{ "SOP_CNT_ALG_IN", 12, 4 },
|
|
{ "EOP_CNT_ALG_IN", 8, 4 },
|
|
{ "SOP_CNT_CIM2ULP", 4, 4 },
|
|
{ "EOP_CNT_CIM2ULP", 0, 4 },
|
|
{ "ULP_TX_SE_CNT_CH3", 0x8eb4, 0 },
|
|
{ "SOP_CNT_ULP2TP", 28, 4 },
|
|
{ "EOP_CNT_ULP2TP", 24, 4 },
|
|
{ "SOP_CNT_LSO_IN", 20, 4 },
|
|
{ "EOP_CNT_LSO_IN", 16, 4 },
|
|
{ "SOP_CNT_ALG_IN", 12, 4 },
|
|
{ "EOP_CNT_ALG_IN", 8, 4 },
|
|
{ "SOP_CNT_CIM2ULP", 4, 4 },
|
|
{ "EOP_CNT_CIM2ULP", 0, 4 },
|
|
{ "ULP_TX_DROP_CNT", 0x8eb8, 0 },
|
|
{ "DROP_CH3", 12, 4 },
|
|
{ "DROP_CH2", 8, 4 },
|
|
{ "DROP_CH1", 4, 4 },
|
|
{ "DROP_CH0", 0, 4 },
|
|
{ "ULP_TX_FPGA_CMD_CTRL", 0x8e38, 0 },
|
|
{ "channel_sel", 12, 2 },
|
|
{ "intf_sel", 4, 4 },
|
|
{ "num_flits", 1, 3 },
|
|
{ "cmd_gen_en", 0, 1 },
|
|
{ "ULP_TX_FPGA_CMD_0", 0x8e3c, 0 },
|
|
{ "ULP_TX_FPGA_CMD_1", 0x8e40, 0 },
|
|
{ "ULP_TX_FPGA_CMD_2", 0x8e44, 0 },
|
|
{ "ULP_TX_FPGA_CMD_3", 0x8e48, 0 },
|
|
{ "ULP_TX_FPGA_CMD_4", 0x8e4c, 0 },
|
|
{ "ULP_TX_FPGA_CMD_5", 0x8e50, 0 },
|
|
{ "ULP_TX_FPGA_CMD_6", 0x8e54, 0 },
|
|
{ "ULP_TX_FPGA_CMD_7", 0x8e58, 0 },
|
|
{ "ULP_TX_FPGA_CMD_8", 0x8e5c, 0 },
|
|
{ "ULP_TX_FPGA_CMD_9", 0x8e60, 0 },
|
|
{ "ULP_TX_FPGA_CMD_10", 0x8e64, 0 },
|
|
{ "ULP_TX_FPGA_CMD_11", 0x8e68, 0 },
|
|
{ "ULP_TX_FPGA_CMD_12", 0x8e6c, 0 },
|
|
{ "ULP_TX_FPGA_CMD_13", 0x8e70, 0 },
|
|
{ "ULP_TX_FPGA_CMD_14", 0x8e74, 0 },
|
|
{ "ULP_TX_FPGA_CMD_15", 0x8e78, 0 },
|
|
{ "ULP_TX_ASIC_DEBUG_CTRL", 0x8f70, 0 },
|
|
{ "ULP_TX_ASIC_DEBUG_0", 0x8f74, 0 },
|
|
{ "ULP_TX_ASIC_DEBUG_1", 0x8f78, 0 },
|
|
{ "ULP_TX_ASIC_DEBUG_2", 0x8f7c, 0 },
|
|
{ "ULP_TX_ASIC_DEBUG_3", 0x8f80, 0 },
|
|
{ "ULP_TX_ASIC_DEBUG_4", 0x8f84, 0 },
|
|
{ "ULP_TX_CSU_REVISION", 0x8ebc, 0 },
|
|
{ "ULP_TX_LA_RDPTR_0", 0x8ec0, 0 },
|
|
{ "ULP_TX_LA_RDDATA_0", 0x8ec4, 0 },
|
|
{ "ULP_TX_LA_WRPTR_0", 0x8ec8, 0 },
|
|
{ "ULP_TX_LA_RESERVED_0", 0x8ecc, 0 },
|
|
{ "ULP_TX_LA_RDPTR_1", 0x8ed0, 0 },
|
|
{ "ULP_TX_LA_RDDATA_1", 0x8ed4, 0 },
|
|
{ "ULP_TX_LA_WRPTR_1", 0x8ed8, 0 },
|
|
{ "ULP_TX_LA_RESERVED_1", 0x8edc, 0 },
|
|
{ "ULP_TX_LA_RDPTR_2", 0x8ee0, 0 },
|
|
{ "ULP_TX_LA_RDDATA_2", 0x8ee4, 0 },
|
|
{ "ULP_TX_LA_WRPTR_2", 0x8ee8, 0 },
|
|
{ "ULP_TX_LA_RESERVED_2", 0x8eec, 0 },
|
|
{ "ULP_TX_LA_RDPTR_3", 0x8ef0, 0 },
|
|
{ "ULP_TX_LA_RDDATA_3", 0x8ef4, 0 },
|
|
{ "ULP_TX_LA_WRPTR_3", 0x8ef8, 0 },
|
|
{ "ULP_TX_LA_RESERVED_3", 0x8efc, 0 },
|
|
{ "ULP_TX_LA_RDPTR_4", 0x8f00, 0 },
|
|
{ "ULP_TX_LA_RDDATA_4", 0x8f04, 0 },
|
|
{ "ULP_TX_LA_WRPTR_4", 0x8f08, 0 },
|
|
{ "ULP_TX_LA_RESERVED_4", 0x8f0c, 0 },
|
|
{ "ULP_TX_LA_RDPTR_5", 0x8f10, 0 },
|
|
{ "ULP_TX_LA_RDDATA_5", 0x8f14, 0 },
|
|
{ "ULP_TX_LA_WRPTR_5", 0x8f18, 0 },
|
|
{ "ULP_TX_LA_RESERVED_5", 0x8f1c, 0 },
|
|
{ "ULP_TX_LA_RDPTR_6", 0x8f20, 0 },
|
|
{ "ULP_TX_LA_RDDATA_6", 0x8f24, 0 },
|
|
{ "ULP_TX_LA_WRPTR_6", 0x8f28, 0 },
|
|
{ "ULP_TX_LA_RESERVED_6", 0x8f2c, 0 },
|
|
{ "ULP_TX_LA_RDPTR_7", 0x8f30, 0 },
|
|
{ "ULP_TX_LA_RDDATA_7", 0x8f34, 0 },
|
|
{ "ULP_TX_LA_WRPTR_7", 0x8f38, 0 },
|
|
{ "ULP_TX_LA_RESERVED_7", 0x8f3c, 0 },
|
|
{ "ULP_TX_LA_RDPTR_8", 0x8f40, 0 },
|
|
{ "ULP_TX_LA_RDDATA_8", 0x8f44, 0 },
|
|
{ "ULP_TX_LA_WRPTR_8", 0x8f48, 0 },
|
|
{ "ULP_TX_LA_RESERVED_8", 0x8f4c, 0 },
|
|
{ "ULP_TX_LA_RDPTR_9", 0x8f50, 0 },
|
|
{ "ULP_TX_LA_RDDATA_9", 0x8f54, 0 },
|
|
{ "ULP_TX_LA_WRPTR_9", 0x8f58, 0 },
|
|
{ "ULP_TX_LA_RESERVED_9", 0x8f5c, 0 },
|
|
{ "ULP_TX_LA_RDPTR_10", 0x8f60, 0 },
|
|
{ "ULP_TX_LA_RDDATA_10", 0x8f64, 0 },
|
|
{ "ULP_TX_LA_WRPTR_10", 0x8f68, 0 },
|
|
{ "ULP_TX_LA_RESERVED_10", 0x8f6c, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_pm_rx_regs[] = {
|
|
{ "PM_RX_CFG", 0x8fc0, 0 },
|
|
{ "ch1_output", 27, 5 },
|
|
{ "strobe1", 16, 1 },
|
|
{ "ch1_input", 11, 5 },
|
|
{ "ch2_input", 6, 5 },
|
|
{ "ch3_input", 1, 5 },
|
|
{ "strobe0", 0, 1 },
|
|
{ "PM_RX_MODE", 0x8fc4, 0 },
|
|
{ "use_bundle_len", 4, 1 },
|
|
{ "stat_to_ch", 3, 1 },
|
|
{ "stat_from_ch", 1, 2 },
|
|
{ "prefetch_enable", 0, 1 },
|
|
{ "PM_RX_STAT_CONFIG", 0x8fc8, 0 },
|
|
{ "PM_RX_STAT_COUNT", 0x8fcc, 0 },
|
|
{ "PM_RX_DBG_CTRL", 0x8fd0, 0 },
|
|
{ "OspiWrBusy", 21, 2 },
|
|
{ "IspiWrBusy", 17, 4 },
|
|
{ "PMDbgAddr", 0, 17 },
|
|
{ "PM_RX_DBG_DATA", 0x8fd4, 0 },
|
|
{ "PM_RX_INT_ENABLE", 0x8fd8, 0 },
|
|
{ "ospi_overflow1", 28, 1 },
|
|
{ "ospi_overflow0", 27, 1 },
|
|
{ "ma_intf_sdc_err", 26, 1 },
|
|
{ "bundle_len_ParErr", 25, 1 },
|
|
{ "bundle_len_ovfl", 24, 1 },
|
|
{ "sdc_err", 23, 1 },
|
|
{ "zero_e_cmd_error", 22, 1 },
|
|
{ "iespi0_fifo2x_Rx_framing_error", 21, 1 },
|
|
{ "iespi1_fifo2x_Rx_framing_error", 20, 1 },
|
|
{ "iespi2_fifo2x_Rx_framing_error", 19, 1 },
|
|
{ "iespi3_fifo2x_Rx_framing_error", 18, 1 },
|
|
{ "iespi0_Rx_framing_error", 17, 1 },
|
|
{ "iespi1_Rx_framing_error", 16, 1 },
|
|
{ "iespi2_Rx_framing_error", 15, 1 },
|
|
{ "iespi3_Rx_framing_error", 14, 1 },
|
|
{ "iespi0_Tx_framing_error", 13, 1 },
|
|
{ "iespi1_Tx_framing_error", 12, 1 },
|
|
{ "iespi2_Tx_framing_error", 11, 1 },
|
|
{ "iespi3_Tx_framing_error", 10, 1 },
|
|
{ "ocspi0_Rx_framing_error", 9, 1 },
|
|
{ "ocspi1_Rx_framing_error", 8, 1 },
|
|
{ "ocspi0_Tx_framing_error", 7, 1 },
|
|
{ "ocspi1_Tx_framing_error", 6, 1 },
|
|
{ "ocspi0_ofifo2x_Tx_framing_error", 5, 1 },
|
|
{ "ocspi1_ofifo2x_Tx_framing_error", 4, 1 },
|
|
{ "ocspi_par_error", 3, 1 },
|
|
{ "db_options_par_error", 2, 1 },
|
|
{ "iespi_par_error", 1, 1 },
|
|
{ "e_pcmd_par_error", 0, 1 },
|
|
{ "PM_RX_INT_CAUSE", 0x8fdc, 0 },
|
|
{ "ospi_overflow1", 28, 1 },
|
|
{ "ospi_overflow0", 27, 1 },
|
|
{ "ma_intf_sdc_err", 26, 1 },
|
|
{ "bundle_len_ParErr", 25, 1 },
|
|
{ "bundle_len_ovfl", 24, 1 },
|
|
{ "sdc_err", 23, 1 },
|
|
{ "zero_e_cmd_error", 22, 1 },
|
|
{ "iespi0_fifo2x_Rx_framing_error", 21, 1 },
|
|
{ "iespi1_fifo2x_Rx_framing_error", 20, 1 },
|
|
{ "iespi2_fifo2x_Rx_framing_error", 19, 1 },
|
|
{ "iespi3_fifo2x_Rx_framing_error", 18, 1 },
|
|
{ "iespi0_Rx_framing_error", 17, 1 },
|
|
{ "iespi1_Rx_framing_error", 16, 1 },
|
|
{ "iespi2_Rx_framing_error", 15, 1 },
|
|
{ "iespi3_Rx_framing_error", 14, 1 },
|
|
{ "iespi0_Tx_framing_error", 13, 1 },
|
|
{ "iespi1_Tx_framing_error", 12, 1 },
|
|
{ "iespi2_Tx_framing_error", 11, 1 },
|
|
{ "iespi3_Tx_framing_error", 10, 1 },
|
|
{ "ocspi0_Rx_framing_error", 9, 1 },
|
|
{ "ocspi1_Rx_framing_error", 8, 1 },
|
|
{ "ocspi0_Tx_framing_error", 7, 1 },
|
|
{ "ocspi1_Tx_framing_error", 6, 1 },
|
|
{ "ocspi0_ofifo2x_Tx_framing_error", 5, 1 },
|
|
{ "ocspi1_ofifo2x_Tx_framing_error", 4, 1 },
|
|
{ "ocspi_par_error", 3, 1 },
|
|
{ "db_options_par_error", 2, 1 },
|
|
{ "iespi_par_error", 1, 1 },
|
|
{ "e_pcmd_par_error", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_pm_tx_regs[] = {
|
|
{ "PM_TX_CFG", 0x8fe0, 0 },
|
|
{ "ch1_output", 27, 5 },
|
|
{ "ch2_output", 22, 5 },
|
|
{ "ch3_output", 17, 5 },
|
|
{ "strobe1", 16, 1 },
|
|
{ "ch1_input", 11, 5 },
|
|
{ "ch2_input", 6, 5 },
|
|
{ "ch3_input", 1, 5 },
|
|
{ "strobe0", 0, 1 },
|
|
{ "PM_TX_MODE", 0x8fe4, 0 },
|
|
{ "cong_thresh3", 25, 7 },
|
|
{ "cong_thresh2", 18, 7 },
|
|
{ "cong_thresh1", 11, 7 },
|
|
{ "cong_thresh0", 4, 7 },
|
|
{ "use_bundle_len", 3, 1 },
|
|
{ "stat_channel", 1, 2 },
|
|
{ "prefetch_enable", 0, 1 },
|
|
{ "PM_TX_STAT_CONFIG", 0x8fe8, 0 },
|
|
{ "PM_TX_STAT_COUNT", 0x8fec, 0 },
|
|
{ "PM_TX_DBG_CTRL", 0x8ff0, 0 },
|
|
{ "OspiWrBusy", 21, 4 },
|
|
{ "IspiWrBusy", 17, 4 },
|
|
{ "PMDbgAddr", 0, 17 },
|
|
{ "PM_TX_DBG_DATA", 0x8ff4, 0 },
|
|
{ "PM_TX_INT_ENABLE", 0x8ff8, 0 },
|
|
{ "pcmd_len_ovfl0", 31, 1 },
|
|
{ "pcmd_len_ovfl1", 30, 1 },
|
|
{ "pcmd_len_ovfl2", 29, 1 },
|
|
{ "zero_c_cmd_error", 28, 1 },
|
|
{ "icspi0_fifo2x_Rx_framing_error", 27, 1 },
|
|
{ "icspi1_fifo2x_Rx_framing_error", 26, 1 },
|
|
{ "icspi2_fifo2x_Rx_framing_error", 25, 1 },
|
|
{ "icspi3_fifo2x_Rx_framing_error", 24, 1 },
|
|
{ "icspi0_Rx_framing_error", 23, 1 },
|
|
{ "icspi1_Rx_framing_error", 22, 1 },
|
|
{ "icspi2_Rx_framing_error", 21, 1 },
|
|
{ "icspi3_Rx_framing_error", 20, 1 },
|
|
{ "icspi0_Tx_framing_error", 19, 1 },
|
|
{ "icspi1_Tx_framing_error", 18, 1 },
|
|
{ "icspi2_Tx_framing_error", 17, 1 },
|
|
{ "icspi3_Tx_framing_error", 16, 1 },
|
|
{ "oespi0_Rx_framing_error", 15, 1 },
|
|
{ "oespi1_Rx_framing_error", 14, 1 },
|
|
{ "oespi2_Rx_framing_error", 13, 1 },
|
|
{ "oespi3_Rx_framing_error", 12, 1 },
|
|
{ "oespi0_Tx_framing_error", 11, 1 },
|
|
{ "oespi1_Tx_framing_error", 10, 1 },
|
|
{ "oespi2_Tx_framing_error", 9, 1 },
|
|
{ "oespi3_Tx_framing_error", 8, 1 },
|
|
{ "oespi0_ofifo2x_Tx_framing_error", 7, 1 },
|
|
{ "oespi1_ofifo2x_Tx_framing_error", 6, 1 },
|
|
{ "oespi2_ofifo2x_Tx_framing_error", 5, 1 },
|
|
{ "oespi3_ofifo2x_Tx_framing_error", 4, 1 },
|
|
{ "oespi_par_error", 3, 1 },
|
|
{ "db_options_par_error", 2, 1 },
|
|
{ "icspi_par_error", 1, 1 },
|
|
{ "c_pcmd_par_error", 0, 1 },
|
|
{ "PM_TX_INT_CAUSE", 0x8ffc, 0 },
|
|
{ "pcmd_len_ovfl0", 31, 1 },
|
|
{ "pcmd_len_ovfl1", 30, 1 },
|
|
{ "pcmd_len_ovfl2", 29, 1 },
|
|
{ "zero_c_cmd_error", 28, 1 },
|
|
{ "icspi0_fifo2x_Rx_framing_error", 27, 1 },
|
|
{ "icspi1_fifo2x_Rx_framing_error", 26, 1 },
|
|
{ "icspi2_fifo2x_Rx_framing_error", 25, 1 },
|
|
{ "icspi3_fifo2x_Rx_framing_error", 24, 1 },
|
|
{ "icspi0_Rx_framing_error", 23, 1 },
|
|
{ "icspi1_Rx_framing_error", 22, 1 },
|
|
{ "icspi2_Rx_framing_error", 21, 1 },
|
|
{ "icspi3_Rx_framing_error", 20, 1 },
|
|
{ "icspi0_Tx_framing_error", 19, 1 },
|
|
{ "icspi1_Tx_framing_error", 18, 1 },
|
|
{ "icspi2_Tx_framing_error", 17, 1 },
|
|
{ "icspi3_Tx_framing_error", 16, 1 },
|
|
{ "oespi0_Rx_framing_error", 15, 1 },
|
|
{ "oespi1_Rx_framing_error", 14, 1 },
|
|
{ "oespi2_Rx_framing_error", 13, 1 },
|
|
{ "oespi3_Rx_framing_error", 12, 1 },
|
|
{ "oespi0_Tx_framing_error", 11, 1 },
|
|
{ "oespi1_Tx_framing_error", 10, 1 },
|
|
{ "oespi2_Tx_framing_error", 9, 1 },
|
|
{ "oespi3_Tx_framing_error", 8, 1 },
|
|
{ "oespi0_ofifo2x_Tx_framing_error", 7, 1 },
|
|
{ "oespi1_ofifo2x_Tx_framing_error", 6, 1 },
|
|
{ "oespi2_ofifo2x_Tx_framing_error", 5, 1 },
|
|
{ "oespi3_ofifo2x_Tx_framing_error", 4, 1 },
|
|
{ "ospi_or_bundle_len_par_err", 3, 1 },
|
|
{ "db_options_par_error", 2, 1 },
|
|
{ "icspi_par_error", 1, 1 },
|
|
{ "c_pcmd_par_error", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_mps_regs[] = {
|
|
{ "MPS_CMN_CTL", 0x9000, 0 },
|
|
{ "LpbkCrdtCtrl", 4, 1 },
|
|
{ "Detect8023", 3, 1 },
|
|
{ "VFDirectAccess", 2, 1 },
|
|
{ "NumPorts", 0, 2 },
|
|
{ "MPS_INT_ENABLE", 0x9004, 0 },
|
|
{ "StatIntEnb", 5, 1 },
|
|
{ "TxIntEnb", 4, 1 },
|
|
{ "RxIntEnb", 3, 1 },
|
|
{ "TrcIntEnb", 2, 1 },
|
|
{ "ClsIntEnb", 1, 1 },
|
|
{ "PLIntEnb", 0, 1 },
|
|
{ "MPS_INT_CAUSE", 0x9008, 0 },
|
|
{ "StatInt", 5, 1 },
|
|
{ "TxInt", 4, 1 },
|
|
{ "RxInt", 3, 1 },
|
|
{ "TrcInt", 2, 1 },
|
|
{ "ClsInt", 1, 1 },
|
|
{ "PLInt", 0, 1 },
|
|
{ "MPS_CGEN_GLOBAL", 0x900c, 0 },
|
|
{ "MPS_VF_TX_CTL_31_0", 0x9010, 0 },
|
|
{ "MPS_VF_TX_CTL_63_32", 0x9014, 0 },
|
|
{ "MPS_VF_TX_CTL_95_64", 0x9018, 0 },
|
|
{ "MPS_VF_TX_CTL_127_96", 0x901c, 0 },
|
|
{ "MPS_VF_RX_CTL_31_0", 0x9020, 0 },
|
|
{ "MPS_VF_RX_CTL_63_32", 0x9024, 0 },
|
|
{ "MPS_VF_RX_CTL_95_64", 0x9028, 0 },
|
|
{ "MPS_VF_RX_CTL_127_96", 0x902c, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP0", 0x9030, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP1", 0x9034, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP2", 0x9038, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP3", 0x903c, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP0", 0x9040, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP1", 0x9044, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP2", 0x9048, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP3", 0x904c, 0 },
|
|
{ "MPS_TP_CSIDE_MUX_CTL_P0", 0x9050, 0 },
|
|
{ "MPS_TP_CSIDE_MUX_CTL_P1", 0x9054, 0 },
|
|
{ "MPS_WOL_CTL_MODE", 0x9058, 0 },
|
|
{ "MPS_FPGA_DEBUG", 0x9060, 0 },
|
|
{ "FPGA_PTP_PORT", 9, 2 },
|
|
{ "LPBK_EN", 8, 1 },
|
|
{ "CH_MAP3", 6, 2 },
|
|
{ "CH_MAP2", 4, 2 },
|
|
{ "CH_MAP1", 2, 2 },
|
|
{ "CH_MAP0", 0, 2 },
|
|
{ "MPS_DEBUG_CTL", 0x9068, 0 },
|
|
{ "DbgModeCtl_H", 11, 1 },
|
|
{ "DbgSel_H", 6, 5 },
|
|
{ "DbgModeCtl_L", 5, 1 },
|
|
{ "DbgSel_L", 0, 5 },
|
|
{ "MPS_DEBUG_DATA_REG_L", 0x906c, 0 },
|
|
{ "MPS_DEBUG_DATA_REG_H", 0x9070, 0 },
|
|
{ "MPS_TOP_SPARE", 0x9074, 0 },
|
|
{ "TopSpare", 8, 24 },
|
|
{ "oVlanSelLpbk3", 7, 1 },
|
|
{ "oVlanSelLpbk2", 6, 1 },
|
|
{ "oVlanSelLpbk1", 5, 1 },
|
|
{ "oVlanSelLpbk0", 4, 1 },
|
|
{ "oVlanSelMac3", 3, 1 },
|
|
{ "oVlanSelMac2", 2, 1 },
|
|
{ "oVlanSelMac1", 1, 1 },
|
|
{ "oVlanSelMac0", 0, 1 },
|
|
{ "MPS_BUILD_REVISION", 0x9078, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH0", 0x907c, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH1", 0x9080, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH2", 0x9084, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH3", 0x9088, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH4", 0x908c, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH5", 0x9090, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH6", 0x9094, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH7", 0x9098, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH8", 0x909c, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH9", 0x90a0, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH10", 0x90a4, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH11", 0x90a8, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH12", 0x90ac, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH13", 0x90b0, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH14", 0x90b4, 0 },
|
|
{ "MPS_TX_PAUSE_DURATION_BUF_GRP_TH15", 0x90b8, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH0", 0x90bc, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH1", 0x90c0, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH2", 0x90c4, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH3", 0x90c8, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH4", 0x90cc, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH5", 0x90d0, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH6", 0x90d4, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH7", 0x90d8, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH8", 0x90dc, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH9", 0x90e0, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH10", 0x90e4, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH11", 0x90e8, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH12", 0x90ec, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH13", 0x90f0, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14", 0x90f4, 0 },
|
|
{ "MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15", 0x90f8, 0 },
|
|
{ "MPS_PORT_CTL", 0x30000, 0 },
|
|
{ "LpbkEn", 31, 1 },
|
|
{ "TxEn", 30, 1 },
|
|
{ "RxEn", 29, 1 },
|
|
{ "PPPEn", 28, 1 },
|
|
{ "FCSStripEn", 27, 1 },
|
|
{ "PPPAndPause", 26, 1 },
|
|
{ "PrioPPPEnMap", 16, 8 },
|
|
{ "MPS_PORT_PAUSE_CTL", 0x30004, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL", 0x30008, 0 },
|
|
{ "RegSendOff", 24, 8 },
|
|
{ "RegSendOn", 16, 8 },
|
|
{ "SgeSendEn", 8, 8 },
|
|
{ "RxSendEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL2", 0x3000c, 0 },
|
|
{ "MPS_PORT_RX_PAUSE_CTL", 0x30010, 0 },
|
|
{ "RegHaltOn", 8, 8 },
|
|
{ "RxHaltEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_STATUS", 0x30014, 0 },
|
|
{ "RegSending", 16, 8 },
|
|
{ "SgeSending", 8, 8 },
|
|
{ "RxSending", 0, 8 },
|
|
{ "MPS_PORT_RX_PAUSE_STATUS", 0x30018, 0 },
|
|
{ "RegHalted", 8, 8 },
|
|
{ "RxHalted", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_L", 0x3001c, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_H", 0x30020, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_L", 0x30024, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_H", 0x30028, 0 },
|
|
{ "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3002c, 0 },
|
|
{ "Prty7", 14, 2 },
|
|
{ "Prty6", 12, 2 },
|
|
{ "Prty5", 10, 2 },
|
|
{ "Prty4", 8, 2 },
|
|
{ "Prty3", 6, 2 },
|
|
{ "Prty2", 4, 2 },
|
|
{ "Prty1", 2, 2 },
|
|
{ "Prty0", 0, 2 },
|
|
{ "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x30030, 0 },
|
|
{ "Prty7", 28, 4 },
|
|
{ "Prty6", 24, 4 },
|
|
{ "Prty5", 20, 4 },
|
|
{ "Prty4", 16, 4 },
|
|
{ "Prty3", 12, 4 },
|
|
{ "Prty2", 8, 4 },
|
|
{ "Prty1", 4, 4 },
|
|
{ "Prty0", 0, 4 },
|
|
{ "MPS_PORT_CTL", 0x34000, 0 },
|
|
{ "LpbkEn", 31, 1 },
|
|
{ "TxEn", 30, 1 },
|
|
{ "RxEn", 29, 1 },
|
|
{ "PPPEn", 28, 1 },
|
|
{ "FCSStripEn", 27, 1 },
|
|
{ "PPPAndPause", 26, 1 },
|
|
{ "PrioPPPEnMap", 16, 8 },
|
|
{ "MPS_PORT_PAUSE_CTL", 0x34004, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL", 0x34008, 0 },
|
|
{ "RegSendOff", 24, 8 },
|
|
{ "RegSendOn", 16, 8 },
|
|
{ "SgeSendEn", 8, 8 },
|
|
{ "RxSendEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL2", 0x3400c, 0 },
|
|
{ "MPS_PORT_RX_PAUSE_CTL", 0x34010, 0 },
|
|
{ "RegHaltOn", 8, 8 },
|
|
{ "RxHaltEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_STATUS", 0x34014, 0 },
|
|
{ "RegSending", 16, 8 },
|
|
{ "SgeSending", 8, 8 },
|
|
{ "RxSending", 0, 8 },
|
|
{ "MPS_PORT_RX_PAUSE_STATUS", 0x34018, 0 },
|
|
{ "RegHalted", 8, 8 },
|
|
{ "RxHalted", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_L", 0x3401c, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_H", 0x34020, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_L", 0x34024, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_H", 0x34028, 0 },
|
|
{ "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3402c, 0 },
|
|
{ "Prty7", 14, 2 },
|
|
{ "Prty6", 12, 2 },
|
|
{ "Prty5", 10, 2 },
|
|
{ "Prty4", 8, 2 },
|
|
{ "Prty3", 6, 2 },
|
|
{ "Prty2", 4, 2 },
|
|
{ "Prty1", 2, 2 },
|
|
{ "Prty0", 0, 2 },
|
|
{ "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x34030, 0 },
|
|
{ "Prty7", 28, 4 },
|
|
{ "Prty6", 24, 4 },
|
|
{ "Prty5", 20, 4 },
|
|
{ "Prty4", 16, 4 },
|
|
{ "Prty3", 12, 4 },
|
|
{ "Prty2", 8, 4 },
|
|
{ "Prty1", 4, 4 },
|
|
{ "Prty0", 0, 4 },
|
|
{ "MPS_PORT_CTL", 0x38000, 0 },
|
|
{ "LpbkEn", 31, 1 },
|
|
{ "TxEn", 30, 1 },
|
|
{ "RxEn", 29, 1 },
|
|
{ "PPPEn", 28, 1 },
|
|
{ "FCSStripEn", 27, 1 },
|
|
{ "PPPAndPause", 26, 1 },
|
|
{ "PrioPPPEnMap", 16, 8 },
|
|
{ "MPS_PORT_PAUSE_CTL", 0x38004, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL", 0x38008, 0 },
|
|
{ "RegSendOff", 24, 8 },
|
|
{ "RegSendOn", 16, 8 },
|
|
{ "SgeSendEn", 8, 8 },
|
|
{ "RxSendEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL2", 0x3800c, 0 },
|
|
{ "MPS_PORT_RX_PAUSE_CTL", 0x38010, 0 },
|
|
{ "RegHaltOn", 8, 8 },
|
|
{ "RxHaltEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_STATUS", 0x38014, 0 },
|
|
{ "RegSending", 16, 8 },
|
|
{ "SgeSending", 8, 8 },
|
|
{ "RxSending", 0, 8 },
|
|
{ "MPS_PORT_RX_PAUSE_STATUS", 0x38018, 0 },
|
|
{ "RegHalted", 8, 8 },
|
|
{ "RxHalted", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_L", 0x3801c, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_H", 0x38020, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_L", 0x38024, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_H", 0x38028, 0 },
|
|
{ "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3802c, 0 },
|
|
{ "Prty7", 14, 2 },
|
|
{ "Prty6", 12, 2 },
|
|
{ "Prty5", 10, 2 },
|
|
{ "Prty4", 8, 2 },
|
|
{ "Prty3", 6, 2 },
|
|
{ "Prty2", 4, 2 },
|
|
{ "Prty1", 2, 2 },
|
|
{ "Prty0", 0, 2 },
|
|
{ "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x38030, 0 },
|
|
{ "Prty7", 28, 4 },
|
|
{ "Prty6", 24, 4 },
|
|
{ "Prty5", 20, 4 },
|
|
{ "Prty4", 16, 4 },
|
|
{ "Prty3", 12, 4 },
|
|
{ "Prty2", 8, 4 },
|
|
{ "Prty1", 4, 4 },
|
|
{ "Prty0", 0, 4 },
|
|
{ "MPS_PORT_CTL", 0x3c000, 0 },
|
|
{ "LpbkEn", 31, 1 },
|
|
{ "TxEn", 30, 1 },
|
|
{ "RxEn", 29, 1 },
|
|
{ "PPPEn", 28, 1 },
|
|
{ "FCSStripEn", 27, 1 },
|
|
{ "PPPAndPause", 26, 1 },
|
|
{ "PrioPPPEnMap", 16, 8 },
|
|
{ "MPS_PORT_PAUSE_CTL", 0x3c004, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL", 0x3c008, 0 },
|
|
{ "RegSendOff", 24, 8 },
|
|
{ "RegSendOn", 16, 8 },
|
|
{ "SgeSendEn", 8, 8 },
|
|
{ "RxSendEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_CTL2", 0x3c00c, 0 },
|
|
{ "MPS_PORT_RX_PAUSE_CTL", 0x3c010, 0 },
|
|
{ "RegHaltOn", 8, 8 },
|
|
{ "RxHaltEn", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_STATUS", 0x3c014, 0 },
|
|
{ "RegSending", 16, 8 },
|
|
{ "SgeSending", 8, 8 },
|
|
{ "RxSending", 0, 8 },
|
|
{ "MPS_PORT_RX_PAUSE_STATUS", 0x3c018, 0 },
|
|
{ "RegHalted", 8, 8 },
|
|
{ "RxHalted", 0, 8 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_L", 0x3c01c, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_DEST_H", 0x3c020, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_L", 0x3c024, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_SOURCE_H", 0x3c028, 0 },
|
|
{ "MPS_PORT_PRTY_BUFFER_GROUP_MAP", 0x3c02c, 0 },
|
|
{ "Prty7", 14, 2 },
|
|
{ "Prty6", 12, 2 },
|
|
{ "Prty5", 10, 2 },
|
|
{ "Prty4", 8, 2 },
|
|
{ "Prty3", 6, 2 },
|
|
{ "Prty2", 4, 2 },
|
|
{ "Prty1", 2, 2 },
|
|
{ "Prty0", 0, 2 },
|
|
{ "MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP", 0x3c030, 0 },
|
|
{ "Prty7", 28, 4 },
|
|
{ "Prty6", 24, 4 },
|
|
{ "Prty5", 20, 4 },
|
|
{ "Prty4", 16, 4 },
|
|
{ "Prty3", 12, 4 },
|
|
{ "Prty2", 8, 4 },
|
|
{ "Prty1", 4, 4 },
|
|
{ "Prty0", 0, 4 },
|
|
{ "MPS_PF_CTL", 0x1e2c0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1e6c0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1eac0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1eec0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1f2c0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1f6c0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1fac0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_PF_CTL", 0x1fec0, 0 },
|
|
{ "TxEn", 1, 1 },
|
|
{ "RxEn", 0, 1 },
|
|
{ "MPS_RX_CTL", 0x11000, 0 },
|
|
{ "FILT_VLAN_SEL", 17, 1 },
|
|
{ "CBA_EN", 16, 1 },
|
|
{ "BLK_SNDR", 12, 4 },
|
|
{ "CMPRS", 8, 4 },
|
|
{ "SNF", 0, 8 },
|
|
{ "MPS_RX_PORT_MUX_CTL", 0x11004, 0 },
|
|
{ "CTL_P3", 12, 4 },
|
|
{ "CTL_P2", 8, 4 },
|
|
{ "CTL_P1", 4, 4 },
|
|
{ "CTL_P0", 0, 4 },
|
|
{ "MPS_RX_PG_FL", 0x11008, 0 },
|
|
{ "RST", 16, 1 },
|
|
{ "CNT", 0, 16 },
|
|
{ "MPS_RX_PKT_FL", 0x1100c, 0 },
|
|
{ "RST", 16, 1 },
|
|
{ "CNT", 0, 16 },
|
|
{ "MPS_RX_PG_RSV0", 0x11010, 0 },
|
|
{ "CLR_INTR", 31, 1 },
|
|
{ "SET_INTR", 30, 1 },
|
|
{ "USED", 16, 12 },
|
|
{ "ALLOC", 0, 12 },
|
|
{ "MPS_RX_PG_RSV1", 0x11014, 0 },
|
|
{ "CLR_INTR", 31, 1 },
|
|
{ "SET_INTR", 30, 1 },
|
|
{ "USED", 16, 12 },
|
|
{ "ALLOC", 0, 12 },
|
|
{ "MPS_RX_PG_RSV2", 0x11018, 0 },
|
|
{ "CLR_INTR", 31, 1 },
|
|
{ "SET_INTR", 30, 1 },
|
|
{ "USED", 16, 12 },
|
|
{ "ALLOC", 0, 12 },
|
|
{ "MPS_RX_PG_RSV3", 0x1101c, 0 },
|
|
{ "CLR_INTR", 31, 1 },
|
|
{ "SET_INTR", 30, 1 },
|
|
{ "USED", 16, 12 },
|
|
{ "ALLOC", 0, 12 },
|
|
{ "MPS_RX_PG_RSV4", 0x11020, 0 },
|
|
{ "CLR_INTR", 31, 1 },
|
|
{ "SET_INTR", 30, 1 },
|
|
{ "USED", 16, 12 },
|
|
{ "ALLOC", 0, 12 },
|
|
{ "MPS_RX_PG_RSV5", 0x11024, 0 },
|
|
{ "CLR_INTR", 31, 1 },
|
|
{ "SET_INTR", 30, 1 },
|
|
{ "USED", 16, 12 },
|
|
{ "ALLOC", 0, 12 },
|
|
{ "MPS_RX_PG_RSV6", 0x11028, 0 },
|
|
{ "CLR_INTR", 31, 1 },
|
|
{ "SET_INTR", 30, 1 },
|
|
{ "USED", 16, 12 },
|
|
{ "ALLOC", 0, 12 },
|
|
{ "MPS_RX_PG_RSV7", 0x1102c, 0 },
|
|
{ "CLR_INTR", 31, 1 },
|
|
{ "SET_INTR", 30, 1 },
|
|
{ "USED", 16, 12 },
|
|
{ "ALLOC", 0, 12 },
|
|
{ "MPS_RX_PG_SHR_BG0", 0x11030, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "SEL", 30, 1 },
|
|
{ "MAX", 16, 12 },
|
|
{ "BORW", 0, 12 },
|
|
{ "MPS_RX_PG_SHR_BG1", 0x11034, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "SEL", 30, 1 },
|
|
{ "MAX", 16, 12 },
|
|
{ "BORW", 0, 12 },
|
|
{ "MPS_RX_PG_SHR_BG2", 0x11038, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "SEL", 30, 1 },
|
|
{ "MAX", 16, 12 },
|
|
{ "BORW", 0, 12 },
|
|
{ "MPS_RX_PG_SHR_BG3", 0x1103c, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "SEL", 30, 1 },
|
|
{ "MAX", 16, 12 },
|
|
{ "BORW", 0, 12 },
|
|
{ "MPS_RX_PG_SHR0", 0x11040, 0 },
|
|
{ "QUOTA", 16, 12 },
|
|
{ "USED", 0, 12 },
|
|
{ "MPS_RX_PG_SHR1", 0x11044, 0 },
|
|
{ "QUOTA", 16, 12 },
|
|
{ "USED", 0, 12 },
|
|
{ "MPS_RX_PG_HYST_BG0", 0x11048, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "TH", 0, 12 },
|
|
{ "MPS_RX_PG_HYST_BG1", 0x1104c, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "TH", 0, 12 },
|
|
{ "MPS_RX_PG_HYST_BG2", 0x11050, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "TH", 0, 12 },
|
|
{ "MPS_RX_PG_HYST_BG3", 0x11054, 0 },
|
|
{ "EN", 31, 1 },
|
|
{ "TH", 0, 12 },
|
|
{ "MPS_RX_OCH_CTL", 0x11058, 0 },
|
|
{ "DROP_WT", 27, 5 },
|
|
{ "TRUNC_WT", 22, 5 },
|
|
{ "DRAIN", 13, 5 },
|
|
{ "DROP", 8, 5 },
|
|
{ "STOP", 0, 5 },
|
|
{ "MPS_RX_LPBK_BP0", 0x1105c, 0 },
|
|
{ "MPS_RX_LPBK_BP1", 0x11060, 0 },
|
|
{ "MPS_RX_LPBK_BP2", 0x11064, 0 },
|
|
{ "MPS_RX_LPBK_BP3", 0x11068, 0 },
|
|
{ "MPS_RX_PORT_GAP", 0x1106c, 0 },
|
|
{ "MPS_RX_PERR_INT_CAUSE", 0x11074, 0 },
|
|
{ "FF", 23, 1 },
|
|
{ "PGMO", 22, 1 },
|
|
{ "PGME", 21, 1 },
|
|
{ "CHMN", 20, 1 },
|
|
{ "RPLC", 19, 1 },
|
|
{ "ATRB", 18, 1 },
|
|
{ "PSMX", 17, 1 },
|
|
{ "PGLL", 16, 1 },
|
|
{ "PGFL", 15, 1 },
|
|
{ "PKTQ", 14, 1 },
|
|
{ "PKFL", 13, 1 },
|
|
{ "PPM3", 12, 1 },
|
|
{ "PPM2", 11, 1 },
|
|
{ "PPM1", 10, 1 },
|
|
{ "PPM0", 9, 1 },
|
|
{ "SPMX", 8, 1 },
|
|
{ "CDL3", 7, 1 },
|
|
{ "CDL2", 6, 1 },
|
|
{ "CDL1", 5, 1 },
|
|
{ "CDL0", 4, 1 },
|
|
{ "CDM3", 3, 1 },
|
|
{ "CDM2", 2, 1 },
|
|
{ "CDM1", 1, 1 },
|
|
{ "CDM0", 0, 1 },
|
|
{ "MPS_RX_PERR_INT_ENABLE", 0x11078, 0 },
|
|
{ "FF", 23, 1 },
|
|
{ "PGMO", 22, 1 },
|
|
{ "PGME", 21, 1 },
|
|
{ "CHMN", 20, 1 },
|
|
{ "RPLC", 19, 1 },
|
|
{ "ATRB", 18, 1 },
|
|
{ "PSMX", 17, 1 },
|
|
{ "PGLL", 16, 1 },
|
|
{ "PGFL", 15, 1 },
|
|
{ "PKTQ", 14, 1 },
|
|
{ "PKFL", 13, 1 },
|
|
{ "PPM3", 12, 1 },
|
|
{ "PPM2", 11, 1 },
|
|
{ "PPM1", 10, 1 },
|
|
{ "PPM0", 9, 1 },
|
|
{ "SPMX", 8, 1 },
|
|
{ "CDL3", 7, 1 },
|
|
{ "CDL2", 6, 1 },
|
|
{ "CDL1", 5, 1 },
|
|
{ "CDL0", 4, 1 },
|
|
{ "CDM3", 3, 1 },
|
|
{ "CDM2", 2, 1 },
|
|
{ "CDM1", 1, 1 },
|
|
{ "CDM0", 0, 1 },
|
|
{ "MPS_RX_PERR_ENABLE", 0x1107c, 0 },
|
|
{ "FF", 23, 1 },
|
|
{ "PGMO", 22, 1 },
|
|
{ "PGME", 21, 1 },
|
|
{ "CHMN", 20, 1 },
|
|
{ "RPLC", 19, 1 },
|
|
{ "ATRB", 18, 1 },
|
|
{ "PSMX", 17, 1 },
|
|
{ "PGLL", 16, 1 },
|
|
{ "PGFL", 15, 1 },
|
|
{ "PKTQ", 14, 1 },
|
|
{ "PKFL", 13, 1 },
|
|
{ "PPM3", 12, 1 },
|
|
{ "PPM2", 11, 1 },
|
|
{ "PPM1", 10, 1 },
|
|
{ "PPM0", 9, 1 },
|
|
{ "SPMX", 8, 1 },
|
|
{ "CDL3", 7, 1 },
|
|
{ "CDL2", 6, 1 },
|
|
{ "CDL1", 5, 1 },
|
|
{ "CDL0", 4, 1 },
|
|
{ "CDM3", 3, 1 },
|
|
{ "CDM2", 2, 1 },
|
|
{ "CDM1", 1, 1 },
|
|
{ "CDM0", 0, 1 },
|
|
{ "MPS_RX_PERR_INJECT", 0x11080, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MPS_RX_FUNC_INT_CAUSE", 0x11084, 0 },
|
|
{ "MTU_ERR_INT3", 19, 1 },
|
|
{ "MTU_ERR_INT2", 18, 1 },
|
|
{ "MTU_ERR_INT1", 17, 1 },
|
|
{ "MTU_ERR_INT0", 16, 1 },
|
|
{ "SE_CNT_ERR_INT", 15, 1 },
|
|
{ "FRM_ERR_INT", 14, 1 },
|
|
{ "LEN_ERR_INT", 13, 1 },
|
|
{ "INT_ERR_INT", 8, 5 },
|
|
{ "PG_TH_INT7", 7, 1 },
|
|
{ "PG_TH_INT6", 6, 1 },
|
|
{ "PG_TH_INT5", 5, 1 },
|
|
{ "PG_TH_INT4", 4, 1 },
|
|
{ "PG_TH_INT3", 3, 1 },
|
|
{ "PG_TH_INT2", 2, 1 },
|
|
{ "PG_TH_INT1", 1, 1 },
|
|
{ "PG_TH_INT0", 0, 1 },
|
|
{ "MPS_RX_FUNC_INT_ENABLE", 0x11088, 0 },
|
|
{ "MTU_ERR_INT3", 19, 1 },
|
|
{ "MTU_ERR_INT2", 18, 1 },
|
|
{ "MTU_ERR_INT1", 17, 1 },
|
|
{ "MTU_ERR_INT0", 16, 1 },
|
|
{ "SE_CNT_ERR_INT", 15, 1 },
|
|
{ "FRM_ERR_INT", 14, 1 },
|
|
{ "LEN_ERR_INT", 13, 1 },
|
|
{ "INT_ERR_INT", 8, 5 },
|
|
{ "PG_TH_INT7", 7, 1 },
|
|
{ "PG_TH_INT6", 6, 1 },
|
|
{ "PG_TH_INT5", 5, 1 },
|
|
{ "PG_TH_INT4", 4, 1 },
|
|
{ "PG_TH_INT3", 3, 1 },
|
|
{ "PG_TH_INT2", 2, 1 },
|
|
{ "PG_TH_INT1", 1, 1 },
|
|
{ "PG_TH_INT0", 0, 1 },
|
|
{ "MPS_RX_PPP_ATRB", 0x1109c, 0 },
|
|
{ "ETYPE", 16, 16 },
|
|
{ "OPCODE", 0, 16 },
|
|
{ "MPS_RX_QFC0_ATRB", 0x110a0, 0 },
|
|
{ "ETYPE", 16, 16 },
|
|
{ "DA", 0, 16 },
|
|
{ "MPS_RX_QFC1_ATRB", 0x110a4, 0 },
|
|
{ "MPS_RX_PT_ARB0", 0x110a8, 0 },
|
|
{ "LPBK_WT", 16, 14 },
|
|
{ "MAC_WT", 0, 14 },
|
|
{ "MPS_RX_PT_ARB1", 0x110ac, 0 },
|
|
{ "LPBK_WT", 16, 14 },
|
|
{ "MAC_WT", 0, 14 },
|
|
{ "MPS_RX_PT_ARB2", 0x110b0, 0 },
|
|
{ "LPBK_WT", 16, 14 },
|
|
{ "MAC_WT", 0, 14 },
|
|
{ "MPS_RX_PT_ARB3", 0x110b4, 0 },
|
|
{ "LPBK_WT", 16, 14 },
|
|
{ "MAC_WT", 0, 14 },
|
|
{ "MPS_RX_PT_ARB4", 0x110b8, 0 },
|
|
{ "LPBK_WT", 16, 14 },
|
|
{ "MAC_WT", 0, 14 },
|
|
{ "MPS_PF_OUT_EN", 0x110bc, 0 },
|
|
{ "MPS_BMC_MTU", 0x110c0, 0 },
|
|
{ "MPS_BMC_PKT_CNT", 0x110c4, 0 },
|
|
{ "MPS_BMC_BYTE_CNT", 0x110c8, 0 },
|
|
{ "MPS_PFVF_ATRB_CTL", 0x110cc, 0 },
|
|
{ "RD_WRN", 31, 1 },
|
|
{ "PFVF", 0, 8 },
|
|
{ "MPS_PFVF_ATRB", 0x110d0, 0 },
|
|
{ "PF", 28, 3 },
|
|
{ "OFF", 18, 1 },
|
|
{ "NV_DROP", 17, 1 },
|
|
{ "MODE", 16, 1 },
|
|
{ "MTU", 0, 14 },
|
|
{ "MPS_PFVF_ATRB_FLTR0", 0x110d4, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR1", 0x110d8, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR2", 0x110dc, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR3", 0x110e0, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR4", 0x110e4, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR5", 0x110e8, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR6", 0x110ec, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR7", 0x110f0, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR8", 0x110f4, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR9", 0x110f8, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR10", 0x110fc, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR11", 0x11100, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR12", 0x11104, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR13", 0x11108, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR14", 0x1110c, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PFVF_ATRB_FLTR15", 0x11110, 0 },
|
|
{ "VLAN_EN", 16, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_RPLC_MAP_CTL", 0x11114, 0 },
|
|
{ "RD_WRN", 31, 1 },
|
|
{ "ADDR", 0, 10 },
|
|
{ "MPS_PF_RPLCT_MAP", 0x11118, 0 },
|
|
{ "MPS_VF_RPLCT_MAP0", 0x1111c, 0 },
|
|
{ "MPS_VF_RPLCT_MAP1", 0x11120, 0 },
|
|
{ "MPS_VF_RPLCT_MAP2", 0x11124, 0 },
|
|
{ "MPS_VF_RPLCT_MAP3", 0x11128, 0 },
|
|
{ "MPS_MEM_DBG_CTL", 0x1112c, 0 },
|
|
{ "PKD", 17, 1 },
|
|
{ "PGD", 16, 1 },
|
|
{ "ADDR", 0, 16 },
|
|
{ "MPS_PKD_MEM_DATA0", 0x11130, 0 },
|
|
{ "MPS_PKD_MEM_DATA1", 0x11134, 0 },
|
|
{ "MPS_PKD_MEM_DATA2", 0x11138, 0 },
|
|
{ "MPS_PGD_MEM_DATA", 0x1113c, 0 },
|
|
{ "MPS_RX_SE_CNT_ERR", 0x11140, 0 },
|
|
{ "MPS_RX_SE_CNT_CLR", 0x11144, 0 },
|
|
{ "MPS_RX_SE_CNT_IN0", 0x11148, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN1", 0x1114c, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN2", 0x11150, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN3", 0x11154, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN4", 0x11158, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN5", 0x1115c, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN6", 0x11160, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_IN7", 0x11164, 0 },
|
|
{ "SOP_CNT_PM", 24, 8 },
|
|
{ "EOP_CNT_PM", 16, 8 },
|
|
{ "SOP_CNT_IN", 8, 8 },
|
|
{ "EOP_CNT_IN", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_OUT01", 0x11168, 0 },
|
|
{ "SOP_CNT_1", 24, 8 },
|
|
{ "EOP_CNT_1", 16, 8 },
|
|
{ "SOP_CNT_0", 8, 8 },
|
|
{ "EOP_CNT_0", 0, 8 },
|
|
{ "MPS_RX_SE_CNT_OUT23", 0x1116c, 0 },
|
|
{ "SOP_CNT_3", 24, 8 },
|
|
{ "EOP_CNT_3", 16, 8 },
|
|
{ "SOP_CNT_2", 8, 8 },
|
|
{ "EOP_CNT_2", 0, 8 },
|
|
{ "MPS_RX_SPI_ERR", 0x11170, 0 },
|
|
{ "LEN_ERR", 21, 4 },
|
|
{ "ERR", 0, 21 },
|
|
{ "MPS_RX_IN_BUS_STATE", 0x11174, 0 },
|
|
{ "ST3", 24, 8 },
|
|
{ "ST2", 16, 8 },
|
|
{ "ST1", 8, 8 },
|
|
{ "ST0", 0, 8 },
|
|
{ "MPS_RX_OUT_BUS_STATE", 0x11178, 0 },
|
|
{ "ST_NCSI", 23, 9 },
|
|
{ "ST_TP", 0, 23 },
|
|
{ "MPS_RX_DBG_CTL", 0x1117c, 0 },
|
|
{ "OUT_DBG_CHNL", 8, 3 },
|
|
{ "DBG_PKD_QSEL", 7, 1 },
|
|
{ "DBG_CDS_INV", 6, 1 },
|
|
{ "IN_DBG_PORT", 3, 3 },
|
|
{ "IN_DBG_CHNL", 0, 3 },
|
|
{ "MPS_RX_SPARE", 0x11190, 0 },
|
|
{ "MPS_RX_PTP_ETYPE", 0x11194, 0 },
|
|
{ "PETYPE2", 16, 16 },
|
|
{ "PETYPE1", 0, 16 },
|
|
{ "MPS_RX_PTP_TCP", 0x11198, 0 },
|
|
{ "PTCPORT2", 16, 16 },
|
|
{ "PTCPORT1", 0, 16 },
|
|
{ "MPS_RX_PTP_UDP", 0x1119c, 0 },
|
|
{ "PUDPORT2", 16, 16 },
|
|
{ "PUDPORT1", 0, 16 },
|
|
{ "MPS_RX_PTP_CTL", 0x111a0, 0 },
|
|
{ "MIN_PTP_SPACE", 24, 7 },
|
|
{ "PUDP2EN", 20, 4 },
|
|
{ "PUDP1EN", 16, 4 },
|
|
{ "PTCP2EN", 12, 4 },
|
|
{ "PTCP1EN", 8, 4 },
|
|
{ "PETYPE2EN", 4, 4 },
|
|
{ "PETYPE1EN", 0, 4 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_0_0", 0x111a4, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_0_1", 0x111a8, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_0_2", 0x111ac, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_0_3", 0x111b0, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_1_0", 0x111b4, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_1_1", 0x111b8, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_1_2", 0x111bc, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_1_3", 0x111c0, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_2_0", 0x111c4, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_2_1", 0x111c8, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_2_2", 0x111cc, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_2_3", 0x111d0, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_3_0", 0x111d4, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_3_1", 0x111d8, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_3_2", 0x111dc, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_PAUSE_GEN_TH_3_3", 0x111e0, 0 },
|
|
{ "TH_HIGH", 16, 16 },
|
|
{ "TH_LOW", 0, 16 },
|
|
{ "MPS_RX_MAC_CLS_DROP_CNT0", 0x111e4, 0 },
|
|
{ "MPS_RX_MAC_CLS_DROP_CNT1", 0x111e8, 0 },
|
|
{ "MPS_RX_MAC_CLS_DROP_CNT2", 0x111ec, 0 },
|
|
{ "MPS_RX_MAC_CLS_DROP_CNT3", 0x111f0, 0 },
|
|
{ "MPS_RX_LPBK_CLS_DROP_CNT0", 0x111f4, 0 },
|
|
{ "MPS_RX_LPBK_CLS_DROP_CNT1", 0x111f8, 0 },
|
|
{ "MPS_RX_LPBK_CLS_DROP_CNT2", 0x111fc, 0 },
|
|
{ "MPS_RX_LPBK_CLS_DROP_CNT3", 0x11200, 0 },
|
|
{ "MPS_RX_CGEN", 0x11204, 0 },
|
|
{ "MPS_RX_CGEN_NCSI", 12, 1 },
|
|
{ "MPS_RX_CGEN_OUT", 8, 4 },
|
|
{ "MPS_RX_CGEN_LPBK_IN", 4, 4 },
|
|
{ "MPS_RX_CGEN_MAC_IN", 0, 4 },
|
|
{ "MPS_PORT_RX_CTL", 0x30100, 0 },
|
|
{ "PTP_FWD_UP", 21, 1 },
|
|
{ "NO_RPLCT_M", 20, 1 },
|
|
{ "RPLCT_SEL_L", 18, 2 },
|
|
{ "FLTR_VLAN_SEL", 17, 1 },
|
|
{ "PRIO_VLAN_SEL", 16, 1 },
|
|
{ "CHK_8023_LEN_M", 15, 1 },
|
|
{ "CHK_8023_LEN_L", 14, 1 },
|
|
{ "NIV_DROP", 13, 1 },
|
|
{ "NOV_DROP", 12, 1 },
|
|
{ "CLS_PRT", 11, 1 },
|
|
{ "RX_QFC_EN", 10, 1 },
|
|
{ "QFC_FWD_UP", 9, 1 },
|
|
{ "PPP_FWD_UP", 8, 1 },
|
|
{ "PAUSE_FWD_UP", 7, 1 },
|
|
{ "LPBK_BP", 6, 1 },
|
|
{ "PASS_NO_MATCH", 5, 1 },
|
|
{ "IVLAN_EN", 4, 1 },
|
|
{ "OVLAN_EN3", 3, 1 },
|
|
{ "OVLAN_EN2", 2, 1 },
|
|
{ "OVLAN_EN1", 1, 1 },
|
|
{ "OVLAN_EN0", 0, 1 },
|
|
{ "MPS_PORT_RX_MTU", 0x30104, 0 },
|
|
{ "MPS_PORT_RX_PF_MAP", 0x30108, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP0", 0x3010c, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP1", 0x30110, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP2", 0x30114, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP3", 0x30118, 0 },
|
|
{ "MPS_PORT_RX_IVLAN", 0x3011c, 0 },
|
|
{ "MPS_PORT_RX_OVLAN0", 0x30120, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN1", 0x30124, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN2", 0x30128, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN3", 0x3012c, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_RSS_HASH", 0x30130, 0 },
|
|
{ "MPS_PORT_RX_RSS_CONTROL", 0x30134, 0 },
|
|
{ "RSS_CTRL", 16, 8 },
|
|
{ "QUE_NUM", 0, 16 },
|
|
{ "MPS_PORT_RX_CTL1", 0x30138, 0 },
|
|
{ "FIXED_PFVF_MAC", 13, 1 },
|
|
{ "FIXED_PFVF_LPBK", 12, 1 },
|
|
{ "FIXED_PFVF_LPBK_OV", 11, 1 },
|
|
{ "FIXED_PF", 8, 3 },
|
|
{ "FIXED_VF_VLD", 7, 1 },
|
|
{ "FIXED_VF", 0, 7 },
|
|
{ "MPS_PORT_RX_SPARE", 0x3013c, 0 },
|
|
{ "MPS_PORT_RX_PTP_RSS_HASH", 0x30140, 0 },
|
|
{ "MPS_PORT_RX_PTP_RSS_CONTROL", 0x30144, 0 },
|
|
{ "RSS_CTRL", 16, 8 },
|
|
{ "QUE_NUM", 0, 16 },
|
|
{ "MPS_PORT_RX_CTL", 0x34100, 0 },
|
|
{ "PTP_FWD_UP", 21, 1 },
|
|
{ "NO_RPLCT_M", 20, 1 },
|
|
{ "RPLCT_SEL_L", 18, 2 },
|
|
{ "FLTR_VLAN_SEL", 17, 1 },
|
|
{ "PRIO_VLAN_SEL", 16, 1 },
|
|
{ "CHK_8023_LEN_M", 15, 1 },
|
|
{ "CHK_8023_LEN_L", 14, 1 },
|
|
{ "NIV_DROP", 13, 1 },
|
|
{ "NOV_DROP", 12, 1 },
|
|
{ "CLS_PRT", 11, 1 },
|
|
{ "RX_QFC_EN", 10, 1 },
|
|
{ "QFC_FWD_UP", 9, 1 },
|
|
{ "PPP_FWD_UP", 8, 1 },
|
|
{ "PAUSE_FWD_UP", 7, 1 },
|
|
{ "LPBK_BP", 6, 1 },
|
|
{ "PASS_NO_MATCH", 5, 1 },
|
|
{ "IVLAN_EN", 4, 1 },
|
|
{ "OVLAN_EN3", 3, 1 },
|
|
{ "OVLAN_EN2", 2, 1 },
|
|
{ "OVLAN_EN1", 1, 1 },
|
|
{ "OVLAN_EN0", 0, 1 },
|
|
{ "MPS_PORT_RX_MTU", 0x34104, 0 },
|
|
{ "MPS_PORT_RX_PF_MAP", 0x34108, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP0", 0x3410c, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP1", 0x34110, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP2", 0x34114, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP3", 0x34118, 0 },
|
|
{ "MPS_PORT_RX_IVLAN", 0x3411c, 0 },
|
|
{ "MPS_PORT_RX_OVLAN0", 0x34120, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN1", 0x34124, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN2", 0x34128, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN3", 0x3412c, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_RSS_HASH", 0x34130, 0 },
|
|
{ "MPS_PORT_RX_RSS_CONTROL", 0x34134, 0 },
|
|
{ "RSS_CTRL", 16, 8 },
|
|
{ "QUE_NUM", 0, 16 },
|
|
{ "MPS_PORT_RX_CTL1", 0x34138, 0 },
|
|
{ "FIXED_PFVF_MAC", 13, 1 },
|
|
{ "FIXED_PFVF_LPBK", 12, 1 },
|
|
{ "FIXED_PFVF_LPBK_OV", 11, 1 },
|
|
{ "FIXED_PF", 8, 3 },
|
|
{ "FIXED_VF_VLD", 7, 1 },
|
|
{ "FIXED_VF", 0, 7 },
|
|
{ "MPS_PORT_RX_SPARE", 0x3413c, 0 },
|
|
{ "MPS_PORT_RX_PTP_RSS_HASH", 0x34140, 0 },
|
|
{ "MPS_PORT_RX_PTP_RSS_CONTROL", 0x34144, 0 },
|
|
{ "RSS_CTRL", 16, 8 },
|
|
{ "QUE_NUM", 0, 16 },
|
|
{ "MPS_PORT_RX_CTL", 0x38100, 0 },
|
|
{ "PTP_FWD_UP", 21, 1 },
|
|
{ "NO_RPLCT_M", 20, 1 },
|
|
{ "RPLCT_SEL_L", 18, 2 },
|
|
{ "FLTR_VLAN_SEL", 17, 1 },
|
|
{ "PRIO_VLAN_SEL", 16, 1 },
|
|
{ "CHK_8023_LEN_M", 15, 1 },
|
|
{ "CHK_8023_LEN_L", 14, 1 },
|
|
{ "NIV_DROP", 13, 1 },
|
|
{ "NOV_DROP", 12, 1 },
|
|
{ "CLS_PRT", 11, 1 },
|
|
{ "RX_QFC_EN", 10, 1 },
|
|
{ "QFC_FWD_UP", 9, 1 },
|
|
{ "PPP_FWD_UP", 8, 1 },
|
|
{ "PAUSE_FWD_UP", 7, 1 },
|
|
{ "LPBK_BP", 6, 1 },
|
|
{ "PASS_NO_MATCH", 5, 1 },
|
|
{ "IVLAN_EN", 4, 1 },
|
|
{ "OVLAN_EN3", 3, 1 },
|
|
{ "OVLAN_EN2", 2, 1 },
|
|
{ "OVLAN_EN1", 1, 1 },
|
|
{ "OVLAN_EN0", 0, 1 },
|
|
{ "MPS_PORT_RX_MTU", 0x38104, 0 },
|
|
{ "MPS_PORT_RX_PF_MAP", 0x38108, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP0", 0x3810c, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP1", 0x38110, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP2", 0x38114, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP3", 0x38118, 0 },
|
|
{ "MPS_PORT_RX_IVLAN", 0x3811c, 0 },
|
|
{ "MPS_PORT_RX_OVLAN0", 0x38120, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN1", 0x38124, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN2", 0x38128, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN3", 0x3812c, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_RSS_HASH", 0x38130, 0 },
|
|
{ "MPS_PORT_RX_RSS_CONTROL", 0x38134, 0 },
|
|
{ "RSS_CTRL", 16, 8 },
|
|
{ "QUE_NUM", 0, 16 },
|
|
{ "MPS_PORT_RX_CTL1", 0x38138, 0 },
|
|
{ "FIXED_PFVF_MAC", 13, 1 },
|
|
{ "FIXED_PFVF_LPBK", 12, 1 },
|
|
{ "FIXED_PFVF_LPBK_OV", 11, 1 },
|
|
{ "FIXED_PF", 8, 3 },
|
|
{ "FIXED_VF_VLD", 7, 1 },
|
|
{ "FIXED_VF", 0, 7 },
|
|
{ "MPS_PORT_RX_SPARE", 0x3813c, 0 },
|
|
{ "MPS_PORT_RX_PTP_RSS_HASH", 0x38140, 0 },
|
|
{ "MPS_PORT_RX_PTP_RSS_CONTROL", 0x38144, 0 },
|
|
{ "RSS_CTRL", 16, 8 },
|
|
{ "QUE_NUM", 0, 16 },
|
|
{ "MPS_PORT_RX_CTL", 0x3c100, 0 },
|
|
{ "PTP_FWD_UP", 21, 1 },
|
|
{ "NO_RPLCT_M", 20, 1 },
|
|
{ "RPLCT_SEL_L", 18, 2 },
|
|
{ "FLTR_VLAN_SEL", 17, 1 },
|
|
{ "PRIO_VLAN_SEL", 16, 1 },
|
|
{ "CHK_8023_LEN_M", 15, 1 },
|
|
{ "CHK_8023_LEN_L", 14, 1 },
|
|
{ "NIV_DROP", 13, 1 },
|
|
{ "NOV_DROP", 12, 1 },
|
|
{ "CLS_PRT", 11, 1 },
|
|
{ "RX_QFC_EN", 10, 1 },
|
|
{ "QFC_FWD_UP", 9, 1 },
|
|
{ "PPP_FWD_UP", 8, 1 },
|
|
{ "PAUSE_FWD_UP", 7, 1 },
|
|
{ "LPBK_BP", 6, 1 },
|
|
{ "PASS_NO_MATCH", 5, 1 },
|
|
{ "IVLAN_EN", 4, 1 },
|
|
{ "OVLAN_EN3", 3, 1 },
|
|
{ "OVLAN_EN2", 2, 1 },
|
|
{ "OVLAN_EN1", 1, 1 },
|
|
{ "OVLAN_EN0", 0, 1 },
|
|
{ "MPS_PORT_RX_MTU", 0x3c104, 0 },
|
|
{ "MPS_PORT_RX_PF_MAP", 0x3c108, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP0", 0x3c10c, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP1", 0x3c110, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP2", 0x3c114, 0 },
|
|
{ "MPS_PORT_RX_VF_MAP3", 0x3c118, 0 },
|
|
{ "MPS_PORT_RX_IVLAN", 0x3c11c, 0 },
|
|
{ "MPS_PORT_RX_OVLAN0", 0x3c120, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN1", 0x3c124, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN2", 0x3c128, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_OVLAN3", 0x3c12c, 0 },
|
|
{ "OVLAN_MASK", 16, 16 },
|
|
{ "OVLAN_ETYPE", 0, 16 },
|
|
{ "MPS_PORT_RX_RSS_HASH", 0x3c130, 0 },
|
|
{ "MPS_PORT_RX_RSS_CONTROL", 0x3c134, 0 },
|
|
{ "RSS_CTRL", 16, 8 },
|
|
{ "QUE_NUM", 0, 16 },
|
|
{ "MPS_PORT_RX_CTL1", 0x3c138, 0 },
|
|
{ "FIXED_PFVF_MAC", 13, 1 },
|
|
{ "FIXED_PFVF_LPBK", 12, 1 },
|
|
{ "FIXED_PFVF_LPBK_OV", 11, 1 },
|
|
{ "FIXED_PF", 8, 3 },
|
|
{ "FIXED_VF_VLD", 7, 1 },
|
|
{ "FIXED_VF", 0, 7 },
|
|
{ "MPS_PORT_RX_SPARE", 0x3c13c, 0 },
|
|
{ "MPS_PORT_RX_PTP_RSS_HASH", 0x3c140, 0 },
|
|
{ "MPS_PORT_RX_PTP_RSS_CONTROL", 0x3c144, 0 },
|
|
{ "RSS_CTRL", 16, 8 },
|
|
{ "QUE_NUM", 0, 16 },
|
|
{ "MPS_TX_PRTY_SEL", 0x9400, 0 },
|
|
{ "Ch4_Prty", 20, 3 },
|
|
{ "Ch3_Prty", 16, 3 },
|
|
{ "Ch2_Prty", 12, 3 },
|
|
{ "Ch1_Prty", 8, 3 },
|
|
{ "Ch0_Prty", 4, 3 },
|
|
{ "TP_Source", 2, 2 },
|
|
{ "NCSI_Source", 0, 2 },
|
|
{ "MPS_TX_INT_ENABLE", 0x9404, 0 },
|
|
{ "PortErr", 16, 1 },
|
|
{ "FRMERR", 15, 1 },
|
|
{ "SECNTERR", 14, 1 },
|
|
{ "BUBBLE", 13, 1 },
|
|
{ "TxDescFifo", 9, 4 },
|
|
{ "TxDataFifo", 5, 4 },
|
|
{ "Ncsi", 4, 1 },
|
|
{ "TP", 0, 4 },
|
|
{ "MPS_TX_INT_CAUSE", 0x9408, 0 },
|
|
{ "PortErr", 16, 1 },
|
|
{ "FRMERR", 15, 1 },
|
|
{ "SECNTERR", 14, 1 },
|
|
{ "BUBBLE", 13, 1 },
|
|
{ "TxDescFifo", 9, 4 },
|
|
{ "TxDataFifo", 5, 4 },
|
|
{ "Ncsi", 4, 1 },
|
|
{ "TP", 0, 4 },
|
|
{ "MPS_TX_PERR_ENABLE", 0x9410, 0 },
|
|
{ "TxDescFifo", 9, 4 },
|
|
{ "TxDataFifo", 5, 4 },
|
|
{ "Ncsi", 4, 1 },
|
|
{ "TP", 0, 4 },
|
|
{ "MPS_TX_PERR_INJECT", 0x9414, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MPS_TX_SE_CNT_TP01", 0x9418, 0 },
|
|
{ "SOP_CNT_1", 24, 8 },
|
|
{ "EOP_CNT_1", 16, 8 },
|
|
{ "SOP_CNT_0", 8, 8 },
|
|
{ "EOP_CNT_0", 0, 8 },
|
|
{ "MPS_TX_SE_CNT_TP23", 0x941c, 0 },
|
|
{ "SOP_CNT_3", 24, 8 },
|
|
{ "EOP_CNT_3", 16, 8 },
|
|
{ "SOP_CNT_2", 8, 8 },
|
|
{ "EOP_CNT_2", 0, 8 },
|
|
{ "MPS_TX_SE_CNT_MAC01", 0x9420, 0 },
|
|
{ "SOP_CNT_1", 24, 8 },
|
|
{ "EOP_CNT_1", 16, 8 },
|
|
{ "SOP_CNT_0", 8, 8 },
|
|
{ "EOP_CNT_0", 0, 8 },
|
|
{ "MPS_TX_SE_CNT_MAC23", 0x9424, 0 },
|
|
{ "SOP_CNT_3", 24, 8 },
|
|
{ "EOP_CNT_3", 16, 8 },
|
|
{ "SOP_CNT_2", 8, 8 },
|
|
{ "EOP_CNT_2", 0, 8 },
|
|
{ "MPS_TX_SECNT_SPI_BUBBLE_ERR", 0x9428, 0 },
|
|
{ "Bubble", 16, 8 },
|
|
{ "Spi", 8, 8 },
|
|
{ "SeCnt", 0, 8 },
|
|
{ "MPS_TX_SECNT_BUBBLE_CLR", 0x942c, 0 },
|
|
{ "NcsiSeCnt", 20, 1 },
|
|
{ "LpbkSeCnt", 16, 4 },
|
|
{ "Bubble", 8, 8 },
|
|
{ "SeCnt", 0, 8 },
|
|
{ "MPS_TX_PORT_ERR", 0x9430, 0 },
|
|
{ "Lpbkpt3", 7, 1 },
|
|
{ "Lpbkpt2", 6, 1 },
|
|
{ "Lpbkpt1", 5, 1 },
|
|
{ "Lpbkpt0", 4, 1 },
|
|
{ "pt3", 3, 1 },
|
|
{ "pt2", 2, 1 },
|
|
{ "pt1", 1, 1 },
|
|
{ "pt0", 0, 1 },
|
|
{ "MPS_TX_LPBK_DROP_BP_CTL_CH0", 0x9434, 0 },
|
|
{ "BpEn", 1, 1 },
|
|
{ "DropEn", 0, 1 },
|
|
{ "MPS_TX_LPBK_DROP_BP_CTL_CH1", 0x9438, 0 },
|
|
{ "BpEn", 1, 1 },
|
|
{ "DropEn", 0, 1 },
|
|
{ "MPS_TX_LPBK_DROP_BP_CTL_CH2", 0x943c, 0 },
|
|
{ "BpEn", 1, 1 },
|
|
{ "DropEn", 0, 1 },
|
|
{ "MPS_TX_LPBK_DROP_BP_CTL_CH3", 0x9440, 0 },
|
|
{ "BpEn", 1, 1 },
|
|
{ "DropEn", 0, 1 },
|
|
{ "MPS_TX_DEBUG_REG_TP2TX_10", 0x9444, 0 },
|
|
{ "SOPCh1", 31, 1 },
|
|
{ "EOPCh1", 30, 1 },
|
|
{ "SizeCh1", 26, 4 },
|
|
{ "ErrCh1", 25, 1 },
|
|
{ "FullCh1", 24, 1 },
|
|
{ "ValidCh1", 23, 1 },
|
|
{ "DataCh1", 16, 7 },
|
|
{ "SOPCh0", 15, 1 },
|
|
{ "EOPCh0", 14, 1 },
|
|
{ "SizeCh0", 10, 4 },
|
|
{ "ErrCh0", 9, 1 },
|
|
{ "FullCh0", 8, 1 },
|
|
{ "ValidCh0", 7, 1 },
|
|
{ "DataCh0", 0, 7 },
|
|
{ "MPS_TX_DEBUG_REG_TP2TX_32", 0x9448, 0 },
|
|
{ "SOPCh3", 31, 1 },
|
|
{ "EOPCh3", 30, 1 },
|
|
{ "SizeCh3", 26, 4 },
|
|
{ "ErrCh3", 25, 1 },
|
|
{ "FullCh3", 24, 1 },
|
|
{ "ValidCh3", 23, 1 },
|
|
{ "DataCh3", 16, 7 },
|
|
{ "SOPCh2", 15, 1 },
|
|
{ "EOPCh2", 14, 1 },
|
|
{ "SizeCh2", 10, 4 },
|
|
{ "ErrCh2", 9, 1 },
|
|
{ "FullCh2", 8, 1 },
|
|
{ "ValidCh2", 7, 1 },
|
|
{ "DataCh2", 0, 7 },
|
|
{ "MPS_TX_DEBUG_REG_TX2MAC_10", 0x944c, 0 },
|
|
{ "SOPPt1", 31, 1 },
|
|
{ "EOPPt1", 30, 1 },
|
|
{ "SizePt1", 26, 4 },
|
|
{ "ErrPt1", 25, 1 },
|
|
{ "FullPt1", 24, 1 },
|
|
{ "ValidPt1", 23, 1 },
|
|
{ "DataPt1", 16, 7 },
|
|
{ "SOPPt0", 15, 1 },
|
|
{ "EOPPt0", 14, 1 },
|
|
{ "SizePt0", 10, 4 },
|
|
{ "ErrPt0", 9, 1 },
|
|
{ "FullPt0", 8, 1 },
|
|
{ "ValidPt0", 7, 1 },
|
|
{ "DataPt0", 0, 7 },
|
|
{ "MPS_TX_DEBUG_REG_TX2MAC_32", 0x9450, 0 },
|
|
{ "SOPPt3", 31, 1 },
|
|
{ "EOPPt3", 30, 1 },
|
|
{ "SizePt3", 26, 4 },
|
|
{ "ErrPt3", 25, 1 },
|
|
{ "FullPt3", 24, 1 },
|
|
{ "ValidPt3", 23, 1 },
|
|
{ "DataPt3", 16, 7 },
|
|
{ "SOPPt2", 15, 1 },
|
|
{ "EOPPt2", 14, 1 },
|
|
{ "SizePt2", 10, 4 },
|
|
{ "ErrPt2", 9, 1 },
|
|
{ "FullPt2", 8, 1 },
|
|
{ "ValidPt2", 7, 1 },
|
|
{ "DataPt2", 0, 7 },
|
|
{ "MPS_TX_SGE_CH_PAUSE_IGNR", 0x9454, 0 },
|
|
{ "MPS_TX_DEBUG_SUBPART_SEL", 0x9458, 0 },
|
|
{ "SubPrtH", 11, 5 },
|
|
{ "PortH", 8, 3 },
|
|
{ "SubPrtL", 3, 5 },
|
|
{ "PortL", 0, 3 },
|
|
{ "MPS_TX_PAD_CTL", 0x945c, 0 },
|
|
{ "LpbkPadEnPt3", 7, 1 },
|
|
{ "LpbkPadEnPt2", 6, 1 },
|
|
{ "LpbkPadEnPt1", 5, 1 },
|
|
{ "LpbkPadEnPt0", 4, 1 },
|
|
{ "MacPadEnPt3", 3, 1 },
|
|
{ "MacPadEnPt2", 2, 1 },
|
|
{ "MacPadEnPt1", 1, 1 },
|
|
{ "MacPadEnPt0", 0, 1 },
|
|
{ "MPS_TX_PFVF_PORT_DROP_TP", 0x9460, 0 },
|
|
{ "TP2MPS_Ch3", 24, 8 },
|
|
{ "TP2MPS_Ch2", 16, 8 },
|
|
{ "TP2MPS_Ch1", 8, 8 },
|
|
{ "TP2MPS_Ch0", 0, 8 },
|
|
{ "MPS_TX_PFVF_PORT_DROP_NCSI", 0x9464, 0 },
|
|
{ "MPS_TX_PFVF_PORT_DROP_CTL", 0x9468, 0 },
|
|
{ "PFNOVFDROP", 5, 1 },
|
|
{ "NCSI_Ch4_CLR", 4, 1 },
|
|
{ "TP2MPS_Ch3_CLR", 3, 1 },
|
|
{ "TP2MPS_Ch2_CLR", 2, 1 },
|
|
{ "TP2MPS_Ch1_CLR", 1, 1 },
|
|
{ "TP2MPS_Ch0_CLR", 0, 1 },
|
|
{ "MPS_TX_CGEN", 0x946c, 0 },
|
|
{ "TxOutLpbk3_CGEN", 31, 1 },
|
|
{ "TxOutLpbk2_CGEN", 30, 1 },
|
|
{ "TxOutLpbk1_CGEN", 29, 1 },
|
|
{ "TxOutLpbk0_CGEN", 28, 1 },
|
|
{ "TxOutMAC3_CGEN", 27, 1 },
|
|
{ "TxOutMAC2_CGEN", 26, 1 },
|
|
{ "TxOutMAC1_CGEN", 25, 1 },
|
|
{ "TxOutMAC0_CGEN", 24, 1 },
|
|
{ "TxSchLpbk3_CGEN", 23, 1 },
|
|
{ "TxSchLpbk2_CGEN", 22, 1 },
|
|
{ "TxSchLpbk1_CGEN", 21, 1 },
|
|
{ "TxSchLpbk0_CGEN", 20, 1 },
|
|
{ "TxSchMAC3_CGEN", 19, 1 },
|
|
{ "TxSchMAC2_CGEN", 18, 1 },
|
|
{ "TxSchMAC1_CGEN", 17, 1 },
|
|
{ "TxSchMAC0_CGEN", 16, 1 },
|
|
{ "TxInCh4_CGEN", 15, 1 },
|
|
{ "TxInCh3_CGEN", 14, 1 },
|
|
{ "TxInCh2_CGEN", 13, 1 },
|
|
{ "TxInCh1_CGEN", 12, 1 },
|
|
{ "TxInCh0_CGEN", 11, 1 },
|
|
{ "MPS_TX_CGEN_DYNAMIC", 0x9470, 0 },
|
|
{ "TxOutLpbk3_CGEN", 31, 1 },
|
|
{ "TxOutLpbk2_CGEN", 30, 1 },
|
|
{ "TxOutLpbk1_CGEN", 29, 1 },
|
|
{ "TxOutLpbk0_CGEN", 28, 1 },
|
|
{ "TxOutMAC3_CGEN", 27, 1 },
|
|
{ "TxOutMAC2_CGEN", 26, 1 },
|
|
{ "TxOutMAC1_CGEN", 25, 1 },
|
|
{ "TxOutMAC0_CGEN", 24, 1 },
|
|
{ "TxSchLpbk3_CGEN", 23, 1 },
|
|
{ "TxSchLpbk2_CGEN", 22, 1 },
|
|
{ "TxSchLpbk1_CGEN", 21, 1 },
|
|
{ "TxSchLpbk0_CGEN", 20, 1 },
|
|
{ "TxSchMAC3_CGEN", 19, 1 },
|
|
{ "TxSchMAC2_CGEN", 18, 1 },
|
|
{ "TxSchMAC1_CGEN", 17, 1 },
|
|
{ "TxSchMAC0_CGEN", 16, 1 },
|
|
{ "TxInCh4_CGEN", 15, 1 },
|
|
{ "TxInCh3_CGEN", 14, 1 },
|
|
{ "TxInCh2_CGEN", 13, 1 },
|
|
{ "TxInCh1_CGEN", 12, 1 },
|
|
{ "TxInCh0_CGEN", 11, 1 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1e2e0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1e6e0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1eae0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1eee0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1f2e0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1f6e0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1fae0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PF_TX_QINQ_VLAN", 0x1fee0, 0 },
|
|
{ "ProtocolID", 16, 16 },
|
|
{ "Priority", 13, 3 },
|
|
{ "CFI", 12, 1 },
|
|
{ "Tag", 0, 12 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH0", 0x30190, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH1", 0x30194, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH2", 0x30198, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3019c, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH4", 0x301a0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x301a8, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x301ac, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x301b0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x301b4, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x301b8, 0 },
|
|
{ "MPS_PORT_TX_FIFO_CTL", 0x301c4, 0 },
|
|
{ "FifoTh", 5, 9 },
|
|
{ "FifoEn", 4, 1 },
|
|
{ "MaxPktCnt", 0, 4 },
|
|
{ "MPS_PORT_FPGA_PAUSE_CTL", 0x301c8, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x301d0, 0 },
|
|
{ "off_pending", 8, 8 },
|
|
{ "on_pending", 0, 8 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH0", 0x34190, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH1", 0x34194, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH2", 0x34198, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3419c, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH4", 0x341a0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x341a8, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x341ac, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x341b0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x341b4, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x341b8, 0 },
|
|
{ "MPS_PORT_TX_FIFO_CTL", 0x341c4, 0 },
|
|
{ "FifoTh", 5, 9 },
|
|
{ "FifoEn", 4, 1 },
|
|
{ "MaxPktCnt", 0, 4 },
|
|
{ "MPS_PORT_FPGA_PAUSE_CTL", 0x341c8, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x341d0, 0 },
|
|
{ "off_pending", 8, 8 },
|
|
{ "on_pending", 0, 8 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH0", 0x38190, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH1", 0x38194, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH2", 0x38198, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3819c, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH4", 0x381a0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x381a8, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x381ac, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x381b0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x381b4, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x381b8, 0 },
|
|
{ "MPS_PORT_TX_FIFO_CTL", 0x381c4, 0 },
|
|
{ "FifoTh", 5, 9 },
|
|
{ "FifoEn", 4, 1 },
|
|
{ "MaxPktCnt", 0, 4 },
|
|
{ "MPS_PORT_FPGA_PAUSE_CTL", 0x381c8, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x381d0, 0 },
|
|
{ "off_pending", 8, 8 },
|
|
{ "on_pending", 0, 8 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH0", 0x3c190, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH1", 0x3c194, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH2", 0x3c198, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH3", 0x3c19c, 0 },
|
|
{ "MPS_PORT_TX_MAC_RELOAD_CH4", 0x3c1a0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH0", 0x3c1a8, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH1", 0x3c1ac, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH2", 0x3c1b0, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH3", 0x3c1b4, 0 },
|
|
{ "MPS_PORT_TX_LPBK_RELOAD_CH4", 0x3c1b8, 0 },
|
|
{ "MPS_PORT_TX_FIFO_CTL", 0x3c1c4, 0 },
|
|
{ "FifoTh", 5, 9 },
|
|
{ "FifoEn", 4, 1 },
|
|
{ "MaxPktCnt", 0, 4 },
|
|
{ "MPS_PORT_FPGA_PAUSE_CTL", 0x3c1c8, 0 },
|
|
{ "MPS_PORT_TX_PAUSE_PENDING_STATUS", 0x3c1d0, 0 },
|
|
{ "off_pending", 8, 8 },
|
|
{ "on_pending", 0, 8 },
|
|
{ "MPS_TRC_CFG", 0x9800, 0 },
|
|
{ "TrcMultiRSSFilter", 5, 1 },
|
|
{ "TrcFifoEmpty", 4, 1 },
|
|
{ "TrcIgnoreDropInput", 3, 1 },
|
|
{ "TrcKeepDuplicates", 2, 1 },
|
|
{ "TrcEn", 1, 1 },
|
|
{ "TrcMultiFilter", 0, 1 },
|
|
{ "MPS_TRC_FILTER0_RSS_HASH", 0x9804, 0 },
|
|
{ "MPS_TRC_FILTER0_RSS_CONTROL", 0x9808, 0 },
|
|
{ "RssControl", 16, 8 },
|
|
{ "QueueNumber", 0, 16 },
|
|
{ "MPS_TRC_FILTER1_RSS_HASH", 0x9ff0, 0 },
|
|
{ "MPS_TRC_FILTER1_RSS_CONTROL", 0x9ff4, 0 },
|
|
{ "RssControl", 16, 8 },
|
|
{ "QueueNumber", 0, 16 },
|
|
{ "MPS_TRC_FILTER2_RSS_HASH", 0x9ff8, 0 },
|
|
{ "MPS_TRC_FILTER2_RSS_CONTROL", 0x9ffc, 0 },
|
|
{ "RssControl", 16, 8 },
|
|
{ "QueueNumber", 0, 16 },
|
|
{ "MPS_TRC_FILTER3_RSS_HASH", 0xa000, 0 },
|
|
{ "MPS_TRC_FILTER3_RSS_CONTROL", 0xa004, 0 },
|
|
{ "RssControl", 16, 8 },
|
|
{ "QueueNumber", 0, 16 },
|
|
{ "MPS_TRC_RSS_HASH", 0xa008, 0 },
|
|
{ "MPS_TRC_RSS_CONTROL", 0xa00c, 0 },
|
|
{ "RssControl", 16, 8 },
|
|
{ "QueueNumber", 0, 16 },
|
|
{ "MPS_TRC_VF_OFF_FILTER_0", 0xa010, 0 },
|
|
{ "TrcMPS2TP_MacOnly", 20, 1 },
|
|
{ "TrcAllMPS2TP", 19, 1 },
|
|
{ "TrcAllTP2MPS", 18, 1 },
|
|
{ "TrcAllVf", 17, 1 },
|
|
{ "OffEn", 16, 1 },
|
|
{ "VfFiltEn", 15, 1 },
|
|
{ "VfFiltMask", 8, 7 },
|
|
{ "VfFiltValid", 7, 1 },
|
|
{ "VfFiltData", 0, 7 },
|
|
{ "MPS_TRC_VF_OFF_FILTER_1", 0xa014, 0 },
|
|
{ "TrcMPS2TP_MacOnly", 20, 1 },
|
|
{ "TrcAllMPS2TP", 19, 1 },
|
|
{ "TrcAllTP2MPS", 18, 1 },
|
|
{ "TrcAllVf", 17, 1 },
|
|
{ "OffEn", 16, 1 },
|
|
{ "VfFiltEn", 15, 1 },
|
|
{ "VfFiltMask", 8, 7 },
|
|
{ "VfFiltValid", 7, 1 },
|
|
{ "VfFiltData", 0, 7 },
|
|
{ "MPS_TRC_VF_OFF_FILTER_2", 0xa018, 0 },
|
|
{ "TrcMPS2TP_MacOnly", 20, 1 },
|
|
{ "TrcAllMPS2TP", 19, 1 },
|
|
{ "TrcAllTP2MPS", 18, 1 },
|
|
{ "TrcAllVf", 17, 1 },
|
|
{ "OffEn", 16, 1 },
|
|
{ "VfFiltEn", 15, 1 },
|
|
{ "VfFiltMask", 8, 7 },
|
|
{ "VfFiltValid", 7, 1 },
|
|
{ "VfFiltData", 0, 7 },
|
|
{ "MPS_TRC_VF_OFF_FILTER_3", 0xa01c, 0 },
|
|
{ "TrcMPS2TP_MacOnly", 20, 1 },
|
|
{ "TrcAllMPS2TP", 19, 1 },
|
|
{ "TrcAllTP2MPS", 18, 1 },
|
|
{ "TrcAllVf", 17, 1 },
|
|
{ "OffEn", 16, 1 },
|
|
{ "VfFiltEn", 15, 1 },
|
|
{ "VfFiltMask", 8, 7 },
|
|
{ "VfFiltValid", 7, 1 },
|
|
{ "VfFiltData", 0, 7 },
|
|
{ "MPS_TRC_CGEN", 0xa020, 0 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_A", 0x9810, 0 },
|
|
{ "TfInsertActLen", 27, 1 },
|
|
{ "TfInsertTimer", 26, 1 },
|
|
{ "TfInvertMatch", 25, 1 },
|
|
{ "TfPktTooLarge", 24, 1 },
|
|
{ "TfEn", 23, 1 },
|
|
{ "TfPort", 18, 5 },
|
|
{ "TfDrop", 17, 1 },
|
|
{ "TfSopEopErr", 16, 1 },
|
|
{ "TfLength", 8, 5 },
|
|
{ "TfOffset", 0, 5 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_A", 0x9814, 0 },
|
|
{ "TfInsertActLen", 27, 1 },
|
|
{ "TfInsertTimer", 26, 1 },
|
|
{ "TfInvertMatch", 25, 1 },
|
|
{ "TfPktTooLarge", 24, 1 },
|
|
{ "TfEn", 23, 1 },
|
|
{ "TfPort", 18, 5 },
|
|
{ "TfDrop", 17, 1 },
|
|
{ "TfSopEopErr", 16, 1 },
|
|
{ "TfLength", 8, 5 },
|
|
{ "TfOffset", 0, 5 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_A", 0x9818, 0 },
|
|
{ "TfInsertActLen", 27, 1 },
|
|
{ "TfInsertTimer", 26, 1 },
|
|
{ "TfInvertMatch", 25, 1 },
|
|
{ "TfPktTooLarge", 24, 1 },
|
|
{ "TfEn", 23, 1 },
|
|
{ "TfPort", 18, 5 },
|
|
{ "TfDrop", 17, 1 },
|
|
{ "TfSopEopErr", 16, 1 },
|
|
{ "TfLength", 8, 5 },
|
|
{ "TfOffset", 0, 5 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_A", 0x981c, 0 },
|
|
{ "TfInsertActLen", 27, 1 },
|
|
{ "TfInsertTimer", 26, 1 },
|
|
{ "TfInvertMatch", 25, 1 },
|
|
{ "TfPktTooLarge", 24, 1 },
|
|
{ "TfEn", 23, 1 },
|
|
{ "TfPort", 18, 5 },
|
|
{ "TfDrop", 17, 1 },
|
|
{ "TfSopEopErr", 16, 1 },
|
|
{ "TfLength", 8, 5 },
|
|
{ "TfOffset", 0, 5 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_B", 0x9820, 0 },
|
|
{ "TfMinPktSize", 16, 9 },
|
|
{ "TfCaptureMax", 0, 14 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_B", 0x9824, 0 },
|
|
{ "TfMinPktSize", 16, 9 },
|
|
{ "TfCaptureMax", 0, 14 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_B", 0x9828, 0 },
|
|
{ "TfMinPktSize", 16, 9 },
|
|
{ "TfCaptureMax", 0, 14 },
|
|
{ "MPS_TRC_FILTER_MATCH_CTL_B", 0x982c, 0 },
|
|
{ "TfMinPktSize", 16, 9 },
|
|
{ "TfCaptureMax", 0, 14 },
|
|
{ "MPS_TRC_FILTER_RUNT_CTL", 0x9830, 0 },
|
|
{ "MPS_TRC_FILTER_RUNT_CTL", 0x9834, 0 },
|
|
{ "MPS_TRC_FILTER_RUNT_CTL", 0x9838, 0 },
|
|
{ "MPS_TRC_FILTER_RUNT_CTL", 0x983c, 0 },
|
|
{ "MPS_TRC_FILTER_DROP", 0x9840, 0 },
|
|
{ "TfDropInpCount", 16, 16 },
|
|
{ "TfDropBufferCount", 0, 16 },
|
|
{ "MPS_TRC_FILTER_DROP", 0x9844, 0 },
|
|
{ "TfDropInpCount", 16, 16 },
|
|
{ "TfDropBufferCount", 0, 16 },
|
|
{ "MPS_TRC_FILTER_DROP", 0x9848, 0 },
|
|
{ "TfDropInpCount", 16, 16 },
|
|
{ "TfDropBufferCount", 0, 16 },
|
|
{ "MPS_TRC_FILTER_DROP", 0x984c, 0 },
|
|
{ "TfDropInpCount", 16, 16 },
|
|
{ "TfDropBufferCount", 0, 16 },
|
|
{ "MPS_TRC_PERR_INJECT", 0x9850, 0 },
|
|
{ "MemSel", 1, 4 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MPS_TRC_PERR_ENABLE", 0x9854, 0 },
|
|
{ "MiscPerr", 8, 1 },
|
|
{ "PktFifo", 4, 4 },
|
|
{ "FiltMem", 0, 4 },
|
|
{ "MPS_TRC_INT_ENABLE", 0x9858, 0 },
|
|
{ "PLErrEnb", 9, 1 },
|
|
{ "MiscPerr", 8, 1 },
|
|
{ "PktFifo", 4, 4 },
|
|
{ "FiltMem", 0, 4 },
|
|
{ "MPS_TRC_INT_CAUSE", 0x985c, 0 },
|
|
{ "PLErrEnb", 9, 1 },
|
|
{ "MiscPerr", 8, 1 },
|
|
{ "PktFifo", 4, 4 },
|
|
{ "FiltMem", 0, 4 },
|
|
{ "MPS_TRC_TIMESTAMP_L", 0x9860, 0 },
|
|
{ "MPS_TRC_TIMESTAMP_H", 0x9864, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c00, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c04, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c08, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c0c, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c10, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c14, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c18, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c1c, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c20, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c24, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c28, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c2c, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c30, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c34, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c38, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c3c, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c40, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c44, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c48, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c4c, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c50, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c54, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c58, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c5c, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c60, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c64, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c68, 0 },
|
|
{ "MPS_TRC_FILTER0_MATCH", 0x9c6c, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c80, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c84, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c88, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c8c, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c90, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c94, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c98, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9c9c, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ca0, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ca4, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ca8, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cac, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cb0, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cb4, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cb8, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cbc, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cc0, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cc4, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cc8, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ccc, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cd0, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cd4, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cd8, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cdc, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ce0, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ce4, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9ce8, 0 },
|
|
{ "MPS_TRC_FILTER0_DONT_CARE", 0x9cec, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d00, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d04, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d08, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d0c, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d10, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d14, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d18, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d1c, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d20, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d24, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d28, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d2c, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d30, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d34, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d38, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d3c, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d40, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d44, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d48, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d4c, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d50, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d54, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d58, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d5c, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d60, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d64, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d68, 0 },
|
|
{ "MPS_TRC_FILTER1_MATCH", 0x9d6c, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d80, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d84, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d88, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d8c, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d90, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d94, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d98, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9d9c, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9da0, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9da4, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9da8, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dac, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9db0, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9db4, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9db8, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dbc, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dc0, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dc4, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dc8, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dcc, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dd0, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dd4, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dd8, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9ddc, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9de0, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9de4, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9de8, 0 },
|
|
{ "MPS_TRC_FILTER1_DONT_CARE", 0x9dec, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e00, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e04, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e08, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e0c, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e10, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e14, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e18, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e1c, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e20, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e24, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e28, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e2c, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e30, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e34, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e38, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e3c, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e40, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e44, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e48, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e4c, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e50, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e54, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e58, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e5c, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e60, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e64, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e68, 0 },
|
|
{ "MPS_TRC_FILTER2_MATCH", 0x9e6c, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e80, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e84, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e88, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e8c, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e90, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e94, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e98, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9e9c, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ea0, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ea4, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ea8, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eac, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eb0, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eb4, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eb8, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ebc, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ec0, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ec4, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ec8, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ecc, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ed0, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ed4, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ed8, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9edc, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ee0, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ee4, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9ee8, 0 },
|
|
{ "MPS_TRC_FILTER2_DONT_CARE", 0x9eec, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f00, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f04, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f08, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f0c, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f10, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f14, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f18, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f1c, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f20, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f24, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f28, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f2c, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f30, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f34, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f38, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f3c, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f40, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f44, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f48, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f4c, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f50, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f54, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f58, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f5c, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f60, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f64, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f68, 0 },
|
|
{ "MPS_TRC_FILTER3_MATCH", 0x9f6c, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f80, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f84, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f88, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f8c, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f90, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f94, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f98, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9f9c, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fa0, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fa4, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fa8, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fac, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fb0, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fb4, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fb8, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fbc, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fc0, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fc4, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fc8, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fcc, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fd0, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fd4, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fd8, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fdc, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fe0, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fe4, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fe8, 0 },
|
|
{ "MPS_TRC_FILTER3_DONT_CARE", 0x9fec, 0 },
|
|
{ "MPS_STAT_CTL", 0x9600, 0 },
|
|
{ "StatStopCtrl", 10, 1 },
|
|
{ "StopStat", 9, 1 },
|
|
{ "StatWriteCtrl", 8, 1 },
|
|
{ "CountLbPF", 7, 1 },
|
|
{ "CountLbVF", 6, 1 },
|
|
{ "CountPauseMCRx", 5, 1 },
|
|
{ "CountPauseStatRx", 4, 1 },
|
|
{ "CountPauseMCTx", 3, 1 },
|
|
{ "CountPauseStatTx", 2, 1 },
|
|
{ "CountVFinPF", 1, 1 },
|
|
{ "LpbkErrStat", 0, 1 },
|
|
{ "MPS_STAT_INT_ENABLE", 0x9608, 0 },
|
|
{ "MPS_STAT_INT_CAUSE", 0x960c, 0 },
|
|
{ "MPS_STAT_PERR_INT_ENABLE_SRAM", 0x9610, 0 },
|
|
{ "Rxbg", 27, 2 },
|
|
{ "Rxpf", 22, 5 },
|
|
{ "Txpf", 18, 4 },
|
|
{ "Rxport", 11, 7 },
|
|
{ "Lbport", 6, 5 },
|
|
{ "Txport", 0, 6 },
|
|
{ "MPS_STAT_PERR_INT_CAUSE_SRAM", 0x9614, 0 },
|
|
{ "Rxbg", 27, 2 },
|
|
{ "Rxpf", 22, 5 },
|
|
{ "Txpf", 18, 4 },
|
|
{ "Rxport", 11, 7 },
|
|
{ "Lbport", 6, 5 },
|
|
{ "Txport", 0, 6 },
|
|
{ "MPS_STAT_PERR_ENABLE_SRAM", 0x9618, 0 },
|
|
{ "Rxbg", 27, 2 },
|
|
{ "Rxpf", 22, 5 },
|
|
{ "Txpf", 18, 4 },
|
|
{ "Rxport", 11, 7 },
|
|
{ "Lbport", 6, 5 },
|
|
{ "Txport", 0, 6 },
|
|
{ "MPS_STAT_PERR_INT_ENABLE_TX_FIFO", 0x961c, 0 },
|
|
{ "TxCh", 20, 4 },
|
|
{ "Tx", 12, 8 },
|
|
{ "Pause", 8, 4 },
|
|
{ "Drop", 0, 8 },
|
|
{ "MPS_STAT_PERR_INT_CAUSE_TX_FIFO", 0x9620, 0 },
|
|
{ "TxCh", 20, 4 },
|
|
{ "Tx", 12, 8 },
|
|
{ "Pause", 8, 4 },
|
|
{ "Drop", 0, 8 },
|
|
{ "MPS_STAT_PERR_ENABLE_TX_FIFO", 0x9624, 0 },
|
|
{ "TxCh", 20, 4 },
|
|
{ "Tx", 12, 8 },
|
|
{ "Pause", 8, 4 },
|
|
{ "Drop", 0, 8 },
|
|
{ "MPS_STAT_PERR_INT_ENABLE_RX_FIFO", 0x9628, 0 },
|
|
{ "Pause", 20, 4 },
|
|
{ "Lpbk", 16, 4 },
|
|
{ "Nq", 8, 8 },
|
|
{ "PV", 4, 4 },
|
|
{ "Mac", 0, 4 },
|
|
{ "MPS_STAT_PERR_INT_CAUSE_RX_FIFO", 0x962c, 0 },
|
|
{ "Pause", 20, 4 },
|
|
{ "Lpbk", 16, 4 },
|
|
{ "Nq", 8, 8 },
|
|
{ "PV", 4, 4 },
|
|
{ "Mac", 0, 4 },
|
|
{ "MPS_STAT_PERR_ENABLE_RX_FIFO", 0x9630, 0 },
|
|
{ "Pause", 20, 4 },
|
|
{ "Lpbk", 16, 4 },
|
|
{ "Nq", 8, 8 },
|
|
{ "PV", 4, 4 },
|
|
{ "Mac", 0, 4 },
|
|
{ "MPS_STAT_PERR_INJECT", 0x9634, 0 },
|
|
{ "MemSel", 1, 7 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MPS_STAT_DEBUG_SUB_SEL", 0x9638, 0 },
|
|
{ "SubPrtH", 5, 5 },
|
|
{ "SubPrtL", 0, 5 },
|
|
{ "MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L", 0x9640, 0 },
|
|
{ "MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H", 0x9644, 0 },
|
|
{ "MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L", 0x9648, 0 },
|
|
{ "MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H", 0x964c, 0 },
|
|
{ "MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L", 0x9650, 0 },
|
|
{ "MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H", 0x9654, 0 },
|
|
{ "MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L", 0x9658, 0 },
|
|
{ "MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H", 0x965c, 0 },
|
|
{ "MPS_STAT_RX_BG_0_LB_DROP_FRAME_L", 0x9660, 0 },
|
|
{ "MPS_STAT_RX_BG_0_LB_DROP_FRAME_H", 0x9664, 0 },
|
|
{ "MPS_STAT_RX_BG_1_LB_DROP_FRAME_L", 0x9668, 0 },
|
|
{ "MPS_STAT_RX_BG_1_LB_DROP_FRAME_H", 0x966c, 0 },
|
|
{ "MPS_STAT_RX_BG_2_LB_DROP_FRAME_L", 0x9670, 0 },
|
|
{ "MPS_STAT_RX_BG_2_LB_DROP_FRAME_H", 0x9674, 0 },
|
|
{ "MPS_STAT_RX_BG_3_LB_DROP_FRAME_L", 0x9678, 0 },
|
|
{ "MPS_STAT_RX_BG_3_LB_DROP_FRAME_H", 0x967c, 0 },
|
|
{ "MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L", 0x9680, 0 },
|
|
{ "MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H", 0x9684, 0 },
|
|
{ "MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L", 0x9688, 0 },
|
|
{ "MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H", 0x968c, 0 },
|
|
{ "MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L", 0x9690, 0 },
|
|
{ "MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H", 0x9694, 0 },
|
|
{ "MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L", 0x9698, 0 },
|
|
{ "MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H", 0x969c, 0 },
|
|
{ "MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L", 0x96a0, 0 },
|
|
{ "MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H", 0x96a4, 0 },
|
|
{ "MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L", 0x96a8, 0 },
|
|
{ "MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H", 0x96ac, 0 },
|
|
{ "MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L", 0x96b0, 0 },
|
|
{ "MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H", 0x96b4, 0 },
|
|
{ "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L", 0x96b8, 0 },
|
|
{ "MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H", 0x96bc, 0 },
|
|
{ "MPS_STAT_PERR_INT_ENABLE_SRAM1", 0x96c0, 0 },
|
|
{ "Rxvf", 5, 3 },
|
|
{ "Txvf", 0, 5 },
|
|
{ "MPS_STAT_PERR_INT_CAUSE_SRAM1", 0x96c4, 0 },
|
|
{ "Rxvf", 5, 3 },
|
|
{ "Txvf", 0, 5 },
|
|
{ "MPS_STAT_PERR_ENABLE_SRAM1", 0x96c8, 0 },
|
|
{ "Rxvf", 5, 3 },
|
|
{ "Txvf", 0, 5 },
|
|
{ "MPS_STAT_STOP_UPD_BG", 0x96cc, 0 },
|
|
{ "MPS_STAT_STOP_UPD_PORT", 0x96d0, 0 },
|
|
{ "PtLpbk", 8, 4 },
|
|
{ "PtTx", 4, 4 },
|
|
{ "PtRx", 0, 4 },
|
|
{ "MPS_STAT_STOP_UPD_PF", 0x96d4, 0 },
|
|
{ "PFTx", 8, 8 },
|
|
{ "PFRx", 0, 8 },
|
|
{ "MPS_STAT_STOP_UPD_TX_VF_0_31", 0x96d8, 0 },
|
|
{ "MPS_STAT_STOP_UPD_TX_VF_32_63", 0x96dc, 0 },
|
|
{ "MPS_STAT_STOP_UPD_TX_VF_64_95", 0x96e0, 0 },
|
|
{ "MPS_STAT_STOP_UPD_TX_VF_96_127", 0x96e4, 0 },
|
|
{ "MPS_STAT_STOP_UPD_RX_VF_0_31", 0x96e8, 0 },
|
|
{ "MPS_STAT_STOP_UPD_RX_VF_32_63", 0x96ec, 0 },
|
|
{ "MPS_STAT_STOP_UPD_RX_VF_64_95", 0x96f0, 0 },
|
|
{ "MPS_STAT_STOP_UPD_RX_VF_96_127", 0x96f4, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x30400, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x30404, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x30408, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3040c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x30410, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x30414, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x30418, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3041c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x30420, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x30424, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x30428, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3042c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_L", 0x30430, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_H", 0x30434, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x30438, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3043c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x30440, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x30444, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x30448, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3044c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x30450, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x30454, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x30458, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3045c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x30460, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x30464, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_L", 0x30468, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3046c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x30470, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x30474, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x30478, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3047c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x30480, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x30484, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x30488, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3048c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x30490, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x30494, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x30498, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3049c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x304a0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x304a4, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x304a8, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x304ac, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x304b0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x304b4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x304c0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x304c4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x304c8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x304cc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x304d0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x304d4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x304d8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x304dc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x304e0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x304e4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x304e8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x304ec, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_L", 0x304f0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_H", 0x304f4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x304f8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x304fc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x30500, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x30504, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x30508, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3050c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x30510, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x30514, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x30518, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3051c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x30520, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x30524, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x30528, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3052c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x30540, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x30544, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x30548, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3054c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x30550, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x30554, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x30558, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3055c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x30560, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x30564, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x30568, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3056c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x30570, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x30574, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x30578, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3057c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x30580, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x30584, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x30588, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3058c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_L", 0x30590, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_H", 0x30594, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x30598, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3059c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x305a0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x305a4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x305a8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x305ac, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x305b0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x305b4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x305b8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x305bc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x305c0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x305c4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x305c8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x305cc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x305d0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x305d4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x305d8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x305dc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x305e0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x305e4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x305e8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x305ec, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x305f0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x305f4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x305f8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x305fc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x30600, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x30604, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x30608, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3060c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x30610, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x30614, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x30618, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3061c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x34400, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x34404, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x34408, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3440c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x34410, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x34414, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x34418, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3441c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x34420, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x34424, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x34428, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3442c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_L", 0x34430, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_H", 0x34434, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x34438, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3443c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x34440, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x34444, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x34448, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3444c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x34450, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x34454, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x34458, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3445c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x34460, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x34464, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_L", 0x34468, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3446c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x34470, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x34474, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x34478, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3447c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x34480, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x34484, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x34488, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3448c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x34490, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x34494, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x34498, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3449c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x344a0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x344a4, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x344a8, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x344ac, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x344b0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x344b4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x344c0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x344c4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x344c8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x344cc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x344d0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x344d4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x344d8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x344dc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x344e0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x344e4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x344e8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x344ec, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_L", 0x344f0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_H", 0x344f4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x344f8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x344fc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x34500, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x34504, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x34508, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3450c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x34510, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x34514, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x34518, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3451c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x34520, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x34524, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x34528, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3452c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x34540, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x34544, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x34548, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3454c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x34550, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x34554, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x34558, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3455c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x34560, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x34564, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x34568, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3456c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x34570, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x34574, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x34578, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3457c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x34580, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x34584, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x34588, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3458c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_L", 0x34590, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_H", 0x34594, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x34598, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3459c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x345a0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x345a4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x345a8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x345ac, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x345b0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x345b4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x345b8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x345bc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x345c0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x345c4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x345c8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x345cc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x345d0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x345d4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x345d8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x345dc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x345e0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x345e4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x345e8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x345ec, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x345f0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x345f4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x345f8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x345fc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x34600, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x34604, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x34608, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3460c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x34610, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x34614, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x34618, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3461c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x38400, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x38404, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x38408, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3840c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x38410, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x38414, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x38418, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3841c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x38420, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x38424, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x38428, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3842c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_L", 0x38430, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_H", 0x38434, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x38438, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3843c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x38440, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x38444, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x38448, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3844c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x38450, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x38454, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x38458, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3845c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x38460, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x38464, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_L", 0x38468, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3846c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x38470, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x38474, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x38478, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3847c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x38480, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x38484, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x38488, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3848c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x38490, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x38494, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x38498, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3849c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x384a0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x384a4, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x384a8, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x384ac, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x384b0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x384b4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x384c0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x384c4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x384c8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x384cc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x384d0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x384d4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x384d8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x384dc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x384e0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x384e4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x384e8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x384ec, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_L", 0x384f0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_H", 0x384f4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x384f8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x384fc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x38500, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x38504, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x38508, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3850c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x38510, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x38514, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x38518, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3851c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x38520, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x38524, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x38528, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3852c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x38540, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x38544, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x38548, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3854c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x38550, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x38554, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x38558, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3855c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x38560, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x38564, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x38568, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3856c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x38570, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x38574, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x38578, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3857c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x38580, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x38584, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x38588, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3858c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_L", 0x38590, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_H", 0x38594, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x38598, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3859c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x385a0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x385a4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x385a8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x385ac, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x385b0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x385b4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x385b8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x385bc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x385c0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x385c4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x385c8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x385cc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x385d0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x385d4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x385d8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x385dc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x385e0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x385e4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x385e8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x385ec, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x385f0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x385f4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x385f8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x385fc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x38600, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x38604, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x38608, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3860c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x38610, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x38614, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x38618, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3861c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_L", 0x3c400, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BYTES_H", 0x3c404, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_L", 0x3c408, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_FRAMES_H", 0x3c40c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_L", 0x3c410, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_BCAST_H", 0x3c414, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_L", 0x3c418, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_MCAST_H", 0x3c41c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_L", 0x3c420, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_UCAST_H", 0x3c424, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_L", 0x3c428, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_ERROR_H", 0x3c42c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_L", 0x3c430, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_64B_H", 0x3c434, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_L", 0x3c438, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_65B_127B_H", 0x3c43c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_L", 0x3c440, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_128B_255B_H", 0x3c444, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_L", 0x3c448, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_256B_511B_H", 0x3c44c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_L", 0x3c450, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_512B_1023B_H", 0x3c454, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_L", 0x3c458, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1024B_1518B_H", 0x3c45c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_L", 0x3c460, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_1519B_MAX_H", 0x3c464, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_L", 0x3c468, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_DROP_H", 0x3c46c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_L", 0x3c470, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PAUSE_H", 0x3c474, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_L", 0x3c478, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP0_H", 0x3c47c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_L", 0x3c480, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP1_H", 0x3c484, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_L", 0x3c488, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP2_H", 0x3c48c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_L", 0x3c490, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP3_H", 0x3c494, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_L", 0x3c498, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP4_H", 0x3c49c, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_L", 0x3c4a0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP5_H", 0x3c4a4, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_L", 0x3c4a8, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP6_H", 0x3c4ac, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_L", 0x3c4b0, 0 },
|
|
{ "MPS_PORT_STAT_TX_PORT_PPP7_H", 0x3c4b4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_L", 0x3c4c0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BYTES_H", 0x3c4c4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_L", 0x3c4c8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_FRAMES_H", 0x3c4cc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_L", 0x3c4d0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_BCAST_H", 0x3c4d4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_L", 0x3c4d8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_MCAST_H", 0x3c4dc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_L", 0x3c4e0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_UCAST_H", 0x3c4e4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_L", 0x3c4e8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_ERROR_H", 0x3c4ec, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_L", 0x3c4f0, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_64B_H", 0x3c4f4, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_L", 0x3c4f8, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_65B_127B_H", 0x3c4fc, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_L", 0x3c500, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_128B_255B_H", 0x3c504, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_L", 0x3c508, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_256B_511B_H", 0x3c50c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_L", 0x3c510, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_512B_1023B_H", 0x3c514, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_L", 0x3c518, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1024B_1518B_H", 0x3c51c, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_L", 0x3c520, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_1519B_MAX_H", 0x3c524, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L", 0x3c528, 0 },
|
|
{ "MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H", 0x3c52c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_L", 0x3c540, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BYTES_H", 0x3c544, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_L", 0x3c548, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_FRAMES_H", 0x3c54c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_L", 0x3c550, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_BCAST_H", 0x3c554, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_L", 0x3c558, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MCAST_H", 0x3c55c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_L", 0x3c560, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_UCAST_H", 0x3c564, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_L", 0x3c568, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_ERROR_H", 0x3c56c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L", 0x3c570, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H", 0x3c574, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_L", 0x3c578, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_CRC_ERROR_H", 0x3c57c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_L", 0x3c580, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LEN_ERROR_H", 0x3c584, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_L", 0x3c588, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_SYM_ERROR_H", 0x3c58c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_L", 0x3c590, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_64B_H", 0x3c594, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_L", 0x3c598, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_65B_127B_H", 0x3c59c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_L", 0x3c5a0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_128B_255B_H", 0x3c5a4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_L", 0x3c5a8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_256B_511B_H", 0x3c5ac, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_L", 0x3c5b0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_512B_1023B_H", 0x3c5b4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_L", 0x3c5b8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1024B_1518B_H", 0x3c5bc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_L", 0x3c5c0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_1519B_MAX_H", 0x3c5c4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_L", 0x3c5c8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PAUSE_H", 0x3c5cc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_L", 0x3c5d0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP0_H", 0x3c5d4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_L", 0x3c5d8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP1_H", 0x3c5dc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_L", 0x3c5e0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP2_H", 0x3c5e4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_L", 0x3c5e8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP3_H", 0x3c5ec, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_L", 0x3c5f0, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP4_H", 0x3c5f4, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_L", 0x3c5f8, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP5_H", 0x3c5fc, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_L", 0x3c600, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP6_H", 0x3c604, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_L", 0x3c608, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_PPP7_H", 0x3c60c, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_L", 0x3c610, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_LESS_64B_H", 0x3c614, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_L", 0x3c618, 0 },
|
|
{ "MPS_PORT_STAT_RX_PORT_MAC_ERROR_H", 0x3c61c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1e300, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1e304, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1e308, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1e30c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1e310, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1e314, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1e318, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1e31c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1e320, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1e324, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1e328, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1e32c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1e330, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1e334, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1e338, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1e33c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1e340, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1e344, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1e348, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1e34c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1e350, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1e354, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1e358, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1e35c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1e360, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1e364, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1e368, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1e36c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1e370, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1e374, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1e378, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1e37c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1e380, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1e384, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1e700, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1e704, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1e708, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1e70c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1e710, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1e714, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1e718, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1e71c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1e720, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1e724, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1e728, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1e72c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1e730, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1e734, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1e738, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1e73c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1e740, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1e744, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1e748, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1e74c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1e750, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1e754, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1e758, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1e75c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1e760, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1e764, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1e768, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1e76c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1e770, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1e774, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1e778, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1e77c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1e780, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1e784, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1eb00, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1eb04, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1eb08, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1eb0c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1eb10, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1eb14, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1eb18, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1eb1c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1eb20, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1eb24, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1eb28, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1eb2c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1eb30, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1eb34, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1eb38, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1eb3c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1eb40, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1eb44, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1eb48, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1eb4c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1eb50, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1eb54, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1eb58, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1eb5c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1eb60, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1eb64, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1eb68, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1eb6c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1eb70, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1eb74, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1eb78, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1eb7c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1eb80, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1eb84, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1ef00, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1ef04, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1ef08, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1ef0c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1ef10, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1ef14, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1ef18, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1ef1c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1ef20, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1ef24, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1ef28, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1ef2c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1ef30, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1ef34, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1ef38, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1ef3c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1ef40, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1ef44, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1ef48, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1ef4c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1ef50, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1ef54, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1ef58, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1ef5c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1ef60, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1ef64, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1ef68, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1ef6c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1ef70, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1ef74, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1ef78, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1ef7c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1ef80, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1ef84, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1f300, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1f304, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1f308, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1f30c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1f310, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1f314, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1f318, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1f31c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1f320, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1f324, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1f328, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1f32c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1f330, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1f334, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1f338, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1f33c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1f340, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1f344, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1f348, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1f34c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1f350, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1f354, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1f358, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1f35c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1f360, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1f364, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1f368, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1f36c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1f370, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1f374, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1f378, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1f37c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1f380, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1f384, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1f700, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1f704, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1f708, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1f70c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1f710, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1f714, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1f718, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1f71c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1f720, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1f724, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1f728, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1f72c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1f730, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1f734, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1f738, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1f73c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1f740, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1f744, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1f748, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1f74c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1f750, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1f754, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1f758, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1f75c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1f760, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1f764, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1f768, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1f76c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1f770, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1f774, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1f778, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1f77c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1f780, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1f784, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1fb00, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1fb04, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1fb08, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1fb0c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1fb10, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1fb14, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1fb18, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1fb1c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1fb20, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1fb24, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1fb28, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1fb2c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1fb30, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1fb34, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1fb38, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1fb3c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1fb40, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1fb44, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1fb48, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1fb4c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1fb50, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1fb54, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1fb58, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1fb5c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1fb60, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1fb64, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1fb68, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1fb6c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1fb70, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1fb74, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1fb78, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1fb7c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1fb80, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1fb84, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_L", 0x1ff00, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_BYTES_H", 0x1ff04, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_L", 0x1ff08, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_BCAST_FRAMES_H", 0x1ff0c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_L", 0x1ff10, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_BYTES_H", 0x1ff14, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_L", 0x1ff18, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_MCAST_FRAMES_H", 0x1ff1c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_L", 0x1ff20, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_BYTES_H", 0x1ff24, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_L", 0x1ff28, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_UCAST_FRAMES_H", 0x1ff2c, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L", 0x1ff30, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H", 0x1ff34, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L", 0x1ff38, 0 },
|
|
{ "MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H", 0x1ff3c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_L", 0x1ff40, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BYTES_H", 0x1ff44, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_L", 0x1ff48, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_FRAMES_H", 0x1ff4c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_L", 0x1ff50, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_BYTES_H", 0x1ff54, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_L", 0x1ff58, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_BCAST_FRAMES_H", 0x1ff5c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_L", 0x1ff60, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_BYTES_H", 0x1ff64, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_L", 0x1ff68, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_MCAST_FRAMES_H", 0x1ff6c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_L", 0x1ff70, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_BYTES_H", 0x1ff74, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_L", 0x1ff78, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_UCAST_FRAMES_H", 0x1ff7c, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_L", 0x1ff80, 0 },
|
|
{ "MPS_PF_STAT_RX_PF_ERR_FRAMES_H", 0x1ff84, 0 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30200, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30204, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30208, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3020c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30210, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30214, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30218, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3021c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30220, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30224, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30228, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3022c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30230, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30234, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30238, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3023c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30240, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30244, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30248, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3024c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30250, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30254, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30258, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3025c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30260, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30264, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30268, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3026c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30270, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30274, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30278, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3027c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30280, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30284, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30288, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3028c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30290, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30294, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30298, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3029c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302a0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302a4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302a8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302ac, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302b0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302b4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302b8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302bc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302c0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302c4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302c8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302cc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302d0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302d4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302d8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302dc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302e0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302e4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302e8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302ec, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302f0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302f4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302f8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x302fc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x30300, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34200, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34204, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34208, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3420c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34210, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34214, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34218, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3421c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34220, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34224, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34228, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3422c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34230, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34234, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34238, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3423c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34240, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34244, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34248, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3424c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34250, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34254, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34258, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3425c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34260, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34264, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34268, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3426c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34270, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34274, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34278, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3427c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34280, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34284, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34288, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3428c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34290, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34294, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34298, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3429c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342a0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342a4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342a8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342ac, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342b0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342b4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342b8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342bc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342c0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342c4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342c8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342cc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342d0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342d4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342d8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342dc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342e0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342e4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342e8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342ec, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342f0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342f4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342f8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x342fc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x34300, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38200, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38204, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38208, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3820c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38210, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38214, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38218, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3821c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38220, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38224, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38228, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3822c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38230, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38234, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38238, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3823c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38240, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38244, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38248, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3824c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38250, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38254, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38258, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3825c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38260, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38264, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38268, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3826c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38270, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38274, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38278, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3827c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38280, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38284, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38288, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3828c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38290, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38294, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38298, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3829c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382a0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382a4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382a8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382ac, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382b0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382b4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382b8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382bc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382c0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382c4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382c8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382cc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382d0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382d4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382d8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382dc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382e0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382e4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382e8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382ec, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382f0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382f4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382f8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x382fc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x38300, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c200, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c204, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c208, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c20c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c210, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c214, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c218, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c21c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c220, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c224, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c228, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c22c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c230, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c234, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c238, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c23c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c240, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c244, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c248, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c24c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c250, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c254, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c258, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c25c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c260, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c264, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c268, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c26c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c270, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c274, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c278, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c27c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c280, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c284, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c288, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c28c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c290, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c294, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c298, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c29c, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2a0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2a4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2a8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2ac, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2b0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2b4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2b8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2bc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2c0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2c4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2c8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2cc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2d0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2d4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2d8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2dc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2e0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2e4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2e8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2ec, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2f0, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2f4, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2f8, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c2fc, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_SRAM", 0x3c300, 0 },
|
|
{ "Valid", 20, 1 },
|
|
{ "PortMap", 16, 4 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_HASH_CTL", 0x30304, 0 },
|
|
{ "UnicastEnable", 31, 1 },
|
|
{ "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x30308, 0 },
|
|
{ "Enable", 31, 1 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x3030c, 0 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x30310, 0 },
|
|
{ "MatchBoth", 17, 1 },
|
|
{ "Valid", 16, 1 },
|
|
{ "DA", 0, 16 },
|
|
{ "MPS_PORT_CLS_BMC_VLAN", 0x30314, 0 },
|
|
{ "BMC_VLAN_SEL", 13, 1 },
|
|
{ "Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PORT_CLS_CTL", 0x30318, 0 },
|
|
{ "LPBK_TCAM1_HIT_PRIORITY", 14, 1 },
|
|
{ "LPBK_TCAM0_HIT_PRIORITY", 13, 1 },
|
|
{ "LPBK_TCAM_PRIORITY", 12, 1 },
|
|
{ "LPBK_SMAC_TCAM_SEL", 10, 2 },
|
|
{ "LPBK_DMAC_TCAM_SEL", 8, 2 },
|
|
{ "TCAM1_HIT_PRIORITY", 7, 1 },
|
|
{ "TCAM0_HIT_PRIORITY", 6, 1 },
|
|
{ "TCAM_PRIORITY", 5, 1 },
|
|
{ "SMAC_TCAM_SEL", 3, 2 },
|
|
{ "DMAC_TCAM_SEL", 1, 2 },
|
|
{ "PF_VLAN_SEL", 0, 1 },
|
|
{ "MPS_PORT_CLS_HASH_CTL", 0x34304, 0 },
|
|
{ "UnicastEnable", 31, 1 },
|
|
{ "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x34308, 0 },
|
|
{ "Enable", 31, 1 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x3430c, 0 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x34310, 0 },
|
|
{ "MatchBoth", 17, 1 },
|
|
{ "Valid", 16, 1 },
|
|
{ "DA", 0, 16 },
|
|
{ "MPS_PORT_CLS_BMC_VLAN", 0x34314, 0 },
|
|
{ "BMC_VLAN_SEL", 13, 1 },
|
|
{ "Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PORT_CLS_CTL", 0x34318, 0 },
|
|
{ "LPBK_TCAM1_HIT_PRIORITY", 14, 1 },
|
|
{ "LPBK_TCAM0_HIT_PRIORITY", 13, 1 },
|
|
{ "LPBK_TCAM_PRIORITY", 12, 1 },
|
|
{ "LPBK_SMAC_TCAM_SEL", 10, 2 },
|
|
{ "LPBK_DMAC_TCAM_SEL", 8, 2 },
|
|
{ "TCAM1_HIT_PRIORITY", 7, 1 },
|
|
{ "TCAM0_HIT_PRIORITY", 6, 1 },
|
|
{ "TCAM_PRIORITY", 5, 1 },
|
|
{ "SMAC_TCAM_SEL", 3, 2 },
|
|
{ "DMAC_TCAM_SEL", 1, 2 },
|
|
{ "PF_VLAN_SEL", 0, 1 },
|
|
{ "MPS_PORT_CLS_HASH_CTL", 0x38304, 0 },
|
|
{ "UnicastEnable", 31, 1 },
|
|
{ "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x38308, 0 },
|
|
{ "Enable", 31, 1 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x3830c, 0 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x38310, 0 },
|
|
{ "MatchBoth", 17, 1 },
|
|
{ "Valid", 16, 1 },
|
|
{ "DA", 0, 16 },
|
|
{ "MPS_PORT_CLS_BMC_VLAN", 0x38314, 0 },
|
|
{ "BMC_VLAN_SEL", 13, 1 },
|
|
{ "Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PORT_CLS_CTL", 0x38318, 0 },
|
|
{ "LPBK_TCAM1_HIT_PRIORITY", 14, 1 },
|
|
{ "LPBK_TCAM0_HIT_PRIORITY", 13, 1 },
|
|
{ "LPBK_TCAM_PRIORITY", 12, 1 },
|
|
{ "LPBK_SMAC_TCAM_SEL", 10, 2 },
|
|
{ "LPBK_DMAC_TCAM_SEL", 8, 2 },
|
|
{ "TCAM1_HIT_PRIORITY", 7, 1 },
|
|
{ "TCAM0_HIT_PRIORITY", 6, 1 },
|
|
{ "TCAM_PRIORITY", 5, 1 },
|
|
{ "SMAC_TCAM_SEL", 3, 2 },
|
|
{ "DMAC_TCAM_SEL", 1, 2 },
|
|
{ "PF_VLAN_SEL", 0, 1 },
|
|
{ "MPS_PORT_CLS_HASH_CTL", 0x3c304, 0 },
|
|
{ "UnicastEnable", 31, 1 },
|
|
{ "MPS_PORT_CLS_PROMISCUOUS_CTL", 0x3c308, 0 },
|
|
{ "Enable", 31, 1 },
|
|
{ "MultiListen", 15, 1 },
|
|
{ "Priority", 12, 3 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_L", 0x3c30c, 0 },
|
|
{ "MPS_PORT_CLS_BMC_MAC_ADDR_H", 0x3c310, 0 },
|
|
{ "MatchBoth", 17, 1 },
|
|
{ "Valid", 16, 1 },
|
|
{ "DA", 0, 16 },
|
|
{ "MPS_PORT_CLS_BMC_VLAN", 0x3c314, 0 },
|
|
{ "BMC_VLAN_SEL", 13, 1 },
|
|
{ "Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_PORT_CLS_CTL", 0x3c318, 0 },
|
|
{ "LPBK_TCAM1_HIT_PRIORITY", 14, 1 },
|
|
{ "LPBK_TCAM0_HIT_PRIORITY", 13, 1 },
|
|
{ "LPBK_TCAM_PRIORITY", 12, 1 },
|
|
{ "LPBK_SMAC_TCAM_SEL", 10, 2 },
|
|
{ "LPBK_DMAC_TCAM_SEL", 8, 2 },
|
|
{ "TCAM1_HIT_PRIORITY", 7, 1 },
|
|
{ "TCAM0_HIT_PRIORITY", 6, 1 },
|
|
{ "TCAM_PRIORITY", 5, 1 },
|
|
{ "SMAC_TCAM_SEL", 3, 2 },
|
|
{ "DMAC_TCAM_SEL", 1, 2 },
|
|
{ "PF_VLAN_SEL", 0, 1 },
|
|
{ "MPS_CLS_CTL", 0xd000, 0 },
|
|
{ "MemWriteFault", 4, 1 },
|
|
{ "MemWriteWaiting", 3, 1 },
|
|
{ "CimNoPromiscuous", 2, 1 },
|
|
{ "HypervisorOnly", 1, 1 },
|
|
{ "VlanClsEn", 0, 1 },
|
|
{ "MPS_CLS_ARB_WEIGHT", 0xd004, 0 },
|
|
{ "PlWeight", 16, 5 },
|
|
{ "CimWeight", 8, 5 },
|
|
{ "LpbkWeight", 0, 5 },
|
|
{ "MPS_CLS_BMC_MAC_ADDR_L", 0xd010, 0 },
|
|
{ "MPS_CLS_BMC_MAC_ADDR_H", 0xd014, 0 },
|
|
{ "MatchBoth", 17, 1 },
|
|
{ "Valid", 16, 1 },
|
|
{ "DA", 0, 16 },
|
|
{ "MPS_CLS_BMC_VLAN", 0xd018, 0 },
|
|
{ "Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_PERR_INJECT", 0xd01c, 0 },
|
|
{ "MemSel", 1, 2 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MPS_CLS_PERR_ENABLE", 0xd020, 0 },
|
|
{ "HashSRAM", 2, 1 },
|
|
{ "MatchTCAM", 1, 1 },
|
|
{ "MatchSRAM", 0, 1 },
|
|
{ "MPS_CLS_INT_ENABLE", 0xd024, 0 },
|
|
{ "PLErrEnb", 3, 1 },
|
|
{ "HashSRAM", 2, 1 },
|
|
{ "MatchTCAM", 1, 1 },
|
|
{ "MatchSRAM", 0, 1 },
|
|
{ "MPS_CLS_INT_CAUSE", 0xd028, 0 },
|
|
{ "PLErrEnb", 3, 1 },
|
|
{ "HashSRAM", 2, 1 },
|
|
{ "MatchTCAM", 1, 1 },
|
|
{ "MatchSRAM", 0, 1 },
|
|
{ "MPS_CLS_PL_TEST_DATA_L", 0xd02c, 0 },
|
|
{ "MPS_CLS_PL_TEST_DATA_H", 0xd030, 0 },
|
|
{ "MPS_CLS_PL_TEST_RES_DATA", 0xd034, 0 },
|
|
{ "Cls_Priority", 24, 3 },
|
|
{ "Cls_Replicate", 23, 1 },
|
|
{ "Cls_Index", 14, 9 },
|
|
{ "Cls_VF", 7, 7 },
|
|
{ "Cls_VF_Vld", 6, 1 },
|
|
{ "Cls_PF", 3, 3 },
|
|
{ "Cls_Match", 0, 3 },
|
|
{ "MPS_CLS_PL_TEST_CTL", 0xd038, 0 },
|
|
{ "MPS_CLS_PORT_BMC_CTL", 0xd03c, 0 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfc0, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfc4, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfc8, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfcc, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfd0, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfd4, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfd8, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfdc, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_VLAN_TABLE", 0xdfe0, 0 },
|
|
{ "VLAN_Mask", 16, 12 },
|
|
{ "PF", 13, 3 },
|
|
{ "VLAN_Valid", 12, 1 },
|
|
{ "VLAN_ID", 0, 12 },
|
|
{ "MPS_CLS_SRAM_L", 0xe000, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe008, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe010, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe018, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe020, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe028, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe030, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe038, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe040, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe048, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe050, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe058, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe060, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe068, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe070, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe078, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe080, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe088, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe090, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe098, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe0f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe100, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe108, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe110, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe118, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe120, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe128, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe130, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe138, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe140, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe148, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe150, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe158, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe160, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe168, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe170, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe178, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe180, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe188, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe190, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe198, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe1f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe200, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe208, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe210, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe218, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe220, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe228, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe230, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe238, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe240, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe248, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe250, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe258, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe260, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe268, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe270, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe278, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe280, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe288, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe290, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe298, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe2f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe300, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe308, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe310, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe318, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe320, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe328, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe330, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe338, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe340, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe348, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe350, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe358, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe360, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe368, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe370, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe378, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe380, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe388, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe390, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe398, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe3f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe400, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe408, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe410, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe418, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe420, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe428, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe430, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe438, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe440, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe448, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe450, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe458, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe460, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe468, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe470, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe478, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe480, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe488, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe490, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe498, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe4f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe500, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe508, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe510, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe518, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe520, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe528, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe530, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe538, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe540, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe548, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe550, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe558, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe560, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe568, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe570, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe578, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe580, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe588, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe590, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe598, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe5f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe600, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe608, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe610, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe618, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe620, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe628, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe630, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe638, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe640, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe648, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe650, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe658, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe660, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe668, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe670, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe678, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe680, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe688, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe690, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe698, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe6f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe700, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe708, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe710, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe718, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe720, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe728, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe730, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe738, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe740, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe748, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe750, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe758, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe760, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe768, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe770, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe778, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe780, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe788, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe790, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe798, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe7f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe800, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe808, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe810, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe818, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe820, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe828, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe830, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe838, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe840, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe848, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe850, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe858, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe860, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe868, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe870, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe878, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe880, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe888, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe890, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe898, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe8f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe900, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe908, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe910, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe918, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe920, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe928, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe930, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe938, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe940, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe948, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe950, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe958, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe960, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe968, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe970, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe978, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe980, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe988, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe990, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe998, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9a0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9a8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9b0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9b8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9c0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9c8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9d0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9d8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9e0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9e8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9f0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xe9f8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea00, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea08, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea10, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea18, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea20, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea28, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea30, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea38, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea40, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea48, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea50, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea58, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea60, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea68, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea70, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea78, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea80, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea88, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea90, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xea98, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeaa0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeaa8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeab0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeab8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeac0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeac8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xead0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xead8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeae0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeae8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeaf0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeaf8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb00, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb08, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb10, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb18, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb20, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb28, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb30, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb38, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb40, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb48, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb50, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb58, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb60, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb68, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb70, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb78, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb80, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb88, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb90, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeb98, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeba0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeba8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xebb0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xebb8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xebc0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xebc8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xebd0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xebd8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xebe0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xebe8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xebf0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xebf8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec00, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec08, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec10, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec18, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec20, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec28, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec30, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec38, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec40, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec48, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec50, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec58, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec60, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec68, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec70, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec78, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec80, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec88, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec90, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xec98, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeca0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeca8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xecb0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xecb8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xecc0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xecc8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xecd0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xecd8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xece0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xece8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xecf0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xecf8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed00, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed08, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed10, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed18, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed20, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed28, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed30, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed38, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed40, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed48, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed50, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed58, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed60, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed68, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed70, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed78, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed80, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed88, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed90, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xed98, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeda0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeda8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xedb0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xedb8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xedc0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xedc8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xedd0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xedd8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xede0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xede8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xedf0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xedf8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee00, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee08, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee10, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee18, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee20, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee28, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee30, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee38, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee40, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee48, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee50, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee58, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee60, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee68, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee70, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee78, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee80, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee88, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee90, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xee98, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeea0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeea8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeeb0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeeb8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeec0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeec8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeed0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeed8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeee0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeee8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeef0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeef8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef00, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef08, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef10, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef18, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef20, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef28, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef30, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef38, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef40, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef48, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef50, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef58, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef60, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef68, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef70, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef78, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef80, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef88, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef90, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xef98, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xefa0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xefa8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xefb0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xefb8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xefc0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xefc8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xefd0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xefd8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xefe0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xefe8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeff0, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_L", 0xeff8, 0 },
|
|
{ "MultiListen3", 28, 1 },
|
|
{ "MultiListen2", 27, 1 },
|
|
{ "MultiListen1", 26, 1 },
|
|
{ "MultiListen0", 25, 1 },
|
|
{ "Priority3", 22, 3 },
|
|
{ "Priority2", 19, 3 },
|
|
{ "Priority1", 16, 3 },
|
|
{ "Priority0", 13, 3 },
|
|
{ "Valid", 12, 1 },
|
|
{ "Replicate", 11, 1 },
|
|
{ "PF", 8, 3 },
|
|
{ "VF_Valid", 7, 1 },
|
|
{ "VF", 0, 7 },
|
|
{ "MPS_CLS_SRAM_H", 0xe004, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe00c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe014, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe01c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe024, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe02c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe034, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe03c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe044, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe04c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe054, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe05c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe064, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe06c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe074, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe07c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe084, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe08c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe094, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe09c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe0fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe104, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe10c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe114, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe11c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe124, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe12c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe134, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe13c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe144, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe14c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe154, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe15c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe164, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe16c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe174, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe17c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe184, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe18c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe194, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe19c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe1fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe204, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe20c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe214, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe21c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe224, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe22c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe234, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe23c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe244, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe24c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe254, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe25c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe264, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe26c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe274, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe27c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe284, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe28c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe294, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe29c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe2fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe304, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe30c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe314, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe31c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe324, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe32c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe334, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe33c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe344, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe34c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe354, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe35c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe364, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe36c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe374, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe37c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe384, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe38c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe394, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe39c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe3fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe404, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe40c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe414, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe41c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe424, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe42c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe434, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe43c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe444, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe44c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe454, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe45c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe464, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe46c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe474, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe47c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe484, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe48c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe494, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe49c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe4fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe504, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe50c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe514, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe51c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe524, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe52c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe534, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe53c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe544, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe54c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe554, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe55c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe564, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe56c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe574, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe57c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe584, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe58c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe594, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe59c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe5fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe604, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe60c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe614, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe61c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe624, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe62c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe634, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe63c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe644, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe64c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe654, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe65c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe664, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe66c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe674, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe67c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe684, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe68c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe694, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe69c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe6fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe704, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe70c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe714, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe71c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe724, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe72c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe734, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe73c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe744, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe74c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe754, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe75c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe764, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe76c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe774, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe77c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe784, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe78c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe794, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe79c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe7fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe804, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe80c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe814, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe81c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe824, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe82c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe834, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe83c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe844, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe84c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe854, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe85c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe864, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe86c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe874, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe87c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe884, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe88c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe894, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe89c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe8fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe904, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe90c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe914, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe91c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe924, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe92c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe934, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe93c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe944, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe94c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe954, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe95c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe964, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe96c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe974, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe97c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe984, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe98c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe994, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe99c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9a4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9ac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9b4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9bc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9c4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9cc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9d4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9dc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9e4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9ec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9f4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xe9fc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea04, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea0c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea14, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea1c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea24, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea2c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea34, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea3c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea44, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea4c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea54, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea5c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea64, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea6c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea74, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea7c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea84, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea8c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea94, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xea9c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeaa4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeaac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeab4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeabc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeac4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeacc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xead4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeadc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeae4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeaec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeaf4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeafc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb04, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb0c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb14, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb1c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb24, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb2c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb34, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb3c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb44, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb4c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb54, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb5c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb64, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb6c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb74, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb7c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb84, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb8c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb94, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeb9c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeba4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xebac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xebb4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xebbc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xebc4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xebcc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xebd4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xebdc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xebe4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xebec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xebf4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xebfc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec04, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec0c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec14, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec1c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec24, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec2c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec34, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec3c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec44, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec4c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec54, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec5c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec64, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec6c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec74, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec7c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec84, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec8c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec94, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xec9c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeca4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xecac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xecb4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xecbc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xecc4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeccc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xecd4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xecdc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xece4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xecec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xecf4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xecfc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed04, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed0c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed14, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed1c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed24, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed2c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed34, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed3c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed44, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed4c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed54, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed5c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed64, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed6c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed74, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed7c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed84, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed8c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed94, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xed9c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeda4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xedac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xedb4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xedbc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xedc4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xedcc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xedd4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeddc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xede4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xedec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xedf4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xedfc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee04, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee0c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee14, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee1c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee24, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee2c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee34, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee3c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee44, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee4c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee54, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee5c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee64, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee6c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee74, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee7c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee84, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee8c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee94, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xee9c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeea4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeeac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeeb4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeebc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeec4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeecc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeed4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeedc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeee4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeeec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeef4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeefc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef04, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef0c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef14, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef1c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef24, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef2c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef34, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef3c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef44, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef4c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef54, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef5c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef64, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef6c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef74, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef7c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef84, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef8c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef94, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xef9c, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefa4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefac, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefb4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefbc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefc4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefcc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefd4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefdc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefe4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xefec, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeff4, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_SRAM_H", 0xeffc, 0 },
|
|
{ "MacParity1", 9, 1 },
|
|
{ "MacParity0", 8, 1 },
|
|
{ "MacParityMaskSize", 4, 4 },
|
|
{ "PortMap", 0, 4 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf000, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf010, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf020, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf030, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf040, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf050, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf060, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf070, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf080, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf090, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf0a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf0b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf0c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf0d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf0e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf0f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf100, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf110, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf120, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf130, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf140, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf150, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf160, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf170, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf180, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf190, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf1a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf1b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf1c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf1d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf1e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf1f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf200, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf210, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf220, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf230, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf240, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf250, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf260, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf270, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf280, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf290, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf2a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf2b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf2c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf2d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf2e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf2f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf300, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf310, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf320, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf330, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf340, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf350, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf360, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf370, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf380, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf390, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf3a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf3b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf3c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf3d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf3e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf3f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf400, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf410, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf420, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf430, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf440, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf450, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf460, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf470, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf480, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf490, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf4a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf4b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf4c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf4d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf4e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf4f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf500, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf510, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf520, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf530, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf540, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf550, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf560, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf570, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf580, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf590, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf5a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf5b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf5c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf5d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf5e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf5f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf600, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf610, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf620, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf630, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf640, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf650, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf660, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf670, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf680, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf690, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf6a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf6b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf6c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf6d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf6e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf6f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf700, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf710, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf720, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf730, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf740, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf750, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf760, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf770, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf780, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf790, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf7a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf7b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf7c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf7d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf7e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf7f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf800, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf810, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf820, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf830, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf840, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf850, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf860, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf870, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf880, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf890, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf8a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf8b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf8c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf8d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf8e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf8f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf900, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf910, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf920, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf930, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf940, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf950, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf960, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf970, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf980, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf990, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf9a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf9b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf9c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf9d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf9e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xf9f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfa90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfaa0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfab0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfac0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfad0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfae0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfaf0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfb90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfba0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfbb0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfbc0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfbd0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfbe0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfbf0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfc90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfca0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfcb0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfcc0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfcd0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfce0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfcf0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfd90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfda0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfdb0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfdc0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfdd0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfde0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfdf0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfe90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfea0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfeb0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfec0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfed0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfee0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfef0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xff90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xffa0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xffb0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xffc0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xffd0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xffe0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0xfff0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10000, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10010, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10020, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10030, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10040, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10050, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10060, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10070, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10080, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10090, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x100a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x100b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x100c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x100d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x100e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x100f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10100, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10110, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10120, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10130, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10140, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10150, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10160, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10170, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10180, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10190, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x101a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x101b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x101c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x101d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x101e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x101f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10200, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10210, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10220, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10230, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10240, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10250, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10260, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10270, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10280, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10290, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x102a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x102b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x102c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x102d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x102e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x102f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10300, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10310, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10320, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10330, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10340, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10350, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10360, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10370, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10380, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10390, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x103a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x103b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x103c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x103d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x103e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x103f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10400, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10410, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10420, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10430, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10440, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10450, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10460, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10470, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10480, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10490, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x104a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x104b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x104c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x104d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x104e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x104f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10500, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10510, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10520, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10530, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10540, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10550, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10560, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10570, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10580, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10590, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x105a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x105b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x105c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x105d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x105e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x105f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10600, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10610, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10620, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10630, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10640, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10650, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10660, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10670, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10680, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10690, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x106a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x106b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x106c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x106d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x106e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x106f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10700, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10710, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10720, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10730, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10740, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10750, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10760, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10770, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10780, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10790, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x107a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x107b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x107c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x107d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x107e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x107f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10800, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10810, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10820, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10830, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10840, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10850, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10860, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10870, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10880, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10890, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x108a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x108b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x108c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x108d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x108e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x108f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10900, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10910, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10920, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10930, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10940, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10950, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10960, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10970, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10980, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10990, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x109a0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x109b0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x109c0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x109d0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x109e0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x109f0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10a90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10aa0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ab0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ac0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ad0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ae0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10af0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10b90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ba0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10bb0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10bc0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10bd0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10be0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10bf0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10c90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ca0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10cb0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10cc0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10cd0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ce0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10cf0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10d90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10da0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10db0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10dc0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10dd0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10de0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10df0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10e90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ea0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10eb0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ec0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ed0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ee0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ef0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f00, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f10, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f20, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f30, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f40, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f50, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f60, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f70, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f80, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10f90, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10fa0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10fb0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10fc0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10fd0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10fe0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_L", 0x10ff0, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf004, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf014, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf024, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf034, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf044, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf054, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf064, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf074, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf084, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf094, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf0a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf0b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf0c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf0d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf0e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf0f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf104, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf114, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf124, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf134, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf144, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf154, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf164, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf174, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf184, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf194, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf1a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf1b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf1c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf1d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf1e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf1f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf204, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf214, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf224, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf234, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf244, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf254, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf264, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf274, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf284, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf294, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf2a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf2b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf2c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf2d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf2e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf2f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf304, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf314, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf324, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf334, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf344, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf354, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf364, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf374, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf384, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf394, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf3a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf3b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf3c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf3d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf3e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf3f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf404, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf414, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf424, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf434, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf444, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf454, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf464, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf474, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf484, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf494, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf4a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf4b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf4c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf4d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf4e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf4f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf504, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf514, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf524, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf534, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf544, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf554, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf564, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf574, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf584, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf594, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf5a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf5b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf5c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf5d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf5e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf5f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf604, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf614, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf624, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf634, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf644, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf654, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf664, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf674, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf684, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf694, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf6a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf6b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf6c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf6d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf6e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf6f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf704, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf714, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf724, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf734, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf744, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf754, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf764, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf774, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf784, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf794, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf7a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf7b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf7c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf7d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf7e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf7f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf804, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf814, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf824, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf834, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf844, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf854, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf864, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf874, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf884, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf894, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf8a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf8b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf8c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf8d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf8e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf8f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf904, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf914, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf924, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf934, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf944, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf954, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf964, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf974, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf984, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf994, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf9a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf9b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf9c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf9d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf9e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xf9f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfa94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfaa4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfab4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfac4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfad4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfae4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfaf4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfb94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfba4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfbb4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfbc4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfbd4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfbe4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfbf4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfc94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfca4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfcb4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfcc4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfcd4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfce4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfcf4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfd94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfda4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfdb4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfdc4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfdd4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfde4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfdf4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfe94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfea4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfeb4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfec4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfed4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfee4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfef4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xff94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xffa4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xffb4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xffc4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xffd4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xffe4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0xfff4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10004, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10014, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10024, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10034, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10044, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10054, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10064, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10074, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10084, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10094, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x100a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x100b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x100c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x100d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x100e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x100f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10104, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10114, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10124, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10134, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10144, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10154, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10164, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10174, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10184, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10194, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x101a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x101b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x101c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x101d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x101e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x101f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10204, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10214, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10224, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10234, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10244, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10254, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10264, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10274, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10284, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10294, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x102a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x102b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x102c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x102d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x102e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x102f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10304, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10314, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10324, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10334, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10344, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10354, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10364, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10374, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10384, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10394, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x103a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x103b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x103c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x103d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x103e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x103f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10404, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10414, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10424, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10434, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10444, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10454, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10464, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10474, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10484, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10494, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x104a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x104b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x104c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x104d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x104e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x104f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10504, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10514, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10524, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10534, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10544, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10554, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10564, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10574, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10584, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10594, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x105a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x105b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x105c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x105d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x105e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x105f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10604, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10614, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10624, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10634, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10644, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10654, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10664, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10674, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10684, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10694, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x106a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x106b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x106c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x106d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x106e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x106f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10704, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10714, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10724, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10734, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10744, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10754, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10764, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10774, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10784, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10794, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x107a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x107b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x107c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x107d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x107e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x107f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10804, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10814, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10824, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10834, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10844, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10854, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10864, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10874, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10884, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10894, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x108a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x108b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x108c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x108d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x108e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x108f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10904, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10914, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10924, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10934, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10944, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10954, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10964, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10974, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10984, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10994, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x109a4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x109b4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x109c4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x109d4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x109e4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x109f4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10a94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10aa4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ab4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ac4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ad4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ae4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10af4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10b94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ba4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10bb4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10bc4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10bd4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10be4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10bf4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10c94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ca4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10cb4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10cc4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10cd4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ce4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10cf4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10d94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10da4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10db4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10dc4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10dd4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10de4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10df4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10e94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ea4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10eb4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ec4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ed4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ee4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ef4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f04, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f14, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f24, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f34, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f44, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f54, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f64, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f74, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f84, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10f94, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10fa4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10fb4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10fc4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10fd4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10fe4, 0 },
|
|
{ "MPS_CLS_TCAM_Y_H", 0x10ff4, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf008, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf018, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf028, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf038, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf048, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf058, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf068, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf078, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf088, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf098, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf0a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf0b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf0c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf0d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf0e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf0f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf108, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf118, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf128, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf138, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf148, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf158, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf168, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf178, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf188, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf198, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf1a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf1b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf1c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf1d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf1e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf1f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf208, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf218, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf228, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf238, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf248, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf258, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf268, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf278, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf288, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf298, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf2a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf2b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf2c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf2d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf2e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf2f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf308, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf318, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf328, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf338, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf348, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf358, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf368, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf378, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf388, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf398, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf3a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf3b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf3c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf3d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf3e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf3f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf408, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf418, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf428, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf438, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf448, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf458, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf468, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf478, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf488, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf498, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf4a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf4b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf4c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf4d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf4e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf4f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf508, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf518, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf528, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf538, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf548, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf558, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf568, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf578, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf588, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf598, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf5a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf5b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf5c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf5d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf5e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf5f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf608, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf618, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf628, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf638, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf648, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf658, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf668, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf678, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf688, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf698, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf6a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf6b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf6c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf6d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf6e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf6f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf708, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf718, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf728, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf738, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf748, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf758, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf768, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf778, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf788, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf798, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf7a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf7b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf7c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf7d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf7e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf7f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf808, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf818, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf828, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf838, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf848, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf858, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf868, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf878, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf888, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf898, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf8a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf8b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf8c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf8d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf8e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf8f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf908, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf918, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf928, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf938, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf948, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf958, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf968, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf978, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf988, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf998, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf9a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf9b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf9c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf9d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf9e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xf9f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfa98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfaa8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfab8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfac8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfad8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfae8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfaf8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfb98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfba8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfbb8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfbc8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfbd8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfbe8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfbf8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfc98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfca8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfcb8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfcc8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfcd8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfce8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfcf8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfd98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfda8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfdb8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfdc8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfdd8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfde8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfdf8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfe98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfea8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfeb8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfec8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfed8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfee8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfef8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xff98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xffa8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xffb8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xffc8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xffd8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xffe8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0xfff8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10008, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10018, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10028, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10038, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10048, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10058, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10068, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10078, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10088, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10098, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x100a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x100b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x100c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x100d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x100e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x100f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10108, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10118, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10128, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10138, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10148, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10158, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10168, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10178, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10188, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10198, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x101a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x101b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x101c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x101d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x101e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x101f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10208, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10218, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10228, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10238, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10248, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10258, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10268, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10278, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10288, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10298, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x102a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x102b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x102c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x102d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x102e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x102f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10308, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10318, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10328, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10338, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10348, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10358, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10368, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10378, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10388, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10398, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x103a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x103b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x103c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x103d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x103e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x103f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10408, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10418, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10428, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10438, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10448, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10458, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10468, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10478, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10488, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10498, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x104a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x104b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x104c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x104d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x104e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x104f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10508, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10518, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10528, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10538, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10548, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10558, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10568, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10578, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10588, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10598, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x105a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x105b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x105c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x105d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x105e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x105f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10608, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10618, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10628, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10638, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10648, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10658, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10668, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10678, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10688, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10698, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x106a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x106b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x106c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x106d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x106e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x106f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10708, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10718, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10728, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10738, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10748, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10758, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10768, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10778, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10788, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10798, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x107a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x107b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x107c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x107d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x107e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x107f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10808, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10818, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10828, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10838, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10848, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10858, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10868, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10878, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10888, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10898, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x108a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x108b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x108c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x108d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x108e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x108f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10908, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10918, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10928, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10938, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10948, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10958, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10968, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10978, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10988, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10998, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x109a8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x109b8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x109c8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x109d8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x109e8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x109f8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10a98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10aa8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ab8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ac8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ad8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ae8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10af8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10b98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ba8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10bb8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10bc8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10bd8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10be8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10bf8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10c98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ca8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10cb8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10cc8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10cd8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ce8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10cf8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10d98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10da8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10db8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10dc8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10dd8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10de8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10df8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10e98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ea8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10eb8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ec8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ed8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ee8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ef8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f08, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f18, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f28, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f38, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f48, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f58, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f68, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f78, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f88, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10f98, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10fa8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10fb8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10fc8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10fd8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10fe8, 0 },
|
|
{ "MPS_CLS_TCAM_X_L", 0x10ff8, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf00c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf01c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf02c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf03c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf04c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf05c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf06c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf07c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf08c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf09c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf0ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf0bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf0cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf0dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf0ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf0fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf10c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf11c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf12c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf13c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf14c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf15c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf16c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf17c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf18c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf19c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf1ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf1bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf1cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf1dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf1ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf1fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf20c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf21c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf22c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf23c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf24c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf25c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf26c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf27c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf28c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf29c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf2ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf2bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf2cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf2dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf2ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf2fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf30c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf31c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf32c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf33c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf34c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf35c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf36c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf37c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf38c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf39c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf3ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf3bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf3cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf3dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf3ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf3fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf40c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf41c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf42c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf43c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf44c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf45c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf46c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf47c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf48c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf49c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf4ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf4bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf4cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf4dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf4ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf4fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf50c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf51c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf52c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf53c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf54c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf55c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf56c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf57c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf58c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf59c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf5ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf5bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf5cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf5dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf5ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf5fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf60c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf61c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf62c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf63c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf64c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf65c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf66c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf67c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf68c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf69c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf6ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf6bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf6cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf6dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf6ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf6fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf70c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf71c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf72c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf73c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf74c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf75c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf76c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf77c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf78c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf79c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf7ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf7bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf7cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf7dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf7ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf7fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf80c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf81c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf82c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf83c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf84c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf85c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf86c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf87c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf88c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf89c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf8ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf8bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf8cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf8dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf8ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf8fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf90c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf91c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf92c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf93c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf94c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf95c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf96c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf97c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf98c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf99c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf9ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf9bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf9cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf9dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf9ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xf9fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfa9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfaac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfabc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfacc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfadc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfaec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfafc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfb9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfbac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfbbc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfbcc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfbdc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfbec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfbfc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfc9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfcac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfcbc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfccc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfcdc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfcec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfcfc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfd9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfdac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfdbc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfdcc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfddc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfdec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfdfc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfe9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfeac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfebc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfecc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfedc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfeec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfefc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xff9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xffac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xffbc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xffcc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xffdc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xffec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0xfffc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1000c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1001c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1002c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1003c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1004c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1005c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1006c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1007c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1008c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1009c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x100ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x100bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x100cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x100dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x100ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x100fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1010c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1011c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1012c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1013c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1014c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1015c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1016c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1017c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1018c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1019c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x101ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x101bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x101cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x101dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x101ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x101fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1020c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1021c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1022c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1023c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1024c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1025c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1026c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1027c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1028c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1029c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x102ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x102bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x102cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x102dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x102ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x102fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1030c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1031c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1032c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1033c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1034c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1035c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1036c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1037c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1038c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1039c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x103ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x103bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x103cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x103dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x103ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x103fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1040c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1041c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1042c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1043c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1044c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1045c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1046c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1047c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1048c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1049c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x104ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x104bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x104cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x104dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x104ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x104fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1050c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1051c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1052c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1053c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1054c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1055c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1056c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1057c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1058c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1059c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x105ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x105bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x105cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x105dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x105ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x105fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1060c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1061c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1062c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1063c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1064c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1065c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1066c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1067c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1068c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1069c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x106ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x106bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x106cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x106dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x106ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x106fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1070c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1071c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1072c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1073c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1074c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1075c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1076c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1077c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1078c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1079c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x107ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x107bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x107cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x107dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x107ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x107fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1080c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1081c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1082c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1083c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1084c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1085c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1086c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1087c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1088c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1089c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x108ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x108bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x108cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x108dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x108ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x108fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1090c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1091c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1092c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1093c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1094c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1095c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1096c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1097c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1098c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x1099c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x109ac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x109bc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x109cc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x109dc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x109ec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x109fc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10a9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10aac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10abc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10acc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10adc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10aec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10afc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10b9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10bac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10bbc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10bcc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10bdc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10bec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10bfc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10c9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10cac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10cbc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10ccc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10cdc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10cec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10cfc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10d9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10dac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10dbc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10dcc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10ddc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10dec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10dfc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10e9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10eac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10ebc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10ecc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10edc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10eec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10efc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f0c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f1c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f2c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f3c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f4c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f5c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f6c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f7c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f8c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10f9c, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10fac, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10fbc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10fcc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10fdc, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10fec, 0 },
|
|
{ "MPS_CLS_TCAM_X_H", 0x10ffc, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_cpl_switch_regs[] = {
|
|
{ "CPL_SWITCH_CNTRL", 0x19040, 0 },
|
|
{ "cpl_pkt_tid", 8, 24 },
|
|
{ "cim_split_enable", 6, 1 },
|
|
{ "cim_truncate_enable", 5, 1 },
|
|
{ "cim_to_up_full_size", 4, 1 },
|
|
{ "cpu_no_enable", 3, 1 },
|
|
{ "switch_table_enable", 2, 1 },
|
|
{ "sge_enable", 1, 1 },
|
|
{ "cim_enable", 0, 1 },
|
|
{ "CPL_SWITCH_TBL_IDX", 0x19044, 0 },
|
|
{ "CPL_SWITCH_TBL_DATA", 0x19048, 0 },
|
|
{ "CPL_SWITCH_ZERO_ERROR", 0x1904c, 0 },
|
|
{ "zero_cmd_ch1", 8, 8 },
|
|
{ "zero_cmd_ch0", 0, 8 },
|
|
{ "CPL_INTR_ENABLE", 0x19050, 0 },
|
|
{ "perr_cpl_128to128_1", 7, 1 },
|
|
{ "perr_cpl_128to128_0", 6, 1 },
|
|
{ "cim_op_map_perr", 5, 1 },
|
|
{ "cim_ovfl_error", 4, 1 },
|
|
{ "tp_framing_error", 3, 1 },
|
|
{ "sge_framing_error", 2, 1 },
|
|
{ "cim_framing_error", 1, 1 },
|
|
{ "zero_switch_error", 0, 1 },
|
|
{ "CPL_INTR_CAUSE", 0x19054, 0 },
|
|
{ "perr_cpl_128to128_1", 7, 1 },
|
|
{ "perr_cpl_128to128_0", 6, 1 },
|
|
{ "cim_op_map_perr", 5, 1 },
|
|
{ "cim_ovfl_error", 4, 1 },
|
|
{ "tp_framing_error", 3, 1 },
|
|
{ "sge_framing_error", 2, 1 },
|
|
{ "cim_framing_error", 1, 1 },
|
|
{ "zero_switch_error", 0, 1 },
|
|
{ "CPL_MAP_TBL_IDX", 0x19058, 0 },
|
|
{ "cim_split_opcode_program", 8, 1 },
|
|
{ "cpl_map_tbl_idx", 0, 8 },
|
|
{ "CPL_MAP_TBL_DATA", 0x1905c, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_smb_regs[] = {
|
|
{ "SMB_GLOBAL_TIME_CFG", 0x19060, 0 },
|
|
{ "MacroCntCfg", 8, 5 },
|
|
{ "MicroCntCfg", 0, 8 },
|
|
{ "SMB_MST_TIMEOUT_CFG", 0x19064, 0 },
|
|
{ "SMB_MST_CTL_CFG", 0x19068, 0 },
|
|
{ "MstFifoDbg", 31, 1 },
|
|
{ "MstFifoDbgClr", 30, 1 },
|
|
{ "MstRxByteCfg", 12, 6 },
|
|
{ "MstTxByteCfg", 6, 6 },
|
|
{ "MstReset", 1, 1 },
|
|
{ "MstCtlEn", 0, 1 },
|
|
{ "SMB_MST_CTL_STS", 0x1906c, 0 },
|
|
{ "MstRxByteCnt", 12, 6 },
|
|
{ "MstTxByteCnt", 6, 6 },
|
|
{ "MstBusySts", 0, 1 },
|
|
{ "SMB_MST_TX_FIFO_RDWR", 0x19070, 0 },
|
|
{ "SMB_MST_RX_FIFO_RDWR", 0x19074, 0 },
|
|
{ "SMB_SLV_TIMEOUT_CFG", 0x19078, 0 },
|
|
{ "SMB_SLV_CTL_CFG", 0x1907c, 0 },
|
|
{ "SlvFifoDbg", 31, 1 },
|
|
{ "SlvFifoDbgClr", 30, 1 },
|
|
{ "SlvCrcOutBitInv", 21, 1 },
|
|
{ "SlvCrcOutBitRev", 20, 1 },
|
|
{ "SlvCrcInBitRev", 19, 1 },
|
|
{ "SlvCrcPreset", 11, 8 },
|
|
{ "SlvAddrCfg", 4, 7 },
|
|
{ "SlvAlrtSet", 2, 1 },
|
|
{ "SlvReset", 1, 1 },
|
|
{ "SlvCtlEn", 0, 1 },
|
|
{ "SMB_SLV_CTL_STS", 0x19080, 0 },
|
|
{ "SlvFifoTxCnt", 12, 6 },
|
|
{ "SlvFifoCnt", 6, 6 },
|
|
{ "SlvAlrtSts", 2, 1 },
|
|
{ "SlvBusySts", 0, 1 },
|
|
{ "SMB_SLV_FIFO_RDWR", 0x19084, 0 },
|
|
{ "SMB_INT_ENABLE", 0x1908c, 0 },
|
|
{ "MstTxFifoParEn", 21, 1 },
|
|
{ "MstRxFifoParEn", 20, 1 },
|
|
{ "SlvFifoParEn", 19, 1 },
|
|
{ "SlvUnExpBusStopEn", 18, 1 },
|
|
{ "SlvUnExpBusStartEn", 17, 1 },
|
|
{ "SlvCommandCodeInvEn", 16, 1 },
|
|
{ "SlvByteCntErrEn", 15, 1 },
|
|
{ "SlvUnExpAckMstEn", 14, 1 },
|
|
{ "SlvUnExpNackMstEn", 13, 1 },
|
|
{ "SlvNoBusStopEn", 12, 1 },
|
|
{ "SlvNoRepStartEn", 11, 1 },
|
|
{ "SlvRxAddrIntEn", 10, 1 },
|
|
{ "SlvRxPecErrIntEn", 9, 1 },
|
|
{ "SlvPrepToArpIntEn", 8, 1 },
|
|
{ "SlvTimeOutIntEn", 7, 1 },
|
|
{ "SlvErrIntEn", 6, 1 },
|
|
{ "SlvDoneIntEn", 5, 1 },
|
|
{ "SlvRxRdyIntEn", 4, 1 },
|
|
{ "MstTimeOutIntEn", 3, 1 },
|
|
{ "MstNAckIntEn", 2, 1 },
|
|
{ "MstLostArbIntEn", 1, 1 },
|
|
{ "MstDoneIntEn", 0, 1 },
|
|
{ "SMB_INT_CAUSE", 0x19090, 0 },
|
|
{ "MstTxFifoParInt", 21, 1 },
|
|
{ "MstRxFifoParInt", 20, 1 },
|
|
{ "SlvFifoParInt", 19, 1 },
|
|
{ "SlvUnExpBusStopInt", 18, 1 },
|
|
{ "SlvUnExpBusStartInt", 17, 1 },
|
|
{ "SlvCommandCodeInvInt", 16, 1 },
|
|
{ "SlvByteCntErrInt", 15, 1 },
|
|
{ "SlvUnExpAckMstInt", 14, 1 },
|
|
{ "SlvUnExpNackMstInt", 13, 1 },
|
|
{ "SlvNoBusStopInt", 12, 1 },
|
|
{ "SlvNoRepStartInt", 11, 1 },
|
|
{ "SlvRxAddrInt", 10, 1 },
|
|
{ "SlvRxPecErrInt", 9, 1 },
|
|
{ "SlvPrepToArpInt", 8, 1 },
|
|
{ "SlvTimeOutInt", 7, 1 },
|
|
{ "SlvErrInt", 6, 1 },
|
|
{ "SlvDoneInt", 5, 1 },
|
|
{ "SlvRxRdyInt", 4, 1 },
|
|
{ "MstTimeOutInt", 3, 1 },
|
|
{ "MstNAckInt", 2, 1 },
|
|
{ "MstLostArbInt", 1, 1 },
|
|
{ "MstDoneInt", 0, 1 },
|
|
{ "SMB_DEBUG_DATA", 0x19094, 0 },
|
|
{ "DebugDataH", 16, 16 },
|
|
{ "DebugDataL", 0, 16 },
|
|
{ "SMB_PERR_EN", 0x19098, 0 },
|
|
{ "MstTxFifo", 21, 1 },
|
|
{ "MstRxFifo", 19, 1 },
|
|
{ "SlvFifo", 18, 1 },
|
|
{ "MstTxFifoPerrEn", 2, 1 },
|
|
{ "MstRxFifoPerrEn", 1, 1 },
|
|
{ "SlvFifoPerrEn", 0, 1 },
|
|
{ "SMB_PERR_INJ", 0x1909c, 0 },
|
|
{ "MstTxInjDataErr", 3, 1 },
|
|
{ "MstRxInjDataErr", 2, 1 },
|
|
{ "SlvInjDataErr", 1, 1 },
|
|
{ "FifoInjDataErrEn", 0, 1 },
|
|
{ "SMB_SLV_ARP_CTL", 0x190a0, 0 },
|
|
{ "ArpCommandCode", 2, 8 },
|
|
{ "ArpAddrRes", 1, 1 },
|
|
{ "ArpAddrVal", 0, 1 },
|
|
{ "SMB_ARP_UDID0", 0x190a4, 0 },
|
|
{ "SMB_ARP_UDID1", 0x190a8, 0 },
|
|
{ "SubsystemVendorID", 16, 16 },
|
|
{ "SubsystemDeviceID", 0, 16 },
|
|
{ "SMB_ARP_UDID2", 0x190ac, 0 },
|
|
{ "DeviceID", 16, 16 },
|
|
{ "Interface", 0, 16 },
|
|
{ "SMB_ARP_UDID3", 0x190b0, 0 },
|
|
{ "DeviceCap", 24, 8 },
|
|
{ "VersionID", 16, 8 },
|
|
{ "VendorID", 0, 16 },
|
|
{ "SMB_SLV_AUX_ADDR0", 0x190b4, 0 },
|
|
{ "AuxAddr0Val", 6, 1 },
|
|
{ "AuxAddr0", 0, 6 },
|
|
{ "SMB_SLV_AUX_ADDR1", 0x190b8, 0 },
|
|
{ "AuxAddr1Val", 6, 1 },
|
|
{ "AuxAddr1", 0, 6 },
|
|
{ "SMB_SLV_AUX_ADDR2", 0x190bc, 0 },
|
|
{ "AuxAddr2Val", 6, 1 },
|
|
{ "AuxAddr2", 0, 6 },
|
|
{ "SMB_SLV_AUX_ADDR3", 0x190c0, 0 },
|
|
{ "AuxAddr3Val", 6, 1 },
|
|
{ "AuxAddr3", 0, 6 },
|
|
{ "SMB_COMMAND_CODE0", 0x190c4, 0 },
|
|
{ "SMB_COMMAND_CODE1", 0x190c8, 0 },
|
|
{ "SMB_COMMAND_CODE2", 0x190cc, 0 },
|
|
{ "SMB_COMMAND_CODE3", 0x190d0, 0 },
|
|
{ "SMB_COMMAND_CODE4", 0x190d4, 0 },
|
|
{ "SMB_COMMAND_CODE5", 0x190d8, 0 },
|
|
{ "SMB_COMMAND_CODE6", 0x190dc, 0 },
|
|
{ "SMB_COMMAND_CODE7", 0x190e0, 0 },
|
|
{ "SMB_MICRO_CNT_CLK_CFG", 0x190e4, 0 },
|
|
{ "MacroCntClkCfg", 8, 5 },
|
|
{ "MicroCntClkCfg", 0, 8 },
|
|
{ "SMB_CTL_STATUS", 0x190e8, 0 },
|
|
{ "MstBusBusy", 2, 1 },
|
|
{ "SlvBusBusy", 1, 1 },
|
|
{ "BusBusy", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_i2cm_regs[] = {
|
|
{ "I2CM_CFG", 0x190f0, 0 },
|
|
{ "I2CM_DATA", 0x190f4, 0 },
|
|
{ "I2CM_OP", 0x190f8, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Ack", 30, 1 },
|
|
{ "Cont", 1, 1 },
|
|
{ "Op", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_mi_regs[] = {
|
|
{ "MI_CFG", 0x19100, 0 },
|
|
{ "T4_St", 14, 1 },
|
|
{ "ClkDiv", 5, 8 },
|
|
{ "St", 3, 2 },
|
|
{ "PreEn", 2, 1 },
|
|
{ "MDIInv", 1, 1 },
|
|
{ "MDIO_1P2V_Sel", 0, 1 },
|
|
{ "MI_ADDR", 0x19104, 0 },
|
|
{ "PhyAddr", 5, 5 },
|
|
{ "RegAddr", 0, 5 },
|
|
{ "MI_DATA", 0x19108, 0 },
|
|
{ "MI_OP", 0x1910c, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "St", 3, 2 },
|
|
{ "Inc", 2, 1 },
|
|
{ "Op", 0, 2 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_uart_regs[] = {
|
|
{ "UART_CONFIG", 0x19110, 0 },
|
|
{ "StopBits", 22, 2 },
|
|
{ "Parity", 20, 2 },
|
|
{ "DataBits", 16, 4 },
|
|
{ "ClkDiv", 0, 12 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_pmu_regs[] = {
|
|
{ "PMU_PART_CG_PWRMODE", 0x19120, 0 },
|
|
{ "SGE_Part_CGEn", 19, 1 },
|
|
{ "PDP_Part_CGEn", 18, 1 },
|
|
{ "TP_Part_CGEn", 17, 1 },
|
|
{ "EDC0_Part_CGEn", 16, 1 },
|
|
{ "EDC1_Part_CGEn", 15, 1 },
|
|
{ "LE_Part_CGEn", 14, 1 },
|
|
{ "MA_Part_CGEn", 13, 1 },
|
|
{ "MC0_Part_CGEn", 12, 1 },
|
|
{ "MC1_Part_CGEn", 11, 1 },
|
|
{ "PCIE_Part_CGEn", 10, 1 },
|
|
{ "InitPowerMode", 0, 2 },
|
|
{ "PMU_SLEEPMODE_WAKEUP", 0x19124, 0 },
|
|
{ "GlobalDeepSleepEn", 6, 1 },
|
|
{ "HWWakeUpEn", 5, 1 },
|
|
{ "Port3SleepMode", 4, 1 },
|
|
{ "Port2SleepMode", 3, 1 },
|
|
{ "Port1SleepMode", 2, 1 },
|
|
{ "Port0SleepMode", 1, 1 },
|
|
{ "WakeUp", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_ulp_rx_regs[] = {
|
|
{ "ULP_RX_CTL", 0x19150, 0 },
|
|
{ "PCMD1Threshold", 24, 8 },
|
|
{ "PCMD0Threshold", 16, 8 },
|
|
{ "disable_0B_STAG_ERR", 14, 1 },
|
|
{ "RDMA_0b_wr_opcode", 10, 4 },
|
|
{ "RDMA_0b_wr_pass", 9, 1 },
|
|
{ "STAG_RQE", 8, 1 },
|
|
{ "RDMA_State_En", 7, 1 },
|
|
{ "Crc1_En", 6, 1 },
|
|
{ "RDMA_0b_wr_cqe", 5, 1 },
|
|
{ "PCIE_Atrb_En", 4, 1 },
|
|
{ "RDMA_permissive_mode", 3, 1 },
|
|
{ "PagePodME", 2, 1 },
|
|
{ "IscsiTagTcb", 1, 1 },
|
|
{ "TddpTagTcb", 0, 1 },
|
|
{ "ULP_RX_INT_ENABLE", 0x19154, 0 },
|
|
{ "SE_CNT_MISMATCH_1", 26, 1 },
|
|
{ "SE_CNT_MISMATCH_0", 25, 1 },
|
|
{ "ENABLE_CTX_1", 24, 1 },
|
|
{ "ENABLE_CTX_0", 23, 1 },
|
|
{ "ENABLE_FF", 22, 1 },
|
|
{ "ENABLE_APF_1", 21, 1 },
|
|
{ "ENABLE_APF_0", 20, 1 },
|
|
{ "ENABLE_AF_1", 19, 1 },
|
|
{ "ENABLE_AF_0", 18, 1 },
|
|
{ "ENABLE_DDPDF_1", 17, 1 },
|
|
{ "ENABLE_DDPMF_1", 16, 1 },
|
|
{ "ENABLE_MEMRF_1", 15, 1 },
|
|
{ "ENABLE_PRSDF_1", 14, 1 },
|
|
{ "ENABLE_DDPDF_0", 13, 1 },
|
|
{ "ENABLE_DDPMF_0", 12, 1 },
|
|
{ "ENABLE_MEMRF_0", 11, 1 },
|
|
{ "ENABLE_PRSDF_0", 10, 1 },
|
|
{ "ENABLE_PCMDF_1", 9, 1 },
|
|
{ "ENABLE_TPTCF_1", 8, 1 },
|
|
{ "ENABLE_DDPCF_1", 7, 1 },
|
|
{ "ENABLE_MPARF_1", 6, 1 },
|
|
{ "ENABLE_MPARC_1", 5, 1 },
|
|
{ "ENABLE_PCMDF_0", 4, 1 },
|
|
{ "ENABLE_TPTCF_0", 3, 1 },
|
|
{ "ENABLE_DDPCF_0", 2, 1 },
|
|
{ "ENABLE_MPARF_0", 1, 1 },
|
|
{ "ENABLE_MPARC_0", 0, 1 },
|
|
{ "ULP_RX_INT_CAUSE", 0x19158, 0 },
|
|
{ "SE_CNT_MISMATCH_1", 26, 1 },
|
|
{ "SE_CNT_MISMATCH_0", 25, 1 },
|
|
{ "CAUSE_CTX_1", 24, 1 },
|
|
{ "CAUSE_CTX_0", 23, 1 },
|
|
{ "CAUSE_FF", 22, 1 },
|
|
{ "CAUSE_APF_1", 21, 1 },
|
|
{ "CAUSE_APF_0", 20, 1 },
|
|
{ "CAUSE_AF_1", 19, 1 },
|
|
{ "CAUSE_AF_0", 18, 1 },
|
|
{ "CAUSE_DDPDF_1", 17, 1 },
|
|
{ "CAUSE_DDPMF_1", 16, 1 },
|
|
{ "CAUSE_MEMRF_1", 15, 1 },
|
|
{ "CAUSE_PRSDF_1", 14, 1 },
|
|
{ "CAUSE_DDPDF_0", 13, 1 },
|
|
{ "CAUSE_DDPMF_0", 12, 1 },
|
|
{ "CAUSE_MEMRF_0", 11, 1 },
|
|
{ "CAUSE_PRSDF_0", 10, 1 },
|
|
{ "CAUSE_PCMDF_1", 9, 1 },
|
|
{ "CAUSE_TPTCF_1", 8, 1 },
|
|
{ "CAUSE_DDPCF_1", 7, 1 },
|
|
{ "CAUSE_MPARF_1", 6, 1 },
|
|
{ "CAUSE_MPARC_1", 5, 1 },
|
|
{ "CAUSE_PCMDF_0", 4, 1 },
|
|
{ "CAUSE_TPTCF_0", 3, 1 },
|
|
{ "CAUSE_DDPCF_0", 2, 1 },
|
|
{ "CAUSE_MPARF_0", 1, 1 },
|
|
{ "CAUSE_MPARC_0", 0, 1 },
|
|
{ "ULP_RX_ISCSI_LLIMIT", 0x1915c, 0 },
|
|
{ "IscsiLlimit", 6, 26 },
|
|
{ "ULP_RX_ISCSI_ULIMIT", 0x19160, 0 },
|
|
{ "IscsiUlimit", 6, 26 },
|
|
{ "ULP_RX_ISCSI_TAGMASK", 0x19164, 0 },
|
|
{ "IscsiTagMask", 6, 26 },
|
|
{ "ULP_RX_ISCSI_PSZ", 0x19168, 0 },
|
|
{ "Hpz3", 24, 4 },
|
|
{ "Hpz2", 16, 4 },
|
|
{ "Hpz1", 8, 4 },
|
|
{ "Hpz0", 0, 4 },
|
|
{ "ULP_RX_TDDP_LLIMIT", 0x1916c, 0 },
|
|
{ "TddpLlimit", 6, 26 },
|
|
{ "ULP_RX_TDDP_ULIMIT", 0x19170, 0 },
|
|
{ "TddpUlimit", 6, 26 },
|
|
{ "ULP_RX_TDDP_TAGMASK", 0x19174, 0 },
|
|
{ "TddpTagMask", 6, 26 },
|
|
{ "ULP_RX_TDDP_PSZ", 0x19178, 0 },
|
|
{ "Hpz3", 24, 4 },
|
|
{ "Hpz2", 16, 4 },
|
|
{ "Hpz1", 8, 4 },
|
|
{ "Hpz0", 0, 4 },
|
|
{ "ULP_RX_STAG_LLIMIT", 0x1917c, 0 },
|
|
{ "ULP_RX_STAG_ULIMIT", 0x19180, 0 },
|
|
{ "ULP_RX_RQ_LLIMIT", 0x19184, 0 },
|
|
{ "ULP_RX_RQ_ULIMIT", 0x19188, 0 },
|
|
{ "ULP_RX_PBL_LLIMIT", 0x1918c, 0 },
|
|
{ "ULP_RX_PBL_ULIMIT", 0x19190, 0 },
|
|
{ "ULP_RX_CTX_BASE", 0x19194, 0 },
|
|
{ "ULP_RX_PERR_ENABLE", 0x1919c, 0 },
|
|
{ "PERR_SE_CNT_MISMATCH_1", 26, 1 },
|
|
{ "PERR_SE_CNT_MISMATCH_0", 25, 1 },
|
|
{ "PERR_RSVD0", 24, 1 },
|
|
{ "PERR_RSVD1", 23, 1 },
|
|
{ "PERR_ENABLE_FF", 22, 1 },
|
|
{ "PERR_ENABLE_APF_1", 21, 1 },
|
|
{ "PERR_ENABLE_APF_0", 20, 1 },
|
|
{ "PERR_ENABLE_AF_1", 19, 1 },
|
|
{ "PERR_ENABLE_AF_0", 18, 1 },
|
|
{ "PERR_ENABLE_DDPDF_1", 17, 1 },
|
|
{ "PERR_ENABLE_DDPMF_1", 16, 1 },
|
|
{ "PERR_ENABLE_MEMRF_1", 15, 1 },
|
|
{ "PERR_ENABLE_PRSDF_1", 14, 1 },
|
|
{ "PERR_ENABLE_DDPDF_0", 13, 1 },
|
|
{ "PERR_ENABLE_DDPMF_0", 12, 1 },
|
|
{ "PERR_ENABLE_MEMRF_0", 11, 1 },
|
|
{ "PERR_ENABLE_PRSDF_0", 10, 1 },
|
|
{ "PERR_ENABLE_PCMDF_1", 9, 1 },
|
|
{ "PERR_ENABLE_TPTCF_1", 8, 1 },
|
|
{ "PERR_ENABLE_DDPCF_1", 7, 1 },
|
|
{ "PERR_ENABLE_MPARF_1", 6, 1 },
|
|
{ "PERR_ENABLE_MPARC_1", 5, 1 },
|
|
{ "PERR_ENABLE_PCMDF_0", 4, 1 },
|
|
{ "PERR_ENABLE_TPTCF_0", 3, 1 },
|
|
{ "PERR_ENABLE_DDPCF_0", 2, 1 },
|
|
{ "PERR_ENABLE_MPARF_0", 1, 1 },
|
|
{ "PERR_ENABLE_MPARC_0", 0, 1 },
|
|
{ "ULP_RX_PERR_INJECT", 0x191a0, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "ULP_RX_RQUDP_LLIMIT", 0x191a4, 0 },
|
|
{ "ULP_RX_RQUDP_ULIMIT", 0x191a8, 0 },
|
|
{ "ULP_RX_CTX_ACC_CH0", 0x191ac, 0 },
|
|
{ "REQ", 21, 1 },
|
|
{ "WB", 20, 1 },
|
|
{ "TID", 0, 20 },
|
|
{ "ULP_RX_CTX_ACC_CH1", 0x191b0, 0 },
|
|
{ "REQ", 21, 1 },
|
|
{ "WB", 20, 1 },
|
|
{ "TID", 0, 20 },
|
|
{ "ULP_RX_SE_CNT_ERR", 0x191d0, 0 },
|
|
{ "ERR_CH1", 4, 4 },
|
|
{ "ERR_CH0", 0, 4 },
|
|
{ "ULP_RX_SE_CNT_CLR", 0x191d4, 0 },
|
|
{ "CLR_CH0", 4, 4 },
|
|
{ "CLR_CH1", 0, 4 },
|
|
{ "ULP_RX_SE_CNT_CH0", 0x191d8, 0 },
|
|
{ "SOP_CNT_OUT0", 28, 4 },
|
|
{ "EOP_CNT_OUT0", 24, 4 },
|
|
{ "SOP_CNT_AL0", 20, 4 },
|
|
{ "EOP_CNT_AL0", 16, 4 },
|
|
{ "SOP_CNT_MR0", 12, 4 },
|
|
{ "EOP_CNT_MR0", 8, 4 },
|
|
{ "SOP_CNT_IN0", 4, 4 },
|
|
{ "EOP_CNT_IN0", 0, 4 },
|
|
{ "ULP_RX_SE_CNT_CH1", 0x191dc, 0 },
|
|
{ "SOP_CNT_OUT1", 28, 4 },
|
|
{ "EOP_CNT_OUT1", 24, 4 },
|
|
{ "SOP_CNT_AL1", 20, 4 },
|
|
{ "EOP_CNT_AL1", 16, 4 },
|
|
{ "SOP_CNT_MR1", 12, 4 },
|
|
{ "EOP_CNT_MR1", 8, 4 },
|
|
{ "SOP_CNT_IN1", 4, 4 },
|
|
{ "EOP_CNT_IN1", 0, 4 },
|
|
{ "ULP_RX_DBG_CTL", 0x191e0, 0 },
|
|
{ "EN_DBG_H", 17, 1 },
|
|
{ "EN_DBG_L", 16, 1 },
|
|
{ "SEL_H", 8, 8 },
|
|
{ "SEL_L", 0, 8 },
|
|
{ "ULP_RX_DBG_DATAH", 0x191e4, 0 },
|
|
{ "ULP_RX_DBG_DATAL", 0x191e8, 0 },
|
|
{ "ULP_RX_LA_CHNL", 0x19238, 0 },
|
|
{ "ULP_RX_LA_CTL", 0x1923c, 0 },
|
|
{ "ULP_RX_LA_RDPTR", 0x19240, 0 },
|
|
{ "ULP_RX_LA_RDDATA", 0x19244, 0 },
|
|
{ "ULP_RX_LA_WRPTR", 0x19248, 0 },
|
|
{ "ULP_RX_LA_RESERVED", 0x1924c, 0 },
|
|
{ "ULP_RX_CQE_GEN_EN", 0x19250, 0 },
|
|
{ "Termimate_msg", 1, 1 },
|
|
{ "Terminate_with_err", 0, 1 },
|
|
{ "ULP_RX_ATOMIC_OPCODES", 0x19254, 0 },
|
|
{ "atomic_req_qno", 22, 2 },
|
|
{ "atomic_rsp_qno", 20, 2 },
|
|
{ "immediate_qno", 18, 2 },
|
|
{ "immediate_with_se_qno", 16, 2 },
|
|
{ "atomic_wr_opcode", 12, 4 },
|
|
{ "atomic_rd_opcode", 8, 4 },
|
|
{ "immediate_opcode", 4, 4 },
|
|
{ "immediate_with_se_opcode", 0, 4 },
|
|
{ "ULP_RX_T10_CRC_ENDIAN_SWITCHING", 0x19258, 0 },
|
|
{ "ULP_RX_MISC_FEATURE_ENABLE", 0x1925c, 0 },
|
|
{ "terminate_status_en", 4, 1 },
|
|
{ "multiple_pref_enable", 3, 1 },
|
|
{ "umudp_pbl_pref_enable", 2, 1 },
|
|
{ "rdma_pbl_pref_en", 1, 1 },
|
|
{ "sdc_crc_prot_en", 0, 1 },
|
|
{ "ULP_RX_CH0_CGEN", 0x19260, 0 },
|
|
{ "BYPASS_CGEN", 7, 1 },
|
|
{ "TDDP_CGEN", 6, 1 },
|
|
{ "ISCSI_CGEN", 5, 1 },
|
|
{ "RDMA_CGEN", 4, 1 },
|
|
{ "CHANNEL_CGEN", 3, 1 },
|
|
{ "All_DataPath_CGEN", 2, 1 },
|
|
{ "T10Diff_DataPath_CGEN", 1, 1 },
|
|
{ "Rdma_DataPath_CGEN", 0, 1 },
|
|
{ "ULP_RX_CH1_CGEN", 0x19264, 0 },
|
|
{ "BYPASS_CGEN", 7, 1 },
|
|
{ "TDDP_CGEN", 6, 1 },
|
|
{ "ISCSI_CGEN", 5, 1 },
|
|
{ "RDMA_CGEN", 4, 1 },
|
|
{ "CHANNEL_CGEN", 3, 1 },
|
|
{ "All_DataPath_CGEN", 2, 1 },
|
|
{ "T10Diff_DataPath_CGEN", 1, 1 },
|
|
{ "Rdma_DataPath_CGEN", 0, 1 },
|
|
{ "ULP_RX_RFE_DISABLE", 0x19268, 0 },
|
|
{ "ULP_RX_INT_ENABLE_2", 0x1926c, 0 },
|
|
{ "ULPRX2MA_IntfPerr", 8, 1 },
|
|
{ "ALN_SDC_ERR_1", 7, 1 },
|
|
{ "ALN_SDC_ERR_0", 6, 1 },
|
|
{ "PF_UNTAGGED_TPT_1", 5, 1 },
|
|
{ "PF_UNTAGGED_TPT_0", 4, 1 },
|
|
{ "PF_PBL_1", 3, 1 },
|
|
{ "PF_PBL_0", 2, 1 },
|
|
{ "DDP_HINT_1", 1, 1 },
|
|
{ "DDP_HINT_0", 0, 1 },
|
|
{ "ULP_RX_INT_CAUSE_2", 0x19270, 0 },
|
|
{ "ULPRX2MA_IntfPerr", 8, 1 },
|
|
{ "ALN_SDC_ERR_1", 7, 1 },
|
|
{ "ALN_SDC_ERR_0", 6, 1 },
|
|
{ "PF_UNTAGGED_TPT_1", 5, 1 },
|
|
{ "PF_UNTAGGED_TPT_0", 4, 1 },
|
|
{ "PF_PBL_1", 3, 1 },
|
|
{ "PF_PBL_0", 2, 1 },
|
|
{ "DDP_HINT_1", 1, 1 },
|
|
{ "DDP_HINT_0", 0, 1 },
|
|
{ "ULP_RX_PERR_ENABLE_2", 0x19274, 0 },
|
|
{ "ENABLE_ULPRX2MA_IntfPerr", 8, 1 },
|
|
{ "ENABLE_ALN_SDC_ERR_1", 7, 1 },
|
|
{ "ENABLE_ALN_SDC_ERR_0", 6, 1 },
|
|
{ "ENABLE_PF_UNTAGGED_TPT_1", 5, 1 },
|
|
{ "ENABLE_PF_UNTAGGED_TPT_0", 4, 1 },
|
|
{ "ENABLE_PF_PBL_1", 3, 1 },
|
|
{ "ENABLE_PF_PBL_0", 2, 1 },
|
|
{ "ENABLE_DDP_HINT_1", 1, 1 },
|
|
{ "ENABLE_DDP_HINT_0", 0, 1 },
|
|
{ "ULP_RX_RQE_PBL_MULTIPLE_OUTSTANDING_CNT", 0x19278, 0 },
|
|
{ "ULP_RX_ATOMIC_LEN", 0x1927c, 0 },
|
|
{ "atomic_rpl_len", 16, 8 },
|
|
{ "atomic_req_len", 8, 8 },
|
|
{ "atomic_immediate_len", 0, 8 },
|
|
{ "ULP_RX_CGEN_GLOBAL", 0x19280, 0 },
|
|
{ "ULP_RX_CTX_SKIP_MA_REQ", 0x19284, 0 },
|
|
{ "clear_ctx_err_cnt1", 3, 1 },
|
|
{ "clear_ctx_err_cnt0", 2, 1 },
|
|
{ "skip_ma_req_en1", 1, 1 },
|
|
{ "skip_ma_req_en0", 0, 1 },
|
|
{ "ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID", 0x19288, 0 },
|
|
{ "ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID", 0x1928c, 0 },
|
|
{ "ULP_RX_MSN_CHECK_ENABLE", 0x19290, 0 },
|
|
{ "Rd_or_Term_msn_check_enable", 2, 1 },
|
|
{ "atomic_op_msn_check_enable", 1, 1 },
|
|
{ "send_msn_check_enable", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_sf_regs[] = {
|
|
{ "SF_DATA", 0x193f8, 0 },
|
|
{ "SF_OP", 0x193fc, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Lock", 4, 1 },
|
|
{ "Cont", 3, 1 },
|
|
{ "ByteCnt", 1, 2 },
|
|
{ "Op", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_pl_regs[] = {
|
|
{ "PL_PF_INT_CAUSE", 0x1e3c0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1e3c4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1e3c8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1e7c0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1e7c4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1e7c8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1ebc0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1ebc4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1ebc8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1efc0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1efc4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1efc8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1f3c0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1f3c4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1f3c8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1f7c0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1f7c4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1f7c8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1fbc0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1fbc4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1fbc8, 0 },
|
|
{ "PL_PF_INT_CAUSE", 0x1ffc0, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_INT_ENABLE", 0x1ffc4, 0 },
|
|
{ "SW", 3, 1 },
|
|
{ "CIM", 1, 1 },
|
|
{ "MPS", 0, 1 },
|
|
{ "PL_PF_CTL", 0x1ffc8, 0 },
|
|
{ "PL_WHOAMI", 0x19400, 0 },
|
|
{ "PortxMap", 24, 3 },
|
|
{ "SourceBus", 16, 2 },
|
|
{ "SourcePF", 8, 3 },
|
|
{ "IsVF", 7, 1 },
|
|
{ "VFID", 0, 7 },
|
|
{ "PL_PERR_CAUSE", 0x19404, 0 },
|
|
{ "MC1", 31, 1 },
|
|
{ "UART", 28, 1 },
|
|
{ "ULP_TX", 27, 1 },
|
|
{ "SGE", 26, 1 },
|
|
{ "HMA", 25, 1 },
|
|
{ "CPL_SWITCH", 24, 1 },
|
|
{ "ULP_RX", 23, 1 },
|
|
{ "PM_RX", 22, 1 },
|
|
{ "PM_TX", 21, 1 },
|
|
{ "MA", 20, 1 },
|
|
{ "TP", 19, 1 },
|
|
{ "LE", 18, 1 },
|
|
{ "EDC1", 17, 1 },
|
|
{ "EDC0", 16, 1 },
|
|
{ "MC0", 15, 1 },
|
|
{ "PCIE", 14, 1 },
|
|
{ "PMU", 13, 1 },
|
|
{ "MAC", 9, 1 },
|
|
{ "SMB", 8, 1 },
|
|
{ "SF", 7, 1 },
|
|
{ "PL", 6, 1 },
|
|
{ "NCSI", 5, 1 },
|
|
{ "MPS", 4, 1 },
|
|
{ "MI", 3, 1 },
|
|
{ "DBG", 2, 1 },
|
|
{ "I2CM", 1, 1 },
|
|
{ "CIM", 0, 1 },
|
|
{ "PL_PERR_ENABLE", 0x19408, 0 },
|
|
{ "MC1", 31, 1 },
|
|
{ "UART", 28, 1 },
|
|
{ "ULP_TX", 27, 1 },
|
|
{ "SGE", 26, 1 },
|
|
{ "HMA", 25, 1 },
|
|
{ "CPL_SWITCH", 24, 1 },
|
|
{ "ULP_RX", 23, 1 },
|
|
{ "PM_RX", 22, 1 },
|
|
{ "PM_TX", 21, 1 },
|
|
{ "MA", 20, 1 },
|
|
{ "TP", 19, 1 },
|
|
{ "LE", 18, 1 },
|
|
{ "EDC1", 17, 1 },
|
|
{ "EDC0", 16, 1 },
|
|
{ "MC0", 15, 1 },
|
|
{ "PCIE", 14, 1 },
|
|
{ "PMU", 13, 1 },
|
|
{ "MAC", 9, 1 },
|
|
{ "SMB", 8, 1 },
|
|
{ "SF", 7, 1 },
|
|
{ "PL", 6, 1 },
|
|
{ "NCSI", 5, 1 },
|
|
{ "MPS", 4, 1 },
|
|
{ "MI", 3, 1 },
|
|
{ "DBG", 2, 1 },
|
|
{ "I2CM", 1, 1 },
|
|
{ "CIM", 0, 1 },
|
|
{ "PL_INT_CAUSE", 0x1940c, 0 },
|
|
{ "MC1", 31, 1 },
|
|
{ "FLR", 30, 1 },
|
|
{ "SW_CIM", 29, 1 },
|
|
{ "UART", 28, 1 },
|
|
{ "ULP_TX", 27, 1 },
|
|
{ "SGE", 26, 1 },
|
|
{ "HMA", 25, 1 },
|
|
{ "CPL_SWITCH", 24, 1 },
|
|
{ "ULP_RX", 23, 1 },
|
|
{ "PM_RX", 22, 1 },
|
|
{ "PM_TX", 21, 1 },
|
|
{ "MA", 20, 1 },
|
|
{ "TP", 19, 1 },
|
|
{ "LE", 18, 1 },
|
|
{ "EDC1", 17, 1 },
|
|
{ "EDC0", 16, 1 },
|
|
{ "MC0", 15, 1 },
|
|
{ "PCIE", 14, 1 },
|
|
{ "PMU", 13, 1 },
|
|
{ "MAC3", 12, 1 },
|
|
{ "MAC2", 11, 1 },
|
|
{ "MAC1", 10, 1 },
|
|
{ "MAC0", 9, 1 },
|
|
{ "SMB", 8, 1 },
|
|
{ "SF", 7, 1 },
|
|
{ "PL", 6, 1 },
|
|
{ "NCSI", 5, 1 },
|
|
{ "MPS", 4, 1 },
|
|
{ "MI", 3, 1 },
|
|
{ "DBG", 2, 1 },
|
|
{ "I2CM", 1, 1 },
|
|
{ "CIM", 0, 1 },
|
|
{ "PL_INT_ENABLE", 0x19410, 0 },
|
|
{ "MC1", 31, 1 },
|
|
{ "FLR", 30, 1 },
|
|
{ "SW_CIM", 29, 1 },
|
|
{ "UART", 28, 1 },
|
|
{ "ULP_TX", 27, 1 },
|
|
{ "SGE", 26, 1 },
|
|
{ "HMA", 25, 1 },
|
|
{ "CPL_SWITCH", 24, 1 },
|
|
{ "ULP_RX", 23, 1 },
|
|
{ "PM_RX", 22, 1 },
|
|
{ "PM_TX", 21, 1 },
|
|
{ "MA", 20, 1 },
|
|
{ "TP", 19, 1 },
|
|
{ "LE", 18, 1 },
|
|
{ "EDC1", 17, 1 },
|
|
{ "EDC0", 16, 1 },
|
|
{ "MC0", 15, 1 },
|
|
{ "PCIE", 14, 1 },
|
|
{ "PMU", 13, 1 },
|
|
{ "MAC3", 12, 1 },
|
|
{ "MAC2", 11, 1 },
|
|
{ "MAC1", 10, 1 },
|
|
{ "MAC0", 9, 1 },
|
|
{ "SMB", 8, 1 },
|
|
{ "SF", 7, 1 },
|
|
{ "PL", 6, 1 },
|
|
{ "NCSI", 5, 1 },
|
|
{ "MPS", 4, 1 },
|
|
{ "MI", 3, 1 },
|
|
{ "DBG", 2, 1 },
|
|
{ "I2CM", 1, 1 },
|
|
{ "CIM", 0, 1 },
|
|
{ "PL_INT_MAP0", 0x19414, 0 },
|
|
{ "MapNCSI", 16, 9 },
|
|
{ "MapDefault", 0, 9 },
|
|
{ "PL_INT_MAP1", 0x19418, 0 },
|
|
{ "MapMAC1", 16, 9 },
|
|
{ "MapMAC0", 0, 9 },
|
|
{ "PL_INT_MAP2", 0x1941c, 0 },
|
|
{ "MapMAC3", 16, 9 },
|
|
{ "MapMAC2", 0, 9 },
|
|
{ "PL_INT_MAP3", 0x19420, 0 },
|
|
{ "MapMI", 16, 9 },
|
|
{ "MapSMB", 0, 9 },
|
|
{ "PL_INT_MAP4", 0x19424, 0 },
|
|
{ "MapDBG", 16, 9 },
|
|
{ "MapI2CM", 0, 9 },
|
|
{ "PL_RST", 0x19428, 0 },
|
|
{ "AutoPciePause", 4, 1 },
|
|
{ "FatalPerrEn", 3, 1 },
|
|
{ "SWIntCIM", 2, 1 },
|
|
{ "PIORst", 1, 1 },
|
|
{ "PIORstMode", 0, 1 },
|
|
{ "PL_PL_INT_CAUSE", 0x19430, 0 },
|
|
{ "PL_BusPerr", 6, 1 },
|
|
{ "FatalPerr", 4, 1 },
|
|
{ "InvalidAccess", 3, 1 },
|
|
{ "Timeout", 2, 1 },
|
|
{ "PLErr", 1, 1 },
|
|
{ "PL_PL_INT_ENABLE", 0x19434, 0 },
|
|
{ "PL_BusPerr", 6, 1 },
|
|
{ "FatalPerr", 4, 1 },
|
|
{ "InvalidAccess", 3, 1 },
|
|
{ "Timeout", 2, 1 },
|
|
{ "PLErr", 1, 1 },
|
|
{ "PL_PL_PERR_ENABLE", 0x19438, 0 },
|
|
{ "PL_BusPerr", 6, 1 },
|
|
{ "PL_REV", 0x1943c, 0 },
|
|
{ "ChipID", 4, 4 },
|
|
{ "Rev", 0, 4 },
|
|
{ "PL_PCIE_LINK", 0x19440, 0 },
|
|
{ "LN0_AESTAT", 26, 3 },
|
|
{ "LN0_AECMD", 23, 3 },
|
|
{ "StateCfgInitF", 16, 7 },
|
|
{ "StateCfgInit", 12, 4 },
|
|
{ "SPEED", 8, 2 },
|
|
{ "PERstTimeout", 7, 1 },
|
|
{ "LTSSMEnable", 6, 1 },
|
|
{ "LTSSM", 0, 6 },
|
|
{ "PL_PCIE_CTL_STAT", 0x19444, 0 },
|
|
{ "Status", 16, 16 },
|
|
{ "Control", 0, 16 },
|
|
{ "PL_SEMAPHORE_CTL", 0x1944c, 0 },
|
|
{ "LockStatus", 16, 8 },
|
|
{ "OwnerOverride", 8, 1 },
|
|
{ "EnablePF", 0, 8 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x19450, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x19454, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x19458, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x1945c, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x19460, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x19464, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x19468, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_SEMAPHORE_LOCK", 0x1946c, 0 },
|
|
{ "Lock", 31, 1 },
|
|
{ "SourceBus", 3, 2 },
|
|
{ "SourcePF", 0, 3 },
|
|
{ "PL_PORTX_MAP", 0x19474, 0 },
|
|
{ "MAP7", 28, 3 },
|
|
{ "MAP6", 24, 3 },
|
|
{ "MAP5", 20, 3 },
|
|
{ "MAP4", 16, 3 },
|
|
{ "MAP3", 12, 3 },
|
|
{ "MAP2", 8, 3 },
|
|
{ "MAP1", 4, 3 },
|
|
{ "MAP0", 0, 3 },
|
|
{ "PL_VF_SLICE_L", 0x19490, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x19498, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x194a0, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x194a8, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x194b0, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x194b8, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x194c0, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_L", 0x194c8, 0 },
|
|
{ "LimitAddr", 16, 10 },
|
|
{ "BaseAddr", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x19494, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x1949c, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x194a4, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x194ac, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x194b4, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x194bc, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x194c4, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_VF_SLICE_H", 0x194cc, 0 },
|
|
{ "ModIndx", 16, 3 },
|
|
{ "ModOffset", 0, 10 },
|
|
{ "PL_TIMEOUT_CTL", 0x194f0, 0 },
|
|
{ "PerrCapture", 16, 1 },
|
|
{ "Timeout", 0, 16 },
|
|
{ "PL_TIMEOUT_STATUS0", 0x194f4, 0 },
|
|
{ "Addr", 2, 28 },
|
|
{ "PL_TIMEOUT_STATUS1", 0x194f8, 0 },
|
|
{ "Valid", 31, 1 },
|
|
{ "ValidPerr", 30, 1 },
|
|
{ "Write", 22, 1 },
|
|
{ "Bus", 20, 2 },
|
|
{ "PF", 16, 3 },
|
|
{ "VFID", 0, 8 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_le_regs[] = {
|
|
{ "LE_BUF_CONFIG", 0x19c00, 0 },
|
|
{ "LE_DB_CONFIG", 0x19c04, 0 },
|
|
{ "MASKCMDOLAPDIS", 26, 1 },
|
|
{ "IPv4HASHSIZEEN", 25, 1 },
|
|
{ "PROTOCOLMASKEN", 24, 1 },
|
|
{ "TUPLESIZEEN", 23, 1 },
|
|
{ "SRVRSRAMEN", 22, 1 },
|
|
{ "TCAMCMDOVLAPEN", 21, 1 },
|
|
{ "HASHEN", 20, 1 },
|
|
{ "ASBOTHSRCHENPR", 19, 1 },
|
|
{ "ASBOTHSRCHEN", 18, 1 },
|
|
{ "ASLIPCOMPEN", 17, 1 },
|
|
{ "BUILD", 16, 1 },
|
|
{ "POCLIPTID0", 15, 1 },
|
|
{ "TCAMARBOFF", 14, 1 },
|
|
{ "ACCNTFULLEN", 13, 1 },
|
|
{ "FilterRWnoCLIP", 12, 1 },
|
|
{ "FilterEn", 11, 1 },
|
|
{ "CRCHASH", 10, 1 },
|
|
{ "COMPTID", 9, 1 },
|
|
{ "SYNMode", 7, 2 },
|
|
{ "SINGLETHREAD", 6, 1 },
|
|
{ "LEBUSEN", 5, 1 },
|
|
{ "ELOOKDUMEN", 4, 1 },
|
|
{ "IPv4ONLYEN", 3, 1 },
|
|
{ "MOSTCMDOEN", 2, 1 },
|
|
{ "DELACTSYNOEN", 1, 1 },
|
|
{ "CMDOVERLAPDIS", 0, 1 },
|
|
{ "LE_MISC", 0x19c08, 0 },
|
|
{ "SRAMDEEPSLEEP_STAT", 11, 1 },
|
|
{ "TCAMDEEPSLEEP1_STAT", 10, 1 },
|
|
{ "TCAMDEEPSLEEP0_STAT", 9, 1 },
|
|
{ "SRAMDEEPSLEEP", 8, 1 },
|
|
{ "TCAMDEEPSLEEP1", 7, 1 },
|
|
{ "TCAMDEEPSLEEP0", 6, 1 },
|
|
{ "SRVRAMCLKOFF", 5, 1 },
|
|
{ "HASHCLKOFF", 4, 1 },
|
|
{ "CMPUNVAIL", 0, 4 },
|
|
{ "LE_DB_ROUTING_TABLE_INDEX", 0x19c10, 0 },
|
|
{ "RTINDX", 7, 6 },
|
|
{ "LE_DB_FILTER_TABLE_INDEX", 0x19c14, 0 },
|
|
{ "FTINDX", 7, 6 },
|
|
{ "LE_DB_SERVER_INDEX", 0x19c18, 0 },
|
|
{ "SRINDX", 7, 6 },
|
|
{ "LE_DB_CLIP_TABLE_INDEX", 0x19c1c, 0 },
|
|
{ "CLIPTINDX", 7, 6 },
|
|
{ "LE_DB_ACT_CNT_IPV4", 0x19c20, 0 },
|
|
{ "LE_DB_ACT_CNT_IPV6", 0x19c24, 0 },
|
|
{ "LE_DB_ACT_CNT_IPV4_TCAM", 0x19c94, 0 },
|
|
{ "LE_DB_ACT_CNT_IPV6_TCAM", 0x19c98, 0 },
|
|
{ "LE_ACT_CNT_THRSH", 0x19c9c, 0 },
|
|
{ "LE_DB_HASH_CONFIG", 0x19c28, 0 },
|
|
{ "HASHTIDSIZE", 16, 6 },
|
|
{ "HASHSIZE", 0, 6 },
|
|
{ "LE_DB_HASH_TABLE_BASE", 0x19c2c, 0 },
|
|
{ "LE_DB_HASH_TID_BASE", 0x19c30, 0 },
|
|
{ "LE_DB_SIZE", 0x19c34, 0 },
|
|
{ "LE_DB_INT_ENABLE", 0x19c38, 0 },
|
|
{ "MsgSel", 27, 5 },
|
|
{ "ActCntIPv6Tzero", 21, 1 },
|
|
{ "ActCntIPv4Tzero", 20, 1 },
|
|
{ "ActCntIPv6zero", 19, 1 },
|
|
{ "ActCntIPv4zero", 18, 1 },
|
|
{ "MARspParErr", 17, 1 },
|
|
{ "ReqQParErr", 16, 1 },
|
|
{ "UnknownCmd", 15, 1 },
|
|
{ "VfParErr", 14, 1 },
|
|
{ "DropFilterHit", 13, 1 },
|
|
{ "FilterHit", 12, 1 },
|
|
{ "SYNCookieOff", 11, 1 },
|
|
{ "SYNCookieBad", 10, 1 },
|
|
{ "SYNCookie", 9, 1 },
|
|
{ "NFASrchFail", 8, 1 },
|
|
{ "ActRgnFull", 7, 1 },
|
|
{ "ParityErr", 6, 1 },
|
|
{ "LIPMiss", 5, 1 },
|
|
{ "LIP0", 4, 1 },
|
|
{ "Miss", 3, 1 },
|
|
{ "RoutingHit", 2, 1 },
|
|
{ "ActiveHit", 1, 1 },
|
|
{ "ServerHit", 0, 1 },
|
|
{ "LE_DB_INT_CAUSE", 0x19c3c, 0 },
|
|
{ "ActCntIPv6Tzero", 21, 1 },
|
|
{ "ActCntIPv4Tzero", 20, 1 },
|
|
{ "ActCntIPv6zero", 19, 1 },
|
|
{ "ActCntIPv4zero", 18, 1 },
|
|
{ "MARspParErr", 17, 1 },
|
|
{ "ReqQParErr", 16, 1 },
|
|
{ "UnknownCmd", 15, 1 },
|
|
{ "VfParErr", 14, 1 },
|
|
{ "DropFilterHit", 13, 1 },
|
|
{ "FilterHit", 12, 1 },
|
|
{ "SYNCookieOff", 11, 1 },
|
|
{ "SYNCookieBad", 10, 1 },
|
|
{ "SYNCookie", 9, 1 },
|
|
{ "NFASrchFail", 8, 1 },
|
|
{ "ActRgnFull", 7, 1 },
|
|
{ "ParityErr", 6, 1 },
|
|
{ "LIPMiss", 5, 1 },
|
|
{ "LIP0", 4, 1 },
|
|
{ "Miss", 3, 1 },
|
|
{ "RoutingHit", 2, 1 },
|
|
{ "ActiveHit", 1, 1 },
|
|
{ "ServerHit", 0, 1 },
|
|
{ "LE_DB_INT_TID", 0x19c40, 0 },
|
|
{ "LE_DB_INT_PTID", 0x19c44, 0 },
|
|
{ "LE_DB_INT_INDEX", 0x19c48, 0 },
|
|
{ "LE_DB_INT_CMD", 0x19c4c, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c50, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c54, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c58, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c5c, 0 },
|
|
{ "LE_DB_MASK_IPV4", 0x19c60, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19ca0, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19ca4, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19ca8, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cac, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cb0, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cb4, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cb8, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cbc, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cc0, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cc4, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cc8, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19ccc, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cd0, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cd4, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cd8, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19cdc, 0 },
|
|
{ "LE_DB_MASK_IPV6", 0x19ce0, 0 },
|
|
{ "LE_DB_REQ_RSP_CNT", 0x19ce4, 0 },
|
|
{ "RspCnt", 16, 16 },
|
|
{ "ReqCnt", 0, 16 },
|
|
{ "LE_DB_DBGI_CONFIG", 0x19cf0, 0 },
|
|
{ "DBGICMDPERR", 31, 1 },
|
|
{ "DBGICMDRANGE", 22, 3 },
|
|
{ "DBGICMDMSKTYPE", 21, 1 },
|
|
{ "DBGICMDSEARCH", 20, 1 },
|
|
{ "DBGICMDREAD", 19, 1 },
|
|
{ "DBGICMDLEARN", 18, 1 },
|
|
{ "DBGICMDERASE", 17, 1 },
|
|
{ "DBGICMDIPv6", 16, 1 },
|
|
{ "DBGICMDTYPE", 13, 3 },
|
|
{ "DBGICMDACKERR", 12, 1 },
|
|
{ "DBGICMDBUSY", 3, 1 },
|
|
{ "DBGICMDSTRT", 2, 1 },
|
|
{ "DBGICMDMODE", 0, 2 },
|
|
{ "LE_DB_DBGI_REQ_TCAM_CMD", 0x19cf4, 0 },
|
|
{ "DBGICMD", 20, 4 },
|
|
{ "DBGITINDEX", 0, 20 },
|
|
{ "LE_PERR_ENABLE", 0x19cf8, 0 },
|
|
{ "MARspParErr", 17, 1 },
|
|
{ "ReqQueue", 16, 1 },
|
|
{ "VfParErr", 14, 1 },
|
|
{ "TCAM", 6, 1 },
|
|
{ "LE_SPARE", 0x19cfc, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d00, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d04, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d08, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d0c, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d10, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d14, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d18, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d1c, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d20, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d24, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d28, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d2c, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d30, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d34, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d38, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d3c, 0 },
|
|
{ "LE_DB_DBGI_REQ_DATA", 0x19d40, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d50, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d54, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d58, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d5c, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d60, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d64, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d68, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d6c, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d70, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d74, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d78, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d7c, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d80, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d84, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d88, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d8c, 0 },
|
|
{ "LE_DB_DBGI_REQ_MASK", 0x19d90, 0 },
|
|
{ "LE_DB_DBGI_RSP_STATUS", 0x19d94, 0 },
|
|
{ "DBGIRspIndex", 12, 20 },
|
|
{ "DBGIRspMsg", 8, 4 },
|
|
{ "DBGIRspMsgVld", 7, 1 },
|
|
{ "DBGIRspMHit", 2, 1 },
|
|
{ "DBGIRspHit", 1, 1 },
|
|
{ "DBGIRspValid", 0, 1 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19da0, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19da4, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19da8, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dac, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19db0, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19db4, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19db8, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dbc, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dc0, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dc4, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dc8, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dcc, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dd0, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dd4, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19dd8, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19ddc, 0 },
|
|
{ "LE_DB_DBGI_RSP_DATA", 0x19de0, 0 },
|
|
{ "LE_DB_DBGI_RSP_LAST_CMD", 0x19de4, 0 },
|
|
{ "LastCmdB", 16, 11 },
|
|
{ "LastCmdA", 0, 11 },
|
|
{ "LE_DB_DROP_FILTER_ENTRY", 0x19de8, 0 },
|
|
{ "DropFilterEn", 31, 1 },
|
|
{ "DropFilterClear", 17, 1 },
|
|
{ "DropFilterSet", 16, 1 },
|
|
{ "DropFilterFIDX", 0, 13 },
|
|
{ "LE_DB_PTID_SVRBASE", 0x19df0, 0 },
|
|
{ "SVRBASE_ADDR", 2, 18 },
|
|
{ "LE_DB_FTID_FLTRBASE", 0x19df4, 0 },
|
|
{ "FLTRBASE_ADDR", 2, 18 },
|
|
{ "LE_DB_TID_HASHBASE", 0x19df8, 0 },
|
|
{ "HASHBASE_ADDR", 2, 20 },
|
|
{ "LE_PERR_INJECT", 0x19dfc, 0 },
|
|
{ "MemSel", 1, 3 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e00, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e04, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e08, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e0c, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV4", 0x19e10, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e50, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e54, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e58, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e5c, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e60, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e64, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e68, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e6c, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e70, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e74, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e78, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e7c, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e80, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e84, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e88, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e8c, 0 },
|
|
{ "LE_DB_ACTIVE_MASK_IPV6", 0x19e90, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV4", 0x19ea0, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV4", 0x19ea4, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV4", 0x19ea8, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV4", 0x19eac, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV4", 0x19eb0, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19eb4, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19eb8, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19ebc, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19ec0, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19ec4, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19ec8, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19ecc, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19ed0, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19ed4, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19ed8, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19edc, 0 },
|
|
{ "LE_HASH_MASK_GEN_IPV6", 0x19ee0, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV4", 0x19ee4, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV4", 0x19ee8, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV4", 0x19eec, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV4", 0x19ef0, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV4", 0x19ef4, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19ef8, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19efc, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19f00, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19f04, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19f08, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19f0c, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19f10, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19f14, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19f18, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19f1c, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19f20, 0 },
|
|
{ "LE_HASH_MASK_CMP_IPV6", 0x19f24, 0 },
|
|
{ "LE_SRVR_SRAM_INIT", 0x19f34, 0 },
|
|
{ "SRVRSRAMBASE", 2, 20 },
|
|
{ "SRVRINITBUSY", 1, 1 },
|
|
{ "SRVRINIT", 0, 1 },
|
|
{ "LE_SRVR_VF_SRCH_TABLE", 0x19f38, 0 },
|
|
{ "RDWR", 21, 1 },
|
|
{ "VFINDEX", 14, 7 },
|
|
{ "SRCHHADDR", 7, 7 },
|
|
{ "SRCHLADDR", 0, 7 },
|
|
{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f40, 0 },
|
|
{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f44, 0 },
|
|
{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f48, 0 },
|
|
{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f4c, 0 },
|
|
{ "LE_DB_SECOND_ACTIVE_MASK_IPV4", 0x19f50, 0 },
|
|
{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f90, 0 },
|
|
{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f94, 0 },
|
|
{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f98, 0 },
|
|
{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19f9c, 0 },
|
|
{ "LE_DB_SECOND_GEN_HASH_MASK_IPV4", 0x19fa0, 0 },
|
|
{ "LE_DB_SECOND_CMP_HASH_MASK_IPV4", 0x19fa4, 0 },
|
|
{ "LE_DB_SECOND_CMP_HASH_MASK_IPV4", 0x19fa8, 0 },
|
|
{ "LE_DB_SECOND_CMP_HASH_MASK_IPV4", 0x19fac, 0 },
|
|
{ "LE_DB_SECOND_CMP_HASH_MASK_IPV4", 0x19fb0, 0 },
|
|
{ "LE_DB_SECOND_CMP_HASH_MASK_IPV4", 0x19fb4, 0 },
|
|
{ "LE_HASH_COLLISION", 0x19fc4, 0 },
|
|
{ "LE_GLOBAL_COLLISION", 0x19fc8, 0 },
|
|
{ "LE_FULL_CNT_COLLISION", 0x19fcc, 0 },
|
|
{ "LE_DEBUG_LA_CONFIG", 0x19fd0, 0 },
|
|
{ "LE_REQ_DEBUG_LA_DATA", 0x19fd4, 0 },
|
|
{ "LE_REQ_DEBUG_LA_WRPTR", 0x19fd8, 0 },
|
|
{ "LE_RSP_DEBUG_LA_DATA", 0x19fdc, 0 },
|
|
{ "LE_RSP_DEBUG_LA_WRPTR", 0x19fe0, 0 },
|
|
{ "LE_DEBUG_LA_SEL_DATA", 0x19fe4, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_ncsi_regs[] = {
|
|
{ "NCSI_PORT_CFGREG", 0x1a000, 0 },
|
|
{ "WireEn", 28, 4 },
|
|
{ "strp_crc", 24, 4 },
|
|
{ "rx_halt", 22, 1 },
|
|
{ "flush_rx_fifo", 21, 1 },
|
|
{ "hw_arb_en", 20, 1 },
|
|
{ "soft_pkg_sel", 19, 1 },
|
|
{ "err_discard_en", 18, 1 },
|
|
{ "max_pkt_size", 4, 14 },
|
|
{ "rx_byte_swap", 3, 1 },
|
|
{ "tx_byte_swap", 2, 1 },
|
|
{ "NCSI_RST_CTRL", 0x1a004, 0 },
|
|
{ "mac_ref_rst", 2, 1 },
|
|
{ "mac_rx_rst", 1, 1 },
|
|
{ "mac_tx_rst", 0, 1 },
|
|
{ "NCSI_CH0_SADDR_LOW", 0x1a010, 0 },
|
|
{ "NCSI_CH0_SADDR_HIGH", 0x1a014, 0 },
|
|
{ "CHO_SADDR_EN", 31, 1 },
|
|
{ "CH0_SADDR_HIGH", 0, 16 },
|
|
{ "NCSI_CH1_SADDR_LOW", 0x1a018, 0 },
|
|
{ "NCSI_CH1_SADDR_HIGH", 0x1a01c, 0 },
|
|
{ "CH1_SADDR_EN", 31, 1 },
|
|
{ "CH1_SADDR_HIGH", 0, 16 },
|
|
{ "NCSI_CH2_SADDR_LOW", 0x1a020, 0 },
|
|
{ "NCSI_CH2_SADDR_HIGH", 0x1a024, 0 },
|
|
{ "CH2_SADDR_EN", 31, 1 },
|
|
{ "CH2_SADDR_HIGH", 0, 16 },
|
|
{ "NCSI_CH3_SADDR_LOW", 0x1a028, 0 },
|
|
{ "NCSI_CH3_SADDR_HIGH", 0x1a02c, 0 },
|
|
{ "CH3_SADDR_EN", 31, 1 },
|
|
{ "CH3_SADDR_HIGH", 0, 16 },
|
|
{ "NCSI_WORK_REQHDR_0", 0x1a030, 0 },
|
|
{ "NCSI_WORK_REQHDR_1", 0x1a034, 0 },
|
|
{ "NCSI_WORK_REQHDR_2", 0x1a038, 0 },
|
|
{ "NCSI_WORK_REQHDR_3", 0x1a03c, 0 },
|
|
{ "NCSI_MPS_HDR_LO", 0x1a040, 0 },
|
|
{ "NCSI_MPS_HDR_HI", 0x1a044, 0 },
|
|
{ "NCSI_CTL", 0x1a048, 0 },
|
|
{ "STRIP_OVLAN", 3, 1 },
|
|
{ "bmc_drop_non_bc", 2, 1 },
|
|
{ "bmc_rx_fwd_all", 1, 1 },
|
|
{ "FWD_BMC", 0, 1 },
|
|
{ "NCSI_NCSI_ETYPE", 0x1a04c, 0 },
|
|
{ "NCSI_RX_FIFO_CNT", 0x1a050, 0 },
|
|
{ "NCSI_RX_ERR_CNT", 0x1a054, 0 },
|
|
{ "NCSI_RX_OF_CNT", 0x1a058, 0 },
|
|
{ "NCSI_RX_MS_CNT", 0x1a05c, 0 },
|
|
{ "NCSI_RX_IE_CNT", 0x1a060, 0 },
|
|
{ "NCSI_MPS_DEMUX_CNT", 0x1a064, 0 },
|
|
{ "MPS2CIM_CNT", 16, 9 },
|
|
{ "MPS2BMC_CNT", 0, 9 },
|
|
{ "NCSI_CIM_DEMUX_CNT", 0x1a068, 0 },
|
|
{ "CIM2MPS_CNT", 16, 9 },
|
|
{ "CIM2BMC_CNT", 0, 9 },
|
|
{ "NCSI_TX_FIFO_CNT", 0x1a06c, 0 },
|
|
{ "NCSI_SE_CNT_CTL", 0x1a0b0, 0 },
|
|
{ "NCSI_SE_CNT_MPS", 0x1a0b4, 0 },
|
|
{ "NCSI_SE_CNT_CIM", 0x1a0b8, 0 },
|
|
{ "NCSI_BUS_DEBUG", 0x1a0bc, 0 },
|
|
{ "NCSI_LA_RDPTR", 0x1a0c0, 0 },
|
|
{ "NCSI_LA_RDDATA", 0x1a0c4, 0 },
|
|
{ "NCSI_LA_WRPTR", 0x1a0c8, 0 },
|
|
{ "NCSI_LA_RESERVED", 0x1a0cc, 0 },
|
|
{ "NCSI_LA_CTL", 0x1a0d0, 0 },
|
|
{ "NCSI_INT_ENABLE", 0x1a0d4, 0 },
|
|
{ "CIM_DM_prty_err", 8, 1 },
|
|
{ "MPS_DM_prty_err", 7, 1 },
|
|
{ "token", 6, 1 },
|
|
{ "arb_done", 5, 1 },
|
|
{ "arb_started", 4, 1 },
|
|
{ "WOL", 3, 1 },
|
|
{ "MACInt", 2, 1 },
|
|
{ "TXFIFO_prty_err", 1, 1 },
|
|
{ "RXFIFO_prty_err", 0, 1 },
|
|
{ "NCSI_INT_CAUSE", 0x1a0d8, 0 },
|
|
{ "CIM_DM_prty_err", 8, 1 },
|
|
{ "MPS_DM_prty_err", 7, 1 },
|
|
{ "token", 6, 1 },
|
|
{ "arb_done", 5, 1 },
|
|
{ "arb_started", 4, 1 },
|
|
{ "WOL", 3, 1 },
|
|
{ "MACInt", 2, 1 },
|
|
{ "TXFIFO_prty_err", 1, 1 },
|
|
{ "RXFIFO_prty_err", 0, 1 },
|
|
{ "NCSI_STATUS", 0x1a0dc, 0 },
|
|
{ "Master", 1, 1 },
|
|
{ "arb_status", 0, 1 },
|
|
{ "NCSI_PAUSE_CTRL", 0x1a0e0, 0 },
|
|
{ "NCSI_PAUSE_TIMEOUT", 0x1a0e4, 0 },
|
|
{ "NCSI_PAUSE_WM", 0x1a0ec, 0 },
|
|
{ "PauseHWM", 16, 11 },
|
|
{ "PauseLWM", 0, 11 },
|
|
{ "NCSI_DEBUG", 0x1a0f0, 0 },
|
|
{ "TxFIFO_empty", 4, 1 },
|
|
{ "TxFIFO_full", 3, 1 },
|
|
{ "PKG_ID", 0, 3 },
|
|
{ "NCSI_PERR_INJECT", 0x1a0f4, 0 },
|
|
{ "MemSel", 1, 1 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "NCSI_PERR_ENABLE", 0x1a0f8, 0 },
|
|
{ "CIM_DM_prty_err", 8, 1 },
|
|
{ "MPS_DM_prty_err", 7, 1 },
|
|
{ "TXFIFO_prty_err", 1, 1 },
|
|
{ "RXFIFO_prty_err", 0, 1 },
|
|
{ "NCSI_MACB_NETWORK_CTRL", 0x1a100, 0 },
|
|
{ "TxSndZeroPause", 12, 1 },
|
|
{ "TxSndPause", 11, 1 },
|
|
{ "TxStop", 10, 1 },
|
|
{ "TxStart", 9, 1 },
|
|
{ "BackPress", 8, 1 },
|
|
{ "StatWrEn", 7, 1 },
|
|
{ "IncrStat", 6, 1 },
|
|
{ "ClearStat", 5, 1 },
|
|
{ "EnMgmtPort", 4, 1 },
|
|
{ "TxEn", 3, 1 },
|
|
{ "RxEn", 2, 1 },
|
|
{ "LoopLocal", 1, 1 },
|
|
{ "LoopPHY", 0, 1 },
|
|
{ "NCSI_MACB_NETWORK_CFG", 0x1a104, 0 },
|
|
{ "PClkDiv128", 22, 1 },
|
|
{ "CopyPause", 21, 1 },
|
|
{ "NonStdPreOK", 20, 1 },
|
|
{ "NoFCS", 19, 1 },
|
|
{ "RxEnHalfDup", 18, 1 },
|
|
{ "NoCopyFCS", 17, 1 },
|
|
{ "LenChkEn", 16, 1 },
|
|
{ "RxBufOffset", 14, 2 },
|
|
{ "PauseEn", 13, 1 },
|
|
{ "RetryTest", 12, 1 },
|
|
{ "PClkDiv", 10, 2 },
|
|
{ "ExtClass", 9, 1 },
|
|
{ "En1536Frame", 8, 1 },
|
|
{ "UCastHashEn", 7, 1 },
|
|
{ "MCastHashEn", 6, 1 },
|
|
{ "RxBCastDis", 5, 1 },
|
|
{ "CopyAllFrames", 4, 1 },
|
|
{ "JumboEn", 3, 1 },
|
|
{ "SerEn", 2, 1 },
|
|
{ "FullDuplex", 1, 1 },
|
|
{ "Speed", 0, 1 },
|
|
{ "NCSI_MACB_NETWORK_STATUS", 0x1a108, 0 },
|
|
{ "PHYMgmtStatus", 2, 1 },
|
|
{ "MDIStatus", 1, 1 },
|
|
{ "LinkStatus", 0, 1 },
|
|
{ "NCSI_MACB_TX_STATUS", 0x1a114, 0 },
|
|
{ "UnderrunErr", 6, 1 },
|
|
{ "TxComplete", 5, 1 },
|
|
{ "BufferExhausted", 4, 1 },
|
|
{ "TxProgress", 3, 1 },
|
|
{ "RetryLimit", 2, 1 },
|
|
{ "ColEvent", 1, 1 },
|
|
{ "UsedBitRead", 0, 1 },
|
|
{ "NCSI_MACB_RX_BUF_QPTR", 0x1a118, 0 },
|
|
{ "RxBufQPtr", 2, 30 },
|
|
{ "NCSI_MACB_TX_BUF_QPTR", 0x1a11c, 0 },
|
|
{ "TxBufQPtr", 2, 30 },
|
|
{ "NCSI_MACB_RX_STATUS", 0x1a120, 0 },
|
|
{ "RxOverrunErr", 2, 1 },
|
|
{ "FrameRcvd", 1, 1 },
|
|
{ "NoRxBuf", 0, 1 },
|
|
{ "NCSI_MACB_INT_STATUS", 0x1a124, 0 },
|
|
{ "PauseTimeZero", 13, 1 },
|
|
{ "PauseRcvd", 12, 1 },
|
|
{ "HRespNotOK", 11, 1 },
|
|
{ "RxOverrun", 10, 1 },
|
|
{ "LinkChange", 9, 1 },
|
|
{ "TxComplete", 7, 1 },
|
|
{ "TxBufErr", 6, 1 },
|
|
{ "RetryLimitErr", 5, 1 },
|
|
{ "TxBufUnderrun", 4, 1 },
|
|
{ "TxUsedBitRead", 3, 1 },
|
|
{ "RxUsedBitRead", 2, 1 },
|
|
{ "RxComplete", 1, 1 },
|
|
{ "MgmtFrameSent", 0, 1 },
|
|
{ "NCSI_MACB_INT_EN", 0x1a128, 0 },
|
|
{ "PauseTimeZero", 13, 1 },
|
|
{ "PauseRcvd", 12, 1 },
|
|
{ "HRespNotOK", 11, 1 },
|
|
{ "RxOverrun", 10, 1 },
|
|
{ "LinkChange", 9, 1 },
|
|
{ "TxComplete", 7, 1 },
|
|
{ "TxBufErr", 6, 1 },
|
|
{ "RetryLimitErr", 5, 1 },
|
|
{ "TxBufUnderrun", 4, 1 },
|
|
{ "TxUsedBitRead", 3, 1 },
|
|
{ "RxUsedBitRead", 2, 1 },
|
|
{ "RxComplete", 1, 1 },
|
|
{ "MgmtFrameSent", 0, 1 },
|
|
{ "NCSI_MACB_INT_DIS", 0x1a12c, 0 },
|
|
{ "PauseTimeZero", 13, 1 },
|
|
{ "PauseRcvd", 12, 1 },
|
|
{ "HRespNotOK", 11, 1 },
|
|
{ "RxOverrun", 10, 1 },
|
|
{ "LinkChange", 9, 1 },
|
|
{ "TxComplete", 7, 1 },
|
|
{ "TxBufErr", 6, 1 },
|
|
{ "RetryLimitErr", 5, 1 },
|
|
{ "TxBufUnderrun", 4, 1 },
|
|
{ "TxUsedBitRead", 3, 1 },
|
|
{ "RxUsedBitRead", 2, 1 },
|
|
{ "RxComplete", 1, 1 },
|
|
{ "MgmtFrameSent", 0, 1 },
|
|
{ "NCSI_MACB_INT_MASK", 0x1a130, 0 },
|
|
{ "PauseTimeZero", 13, 1 },
|
|
{ "PauseRcvd", 12, 1 },
|
|
{ "HRespNotOK", 11, 1 },
|
|
{ "RxOverrun", 10, 1 },
|
|
{ "LinkChange", 9, 1 },
|
|
{ "TxComplete", 7, 1 },
|
|
{ "TxBufErr", 6, 1 },
|
|
{ "RetryLimitErr", 5, 1 },
|
|
{ "TxBufUnderrun", 4, 1 },
|
|
{ "TxUsedBitRead", 3, 1 },
|
|
{ "RxUsedBitRead", 2, 1 },
|
|
{ "RxComplete", 1, 1 },
|
|
{ "MgmtFrameSent", 0, 1 },
|
|
{ "NCSI_MACB_PAUSE_TIME", 0x1a138, 0 },
|
|
{ "NCSI_MACB_PAUSE_FRAMES_RCVD", 0x1a13c, 0 },
|
|
{ "NCSI_MACB_TX_FRAMES_OK", 0x1a140, 0 },
|
|
{ "NCSI_MACB_SINGLE_COL_FRAMES", 0x1a144, 0 },
|
|
{ "NCSI_MACB_MUL_COL_FRAMES", 0x1a148, 0 },
|
|
{ "NCSI_MACB_RX_FRAMES_OK", 0x1a14c, 0 },
|
|
{ "NCSI_MACB_FCS_ERR", 0x1a150, 0 },
|
|
{ "NCSI_MACB_ALIGN_ERR", 0x1a154, 0 },
|
|
{ "NCSI_MACB_DEF_TX_FRAMES", 0x1a158, 0 },
|
|
{ "NCSI_MACB_LATE_COL", 0x1a15c, 0 },
|
|
{ "NCSI_MACB_EXCESSIVE_COL", 0x1a160, 0 },
|
|
{ "NCSI_MACB_TX_UNDERRUN_ERR", 0x1a164, 0 },
|
|
{ "NCSI_MACB_CARRIER_SENSE_ERR", 0x1a168, 0 },
|
|
{ "NCSI_MACB_RX_RESOURCE_ERR", 0x1a16c, 0 },
|
|
{ "NCSI_MACB_RX_OVERRUN_ERR", 0x1a170, 0 },
|
|
{ "NCSI_MACB_RX_SYMBOL_ERR", 0x1a174, 0 },
|
|
{ "NCSI_MACB_RX_OVERSIZE_FRAME", 0x1a178, 0 },
|
|
{ "NCSI_MACB_RX_JABBER_ERR", 0x1a17c, 0 },
|
|
{ "NCSI_MACB_RX_UNDERSIZE_FRAME", 0x1a180, 0 },
|
|
{ "NCSI_MACB_SQE_TEST_ERR", 0x1a184, 0 },
|
|
{ "NCSI_MACB_LENGTH_ERR", 0x1a188, 0 },
|
|
{ "NCSI_MACB_TX_PAUSE_FRAMES", 0x1a18c, 0 },
|
|
{ "NCSI_MACB_HASH_LOW", 0x1a190, 0 },
|
|
{ "NCSI_MACB_HASH_HIGH", 0x1a194, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_1_LOW", 0x1a198, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_1_HIGH", 0x1a19c, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_2_LOW", 0x1a1a0, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_2_HIGH", 0x1a1a4, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_3_LOW", 0x1a1a8, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_3_HIGH", 0x1a1ac, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_4_LOW", 0x1a1b0, 0 },
|
|
{ "NCSI_MACB_SPECIFIC_4_HIGH", 0x1a1b4, 0 },
|
|
{ "NCSI_MACB_TYPE_ID", 0x1a1b8, 0 },
|
|
{ "NCSI_MACB_TX_PAUSE_QUANTUM", 0x1a1bc, 0 },
|
|
{ "NCSI_MACB_USER_IO", 0x1a1c0, 0 },
|
|
{ "UserProgInput", 16, 16 },
|
|
{ "UserProgOutput", 0, 16 },
|
|
{ "NCSI_MACB_WOL_CFG", 0x1a1c4, 0 },
|
|
{ "MCHashEn", 19, 1 },
|
|
{ "Specific1En", 18, 1 },
|
|
{ "ARPEn", 17, 1 },
|
|
{ "MagicPktEn", 16, 1 },
|
|
{ "ARPIPAddr", 0, 16 },
|
|
{ "NCSI_MACB_REV_STATUS", 0x1a1fc, 0 },
|
|
{ "PartRef", 16, 16 },
|
|
{ "DesRev", 0, 16 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_mac_regs[] = {
|
|
{ "MAC_PORT_CFG", 0x30800, 0 },
|
|
{ "MAC_Clk_Sel", 29, 3 },
|
|
{ "SinkTx", 27, 1 },
|
|
{ "SinkTxOnLinkDown", 26, 1 },
|
|
{ "LoopNoFwd", 24, 1 },
|
|
{ "Smux_Rx_Loop", 19, 1 },
|
|
{ "Rx_Lane_Swap", 18, 1 },
|
|
{ "Tx_Lane_Swap", 17, 1 },
|
|
{ "Signal_Det", 14, 1 },
|
|
{ "SmuxTxSel", 9, 1 },
|
|
{ "SmuxRxSel", 8, 1 },
|
|
{ "PortSpeed", 4, 2 },
|
|
{ "Rx_Byte_Swap", 3, 1 },
|
|
{ "Tx_Byte_Swap", 2, 1 },
|
|
{ "Port_Sel", 0, 1 },
|
|
{ "MAC_PORT_RESET_CTRL", 0x30804, 0 },
|
|
{ "TWGDSK_HSSC16B", 31, 1 },
|
|
{ "EEE_RESET", 30, 1 },
|
|
{ "PTP_TIMER", 29, 1 },
|
|
{ "MtipRefReset", 28, 1 },
|
|
{ "MtipTxffReset", 27, 1 },
|
|
{ "MtipRxffReset", 26, 1 },
|
|
{ "MtipRegReset", 25, 1 },
|
|
{ "AEC3Reset", 23, 1 },
|
|
{ "AEC2Reset", 22, 1 },
|
|
{ "AEC1Reset", 21, 1 },
|
|
{ "AEC0Reset", 20, 1 },
|
|
{ "AET3Reset", 19, 1 },
|
|
{ "AET2Reset", 18, 1 },
|
|
{ "AET1Reset", 17, 1 },
|
|
{ "AET0Reset", 16, 1 },
|
|
{ "TXIF_Reset", 12, 1 },
|
|
{ "RXIF_Reset", 11, 1 },
|
|
{ "AuxExt_Reset", 10, 1 },
|
|
{ "MtipSd3TxRst", 9, 1 },
|
|
{ "MtipSd2TxRst", 8, 1 },
|
|
{ "MtipSd1TxRst", 7, 1 },
|
|
{ "MtipSd0TxRst", 6, 1 },
|
|
{ "MtipSd3RxRst", 5, 1 },
|
|
{ "MtipSd2RxRst", 4, 1 },
|
|
{ "MtipSd1RxRst", 3, 1 },
|
|
{ "WOL_Reset", 2, 1 },
|
|
{ "MtipSd0RxRst", 1, 1 },
|
|
{ "HSS_Reset", 0, 1 },
|
|
{ "MAC_PORT_LED_CFG", 0x30808, 0 },
|
|
{ "Led1_Cfg", 5, 3 },
|
|
{ "Led1_Polarity_Inv", 4, 1 },
|
|
{ "Led0_Cfg", 1, 3 },
|
|
{ "Led0_Polarity_Inv", 0, 1 },
|
|
{ "MAC_PORT_LED_COUNTHI", 0x3080c, 0 },
|
|
{ "MAC_PORT_LED_COUNTLO", 0x30810, 0 },
|
|
{ "MAC_PORT_CFG3", 0x30814, 0 },
|
|
{ "FPGA_PTP_PORT", 26, 2 },
|
|
{ "FCSDisCtrl", 25, 1 },
|
|
{ "SigDetCtrl", 24, 1 },
|
|
{ "tx_lane", 23, 1 },
|
|
{ "rx_lane", 22, 1 },
|
|
{ "se_clr", 21, 1 },
|
|
{ "an_ena", 17, 4 },
|
|
{ "sd_rx_clk_ena", 13, 4 },
|
|
{ "sd_tx_clk_ena", 9, 4 },
|
|
{ "SGMIISEL", 8, 1 },
|
|
{ "HSSPLLSEL", 4, 4 },
|
|
{ "HSSC16C20SEL", 0, 4 },
|
|
{ "MAC_PORT_CFG2", 0x30818, 0 },
|
|
{ "Rx_Polarity_Inv", 28, 4 },
|
|
{ "Tx_Polarity_Inv", 24, 4 },
|
|
{ "InstanceNum", 22, 2 },
|
|
{ "StopOnPerr", 21, 1 },
|
|
{ "PatEn", 18, 1 },
|
|
{ "MagicEn", 17, 1 },
|
|
{ "T5_AEC_PMA_TX_READY", 4, 4 },
|
|
{ "T5_AEC_PMA_RX_READY", 0, 4 },
|
|
{ "MAC_PORT_PKT_COUNT", 0x3081c, 0 },
|
|
{ "tx_sop_count", 24, 8 },
|
|
{ "tx_eop_count", 16, 8 },
|
|
{ "rx_sop_count", 8, 8 },
|
|
{ "rx_eop_count", 0, 8 },
|
|
{ "MAC_PORT_CFG4", 0x30820, 0 },
|
|
{ "AEC3_RX_WIDTH", 14, 2 },
|
|
{ "AEC2_RX_WIDTH", 12, 2 },
|
|
{ "AEC1_RX_WIDTH", 10, 2 },
|
|
{ "AEC0_RX_WIDTH", 8, 2 },
|
|
{ "AEC3_TX_WIDTH", 6, 2 },
|
|
{ "AEC2_TX_WIDTH", 4, 2 },
|
|
{ "AEC1_TX_WIDTH", 2, 2 },
|
|
{ "AEC0_TX_WIDTH", 0, 2 },
|
|
{ "MAC_PORT_MAGIC_MACID_LO", 0x30824, 0 },
|
|
{ "MAC_PORT_MAGIC_MACID_HI", 0x30828, 0 },
|
|
{ "MAC_PORT_LINK_STATUS", 0x30834, 0 },
|
|
{ "an_done", 6, 1 },
|
|
{ "align_done", 5, 1 },
|
|
{ "block_lock", 4, 1 },
|
|
{ "remflt", 3, 1 },
|
|
{ "locflt", 2, 1 },
|
|
{ "linkup", 1, 1 },
|
|
{ "linkdn", 0, 1 },
|
|
{ "MAC_PORT_EPIO_DATA0", 0x308c0, 0 },
|
|
{ "MAC_PORT_EPIO_DATA1", 0x308c4, 0 },
|
|
{ "MAC_PORT_EPIO_DATA2", 0x308c8, 0 },
|
|
{ "MAC_PORT_EPIO_DATA3", 0x308cc, 0 },
|
|
{ "MAC_PORT_EPIO_OP", 0x308d0, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Write", 8, 1 },
|
|
{ "Address", 0, 8 },
|
|
{ "MAC_PORT_WOL_STATUS", 0x308d4, 0 },
|
|
{ "MagicDetected", 31, 1 },
|
|
{ "PatDetected", 30, 1 },
|
|
{ "ClearMagic", 4, 1 },
|
|
{ "ClearMatch", 3, 1 },
|
|
{ "MatchedFilter", 0, 3 },
|
|
{ "MAC_PORT_INT_EN", 0x308d8, 0 },
|
|
{ "tx_ts_avail", 29, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "an_page_rcvd", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "MAC_PORT_INT_CAUSE", 0x308dc, 0 },
|
|
{ "tx_ts_avail", 29, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "an_page_rcvd", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "MAC_PORT_PERR_INT_EN", 0x308e0, 0 },
|
|
{ "Perr_pkt_ram", 24, 1 },
|
|
{ "Perr_mask_ram", 23, 1 },
|
|
{ "Perr_crc_ram", 22, 1 },
|
|
{ "rx_dff_seg0", 21, 1 },
|
|
{ "rx_sff_seg0", 20, 1 },
|
|
{ "rx_dff_mac10", 19, 1 },
|
|
{ "rx_sff_mac10", 18, 1 },
|
|
{ "tx_dff_seg0", 17, 1 },
|
|
{ "tx_sff_seg0", 16, 1 },
|
|
{ "tx_dff_mac10", 15, 1 },
|
|
{ "tx_sff_mac10", 14, 1 },
|
|
{ "rx_stats", 13, 1 },
|
|
{ "tx_stats", 12, 1 },
|
|
{ "Perr3_rx_mix", 11, 1 },
|
|
{ "Perr3_rx_sd", 10, 1 },
|
|
{ "Perr3_tx", 9, 1 },
|
|
{ "Perr2_rx_mix", 8, 1 },
|
|
{ "Perr2_rx_sd", 7, 1 },
|
|
{ "Perr2_tx", 6, 1 },
|
|
{ "Perr1_rx_mix", 5, 1 },
|
|
{ "Perr1_rx_sd", 4, 1 },
|
|
{ "Perr1_tx", 3, 1 },
|
|
{ "Perr0_rx_mix", 2, 1 },
|
|
{ "Perr0_rx_sd", 1, 1 },
|
|
{ "Perr0_tx", 0, 1 },
|
|
{ "MAC_PORT_PERR_INT_CAUSE", 0x308e4, 0 },
|
|
{ "Perr_pkt_ram", 24, 1 },
|
|
{ "Perr_mask_ram", 23, 1 },
|
|
{ "Perr_crc_ram", 22, 1 },
|
|
{ "rx_dff_seg0", 21, 1 },
|
|
{ "rx_sff_seg0", 20, 1 },
|
|
{ "rx_dff_mac10", 19, 1 },
|
|
{ "rx_sff_mac10", 18, 1 },
|
|
{ "tx_dff_seg0", 17, 1 },
|
|
{ "tx_sff_seg0", 16, 1 },
|
|
{ "tx_dff_mac10", 15, 1 },
|
|
{ "tx_sff_mac10", 14, 1 },
|
|
{ "rx_stats", 13, 1 },
|
|
{ "tx_stats", 12, 1 },
|
|
{ "Perr3_rx_mix", 11, 1 },
|
|
{ "Perr3_rx_sd", 10, 1 },
|
|
{ "Perr3_tx", 9, 1 },
|
|
{ "Perr2_rx_mix", 8, 1 },
|
|
{ "Perr2_rx_sd", 7, 1 },
|
|
{ "Perr2_tx", 6, 1 },
|
|
{ "Perr1_rx_mix", 5, 1 },
|
|
{ "Perr1_rx_sd", 4, 1 },
|
|
{ "Perr1_tx", 3, 1 },
|
|
{ "Perr0_rx_mix", 2, 1 },
|
|
{ "Perr0_rx_sd", 1, 1 },
|
|
{ "Perr0_tx", 0, 1 },
|
|
{ "MAC_PORT_PERR_ENABLE", 0x308e8, 0 },
|
|
{ "Perr_pkt_ram", 24, 1 },
|
|
{ "Perr_mask_ram", 23, 1 },
|
|
{ "Perr_crc_ram", 22, 1 },
|
|
{ "rx_dff_seg0", 21, 1 },
|
|
{ "rx_sff_seg0", 20, 1 },
|
|
{ "rx_dff_mac10", 19, 1 },
|
|
{ "rx_sff_mac10", 18, 1 },
|
|
{ "tx_dff_seg0", 17, 1 },
|
|
{ "tx_sff_seg0", 16, 1 },
|
|
{ "tx_dff_mac10", 15, 1 },
|
|
{ "tx_sff_mac10", 14, 1 },
|
|
{ "rx_stats", 13, 1 },
|
|
{ "tx_stats", 12, 1 },
|
|
{ "Perr3_rx_mix", 11, 1 },
|
|
{ "Perr3_rx_sd", 10, 1 },
|
|
{ "Perr3_tx", 9, 1 },
|
|
{ "Perr2_rx_mix", 8, 1 },
|
|
{ "Perr2_rx_sd", 7, 1 },
|
|
{ "Perr2_tx", 6, 1 },
|
|
{ "Perr1_rx_mix", 5, 1 },
|
|
{ "Perr1_rx_sd", 4, 1 },
|
|
{ "Perr1_tx", 3, 1 },
|
|
{ "Perr0_rx_mix", 2, 1 },
|
|
{ "Perr0_rx_sd", 1, 1 },
|
|
{ "Perr0_tx", 0, 1 },
|
|
{ "MAC_PORT_PERR_INJECT", 0x308ec, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MAC_PORT_HSS_CFG0", 0x308f0, 0 },
|
|
{ "TXDTS", 31, 1 },
|
|
{ "TXCTS", 30, 1 },
|
|
{ "TXBTS", 29, 1 },
|
|
{ "TXATS", 28, 1 },
|
|
{ "TXDOBS", 27, 1 },
|
|
{ "TXCOBS", 26, 1 },
|
|
{ "TXBOBS", 25, 1 },
|
|
{ "TXAOBS", 24, 1 },
|
|
{ "HSSREFCLKVALIDA", 20, 1 },
|
|
{ "HSSREFCLKVALIDB", 19, 1 },
|
|
{ "HSSRESYNCA", 18, 1 },
|
|
{ "HSSAVDHI", 17, 1 },
|
|
{ "HSSRESYNCB", 16, 1 },
|
|
{ "HSSRECCALA", 15, 1 },
|
|
{ "HSSRXACMODE", 14, 1 },
|
|
{ "HSSRECCALB", 13, 1 },
|
|
{ "HSSPLLBYPA", 12, 1 },
|
|
{ "HSSPLLBYPB", 11, 1 },
|
|
{ "HSSPDWNPLLA", 10, 1 },
|
|
{ "HSSPDWNPLLB", 9, 1 },
|
|
{ "HSSVCOSELA", 8, 1 },
|
|
{ "HSSVCOSELB", 7, 1 },
|
|
{ "HSSCALCOMP", 6, 1 },
|
|
{ "HSSCALENAB", 5, 1 },
|
|
{ "HSSEXTC16SEL", 4, 1 },
|
|
{ "MAC_PORT_HSS_CFG1", 0x308f4, 0 },
|
|
{ "RXACONFIGSEL", 30, 2 },
|
|
{ "RXAQUIET", 29, 1 },
|
|
{ "RXAREFRESH", 28, 1 },
|
|
{ "RXBCONFIGSEL", 26, 2 },
|
|
{ "RXBQUIET", 25, 1 },
|
|
{ "RXBREFRESH", 24, 1 },
|
|
{ "RXCCONFIGSEL", 22, 2 },
|
|
{ "RXCQUIET", 21, 1 },
|
|
{ "RXCREFRESH", 20, 1 },
|
|
{ "RXDCONFIGSEL", 18, 2 },
|
|
{ "RXDQUIET", 17, 1 },
|
|
{ "RXDREFRESH", 16, 1 },
|
|
{ "TXACONFIGSEL", 14, 2 },
|
|
{ "TXAQUIET", 13, 1 },
|
|
{ "TXAREFRESH", 12, 1 },
|
|
{ "TXBCONFIGSEL", 10, 2 },
|
|
{ "TXBQUIET", 9, 1 },
|
|
{ "TXBREFRESH", 8, 1 },
|
|
{ "TXCCONFIGSEL", 6, 2 },
|
|
{ "TXCQUIET", 5, 1 },
|
|
{ "TXCREFRESH", 4, 1 },
|
|
{ "TXDCONFIGSEL", 2, 2 },
|
|
{ "TXDQUIET", 1, 1 },
|
|
{ "TXDREFRESH", 0, 1 },
|
|
{ "MAC_PORT_HSS_CFG2", 0x308f8, 0 },
|
|
{ "RXAASSTCLK", 31, 1 },
|
|
{ "T5RXAPRBSRST", 30, 1 },
|
|
{ "RXBASSTCLK", 29, 1 },
|
|
{ "T5RXBPRBSRST", 28, 1 },
|
|
{ "RXCASSTCLK", 27, 1 },
|
|
{ "T5RXCPRBSRST", 26, 1 },
|
|
{ "RXDASSTCLK", 25, 1 },
|
|
{ "T5RXDPRBSRST", 24, 1 },
|
|
{ "RXDDATASYNC", 23, 1 },
|
|
{ "RXCDATASYNC", 22, 1 },
|
|
{ "RXBDATASYNC", 21, 1 },
|
|
{ "RXADATASYNC", 20, 1 },
|
|
{ "RXDEARLYIN", 19, 1 },
|
|
{ "RXDLATEIN", 18, 1 },
|
|
{ "RXDPHSLOCK", 17, 1 },
|
|
{ "RXDPHSDNIN", 16, 1 },
|
|
{ "RXDPHSUPIN", 15, 1 },
|
|
{ "RXCEARLYIN", 14, 1 },
|
|
{ "RXCLATEIN", 13, 1 },
|
|
{ "RXCPHSLOCK", 12, 1 },
|
|
{ "RXCPHSDNIN", 11, 1 },
|
|
{ "RXCPHSUPIN", 10, 1 },
|
|
{ "RXBEARLYIN", 9, 1 },
|
|
{ "RXBLATEIN", 8, 1 },
|
|
{ "RXBPHSLOCK", 7, 1 },
|
|
{ "RXBPHSDNIN", 6, 1 },
|
|
{ "RXBPHSUPIN", 5, 1 },
|
|
{ "RXAEARLYIN", 4, 1 },
|
|
{ "RXALATEIN", 3, 1 },
|
|
{ "RXAPHSLOCK", 2, 1 },
|
|
{ "RXAPHSDNIN", 1, 1 },
|
|
{ "RXAPHSUPIN", 0, 1 },
|
|
{ "MAC_PORT_HSS_CFG3", 0x308fc, 0 },
|
|
{ "HSSCALSSTN", 25, 3 },
|
|
{ "HSSCALSSTP", 22, 3 },
|
|
{ "HSSVBOOSTDIVB", 19, 3 },
|
|
{ "HSSVBOOSTDIVA", 16, 3 },
|
|
{ "HSSPLLCONFIGB", 8, 8 },
|
|
{ "HSSPLLCONFIGA", 0, 8 },
|
|
{ "MAC_PORT_HSS_CFG4", 0x30900, 0 },
|
|
{ "HSSDIVSELA", 9, 9 },
|
|
{ "HSSDIVSELB", 0, 9 },
|
|
{ "MAC_PORT_HSS_STATUS", 0x30904, 0 },
|
|
{ "RXDPRBSSYNC", 15, 1 },
|
|
{ "RXCPRBSSYNC", 14, 1 },
|
|
{ "RXBPRBSSYNC", 13, 1 },
|
|
{ "RXAPRBSSYNC", 12, 1 },
|
|
{ "RXDPRBSERR", 11, 1 },
|
|
{ "RXCPRBSERR", 10, 1 },
|
|
{ "RXBPRBSERR", 9, 1 },
|
|
{ "RXAPRBSERR", 8, 1 },
|
|
{ "RXDSIGDET", 7, 1 },
|
|
{ "RXCSIGDET", 6, 1 },
|
|
{ "RXBSIGDET", 5, 1 },
|
|
{ "RXASIGDET", 4, 1 },
|
|
{ "HSSPLLLOCKB", 3, 1 },
|
|
{ "HSSPLLLOCKA", 2, 1 },
|
|
{ "HSSPRTREADYB", 1, 1 },
|
|
{ "HSSPRTREADYA", 0, 1 },
|
|
{ "MAC_PORT_HSS_EEE_STATUS", 0x30908, 0 },
|
|
{ "RXAQUIET_STATUS", 15, 1 },
|
|
{ "RXAREFRESH_STATUS", 14, 1 },
|
|
{ "RXBQUIET_STATUS", 13, 1 },
|
|
{ "RXBREFRESH_STATUS", 12, 1 },
|
|
{ "RXCQUIET_STATUS", 11, 1 },
|
|
{ "RXCREFRESH_STATUS", 10, 1 },
|
|
{ "RXDQUIET_STATUS", 9, 1 },
|
|
{ "RXDREFRESH_STATUS", 8, 1 },
|
|
{ "TXAQUIET_STATUS", 7, 1 },
|
|
{ "TXAREFRESH_STATUS", 6, 1 },
|
|
{ "TXBQUIET_STATUS", 5, 1 },
|
|
{ "TXBREFRESH_STATUS", 4, 1 },
|
|
{ "TXCQUIET_STATUS", 3, 1 },
|
|
{ "TXCREFRESH_STATUS", 2, 1 },
|
|
{ "TXDQUIET_STATUS", 1, 1 },
|
|
{ "TXDREFRESH_STATUS", 0, 1 },
|
|
{ "MAC_PORT_HSS_SIGDET_STATUS", 0x3090c, 0 },
|
|
{ "MAC_PORT_HSS_PL_CTL", 0x30910, 0 },
|
|
{ "TOV", 16, 8 },
|
|
{ "TSU", 8, 8 },
|
|
{ "IPW", 0, 8 },
|
|
{ "MAC_PORT_RUNT_FRAME", 0x30914, 0 },
|
|
{ "runtclear", 16, 1 },
|
|
{ "runt", 0, 16 },
|
|
{ "MAC_PORT_EEE_STATUS", 0x30918, 0 },
|
|
{ "eee_tx_10g_state", 10, 2 },
|
|
{ "eee_rx_10g_state", 8, 2 },
|
|
{ "eee_tx_1g_state", 6, 2 },
|
|
{ "eee_rx_1g_state", 4, 2 },
|
|
{ "pma_rx_refresh", 3, 1 },
|
|
{ "pma_rx_quiet", 2, 1 },
|
|
{ "pma_tx_refresh", 1, 1 },
|
|
{ "pma_tx_quiet", 0, 1 },
|
|
{ "MAC_PORT_CGEN", 0x3091c, 0 },
|
|
{ "CGEN", 8, 1 },
|
|
{ "sd7_CGEN", 7, 1 },
|
|
{ "sd6_CGEN", 6, 1 },
|
|
{ "sd5_CGEN", 5, 1 },
|
|
{ "sd4_CGEN", 4, 1 },
|
|
{ "sd3_CGEN", 3, 1 },
|
|
{ "sd2_CGEN", 2, 1 },
|
|
{ "sd1_CGEN", 1, 1 },
|
|
{ "sd0_CGEN", 0, 1 },
|
|
{ "MAC_PORT_CGEN_MTIP", 0x30920, 0 },
|
|
{ "MACSEG5_CGEN", 11, 1 },
|
|
{ "PCSSEG5_CGEN", 10, 1 },
|
|
{ "MACSEG4_CGEN", 9, 1 },
|
|
{ "PCSSEG4_CGEN", 8, 1 },
|
|
{ "MACSEG3_CGEN", 7, 1 },
|
|
{ "PCSSEG3_CGEN", 6, 1 },
|
|
{ "MACSEG2_CGEN", 5, 1 },
|
|
{ "PCSSEG2_CGEN", 4, 1 },
|
|
{ "MACSEG1_CGEN", 3, 1 },
|
|
{ "PCSSEG1_CGEN", 2, 1 },
|
|
{ "MACSEG0_CGEN", 1, 1 },
|
|
{ "PCSSEG0_CGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_TS_ID", 0x30924, 0 },
|
|
{ "MAC_PORT_TX_TS_VAL_LO", 0x30928, 0 },
|
|
{ "MAC_PORT_TX_TS_VAL_HI", 0x3092c, 0 },
|
|
{ "MAC_PORT_EEE_CTL", 0x30930, 0 },
|
|
{ "EEE_CTRL", 2, 30 },
|
|
{ "TICK_START", 1, 1 },
|
|
{ "En", 0, 1 },
|
|
{ "MAC_PORT_EEE_TX_CTL", 0x30934, 0 },
|
|
{ "WAKE_TIMER", 16, 16 },
|
|
{ "HSS_TIMER", 5, 4 },
|
|
{ "HSS_CTL", 4, 1 },
|
|
{ "LPI_ACTIVE", 3, 1 },
|
|
{ "LPI_TXHOLD", 2, 1 },
|
|
{ "LPI_REQ", 1, 1 },
|
|
{ "EEE_TX_RESET", 0, 1 },
|
|
{ "MAC_PORT_EEE_RX_CTL", 0x30938, 0 },
|
|
{ "WAKE_TIMER", 16, 16 },
|
|
{ "HSS_TIMER", 5, 4 },
|
|
{ "HSS_CTL", 4, 1 },
|
|
{ "LPI_IND", 1, 1 },
|
|
{ "EEE_RX_RESET", 0, 1 },
|
|
{ "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x3093c, 0 },
|
|
{ "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x30940, 0 },
|
|
{ "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x30944, 0 },
|
|
{ "MAC_PORT_EEE_TX_1G_SLEEP_TIMER", 0x30948, 0 },
|
|
{ "MAC_PORT_EEE_TX_1G_QUIET_TIMER", 0x3094c, 0 },
|
|
{ "MAC_PORT_EEE_TX_1G_REFRESH_TIMER", 0x30950, 0 },
|
|
{ "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x30954, 0 },
|
|
{ "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x30958, 0 },
|
|
{ "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x3095c, 0 },
|
|
{ "MAC_PORT_EEE_RX_1G_QUIET_TIMER", 0x30960, 0 },
|
|
{ "MAC_PORT_EEE_RX_1G_WAKE_TIMER", 0x30964, 0 },
|
|
{ "MAC_PORT_EEE_WF_COUNT", 0x30968, 0 },
|
|
{ "wake_cnt_clr", 16, 1 },
|
|
{ "wake_cnt", 0, 16 },
|
|
{ "MAC_PORT_PTP_TIMER_RD0_LO", 0x3096c, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_RD0_HI", 0x30970, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_RD1_LO", 0x30974, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_RD1_HI", 0x30978, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_WR_LO", 0x3097c, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_WR_HI", 0x30980, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_OFFSET_0", 0x30984, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_OFFSET_1", 0x30988, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_OFFSET_2", 0x3098c, 0 },
|
|
{ "MAC_PORT_PTP_SUM_LO", 0x30990, 0 },
|
|
{ "MAC_PORT_PTP_SUM_HI", 0x30994, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_INCR0", 0x30998, 0 },
|
|
{ "Y", 16, 16 },
|
|
{ "X", 0, 16 },
|
|
{ "MAC_PORT_PTP_TIMER_INCR1", 0x3099c, 0 },
|
|
{ "Y_TICK", 16, 16 },
|
|
{ "X_TICK", 0, 16 },
|
|
{ "MAC_PORT_PTP_DRIFT_ADJUST_COUNT", 0x309a0, 0 },
|
|
{ "MAC_PORT_PTP_OFFSET_ADJUST_FINE", 0x309a4, 0 },
|
|
{ "B", 16, 16 },
|
|
{ "A", 0, 16 },
|
|
{ "MAC_PORT_PTP_OFFSET_ADJUST_TOTAL", 0x309a8, 0 },
|
|
{ "MAC_PORT_PTP_CFG", 0x309ac, 0 },
|
|
{ "FRZ", 18, 1 },
|
|
{ "OFFSER_ADJUST_SIGN", 17, 1 },
|
|
{ "ADD_OFFSET", 16, 1 },
|
|
{ "CYCLE1", 8, 8 },
|
|
{ "Q", 0, 8 },
|
|
{ "MAC_PORT_MTIP_REVISION", 0x30a00, 0 },
|
|
{ "CUSTREV", 16, 16 },
|
|
{ "VER", 8, 8 },
|
|
{ "REV", 0, 8 },
|
|
{ "MAC_PORT_MTIP_SCRATCH", 0x30a04, 0 },
|
|
{ "MAC_PORT_MTIP_COMMAND_CONFIG", 0x30a08, 0 },
|
|
{ "TX_FLUSH", 22, 1 },
|
|
{ "RX_SFD_ANY", 21, 1 },
|
|
{ "PAUSE_PFC_COMP", 20, 1 },
|
|
{ "PFC_MODE", 19, 1 },
|
|
{ "RS_COL_CNT_EXT", 18, 1 },
|
|
{ "NO_LGTH_CHECK", 17, 1 },
|
|
{ "SEND_IDLE", 16, 1 },
|
|
{ "PHY_TXENA", 15, 1 },
|
|
{ "RX_ERR_DISC", 14, 1 },
|
|
{ "CMD_FRAME_ENA", 13, 1 },
|
|
{ "SW_RESET", 12, 1 },
|
|
{ "TX_PAD_EN", 11, 1 },
|
|
{ "LOOPBACK_EN", 10, 1 },
|
|
{ "TX_ADDR_INS", 9, 1 },
|
|
{ "PAUSE_IGNORE", 8, 1 },
|
|
{ "PAUSE_FWD", 7, 1 },
|
|
{ "CRC_FWD", 6, 1 },
|
|
{ "PAD_EN", 5, 1 },
|
|
{ "PROMIS_EN", 4, 1 },
|
|
{ "WAN_MODE", 3, 1 },
|
|
{ "RX_ENA", 1, 1 },
|
|
{ "TX_ENA", 0, 1 },
|
|
{ "MAC_PORT_MTIP_MAC_ADDR_0", 0x30a0c, 0 },
|
|
{ "MAC_PORT_MTIP_MAC_ADDR_1", 0x30a10, 0 },
|
|
{ "MAC_PORT_MTIP_FRM_LENGTH", 0x30a14, 0 },
|
|
{ "MAC_PORT_MTIP_RX_FIFO_SECTIONS", 0x30a1c, 0 },
|
|
{ "AVAIL", 16, 16 },
|
|
{ "EMPTY", 0, 16 },
|
|
{ "MAC_PORT_MTIP_TX_FIFO_SECTIONS", 0x30a20, 0 },
|
|
{ "AVAIL", 16, 16 },
|
|
{ "EMPTY", 0, 16 },
|
|
{ "MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E", 0x30a24, 0 },
|
|
{ "AlmstFull", 16, 16 },
|
|
{ "AlmstEmpty", 0, 16 },
|
|
{ "MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E", 0x30a28, 0 },
|
|
{ "AlmstFull", 16, 16 },
|
|
{ "AlmstEmpty", 0, 16 },
|
|
{ "MAC_PORT_MTIP_HASHTABLE_LOAD", 0x30a2c, 0 },
|
|
{ "ENABLE", 8, 1 },
|
|
{ "ADDR", 0, 6 },
|
|
{ "MAC_PORT_MTIP_MAC_STATUS", 0x30a40, 0 },
|
|
{ "TS_AVAIL", 3, 1 },
|
|
{ "PHY_LOS", 2, 1 },
|
|
{ "RX_REM_FAULT", 1, 1 },
|
|
{ "RX_LOC_FAULT", 0, 1 },
|
|
{ "MAC_PORT_MTIP_TX_IPG_LENGTH", 0x30a44, 0 },
|
|
{ "MAC_PORT_MTIP_MAC_CREDIT_TRIGGER", 0x30a48, 0 },
|
|
{ "MAC_PORT_MTIP_INIT_CREDIT", 0x30a4c, 0 },
|
|
{ "MAC_PORT_MTIP_CURRENT_CREDIT", 0x30a50, 0 },
|
|
{ "MAC_PORT_RX_PAUSE_STATUS", 0x30a74, 0 },
|
|
{ "MAC_PORT_MTIP_TS_TIMESTAMP", 0x30a7c, 0 },
|
|
{ "MAC_PORT_AFRAMESTRANSMITTEDOK", 0x30a80, 0 },
|
|
{ "MAC_PORT_AFRAMESTRANSMITTEDOKHI", 0x30a84, 0 },
|
|
{ "MAC_PORT_AFRAMESRECEIVEDOK", 0x30a88, 0 },
|
|
{ "MAC_PORT_AFRAMESRECEIVEDOKHI", 0x30a8c, 0 },
|
|
{ "MAC_PORT_AFRAMECHECKSEQUENCEERRORS", 0x30a90, 0 },
|
|
{ "MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI", 0x30a94, 0 },
|
|
{ "MAC_PORT_AALIGNMENTERRORS", 0x30a98, 0 },
|
|
{ "MAC_PORT_AALIGNMENTERRORSHI", 0x30a9c, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED", 0x30aa0, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI", 0x30aa4, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED", 0x30aa8, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI", 0x30aac, 0 },
|
|
{ "MAC_PORT_AFRAMETOOLONGERRORS", 0x30ab0, 0 },
|
|
{ "MAC_PORT_AFRAMETOOLONGERRORSHI", 0x30ab4, 0 },
|
|
{ "MAC_PORT_AINRANGELENGTHERRORS", 0x30ab8, 0 },
|
|
{ "MAC_PORT_AINRANGELENGTHERRORSHI", 0x30abc, 0 },
|
|
{ "MAC_PORT_VLANTRANSMITTEDOK", 0x30ac0, 0 },
|
|
{ "MAC_PORT_VLANTRANSMITTEDOKHI", 0x30ac4, 0 },
|
|
{ "MAC_PORT_VLANRECEIVEDOK", 0x30ac8, 0 },
|
|
{ "MAC_PORT_VLANRECEIVEDOKHI", 0x30acc, 0 },
|
|
{ "MAC_PORT_AOCTETSTRANSMITTEDOK", 0x30ad0, 0 },
|
|
{ "MAC_PORT_AOCTETSTRANSMITTEDOKHI", 0x30ad4, 0 },
|
|
{ "MAC_PORT_AOCTETSRECEIVEDOK", 0x30ad8, 0 },
|
|
{ "MAC_PORT_AOCTETSRECEIVEDOKHI", 0x30adc, 0 },
|
|
{ "MAC_PORT_IFINUCASTPKTS", 0x30ae0, 0 },
|
|
{ "MAC_PORT_IFINUCASTPKTSHI", 0x30ae4, 0 },
|
|
{ "MAC_PORT_IFINMULTICASTPKTS", 0x30ae8, 0 },
|
|
{ "MAC_PORT_IFINMULTICASTPKTSHI", 0x30aec, 0 },
|
|
{ "MAC_PORT_IFINBROADCASTPKTS", 0x30af0, 0 },
|
|
{ "MAC_PORT_IFINBROADCASTPKTSHI", 0x30af4, 0 },
|
|
{ "MAC_PORT_IFOUTERRORS", 0x30af8, 0 },
|
|
{ "MAC_PORT_IFOUTERRORSHI", 0x30afc, 0 },
|
|
{ "MAC_PORT_IFOUTUCASTPKTS", 0x30b08, 0 },
|
|
{ "MAC_PORT_IFOUTUCASTPKTSHI", 0x30b0c, 0 },
|
|
{ "MAC_PORT_IFOUTMULTICASTPKTS", 0x30b10, 0 },
|
|
{ "MAC_PORT_IFOUTMULTICASTPKTSHI", 0x30b14, 0 },
|
|
{ "MAC_PORT_IFOUTBROADCASTPKTS", 0x30b18, 0 },
|
|
{ "MAC_PORT_IFOUTBROADCASTPKTSHI", 0x30b1c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSDROPEVENTS", 0x30b20, 0 },
|
|
{ "MAC_PORT_ETHERSTATSDROPEVENTSHI", 0x30b24, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOCTETS", 0x30b28, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOCTETSHI", 0x30b2c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS", 0x30b30, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTSHI", 0x30b34, 0 },
|
|
{ "MAC_PORT_ETHERSTATSUNDERSIZEPKTS", 0x30b38, 0 },
|
|
{ "MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI", 0x30b3c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS64OCTETS", 0x30b40, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS64OCTETSHI", 0x30b44, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS65TO127OCTETS", 0x30b48, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI", 0x30b4c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS128TO255OCTETS", 0x30b50, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI", 0x30b54, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS256TO511OCTETS", 0x30b58, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI", 0x30b5c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS", 0x30b60, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI", 0x30b64, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS", 0x30b68, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x30b6c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS", 0x30b70, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI", 0x30b74, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOVERSIZEPKTS", 0x30b78, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOVERSIZEPKTSHI", 0x30b7c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSJABBERS", 0x30b80, 0 },
|
|
{ "MAC_PORT_ETHERSTATSJABBERSHI", 0x30b84, 0 },
|
|
{ "MAC_PORT_ETHERSTATSFRAGMENTS", 0x30b88, 0 },
|
|
{ "MAC_PORT_ETHERSTATSFRAGMENTSHI", 0x30b8c, 0 },
|
|
{ "MAC_PORT_IFINERRORS", 0x30b90, 0 },
|
|
{ "MAC_PORT_IFINERRORSHI", 0x30b94, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0", 0x30b98, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI", 0x30b9c, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1", 0x30ba0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI", 0x30ba4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2", 0x30ba8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI", 0x30bac, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3", 0x30bb0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI", 0x30bb4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4", 0x30bb8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI", 0x30bbc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5", 0x30bc0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI", 0x30bc4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6", 0x30bc8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI", 0x30bcc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7", 0x30bd0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI", 0x30bd4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0", 0x30bd8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI", 0x30bdc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1", 0x30be0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI", 0x30be4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2", 0x30be8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI", 0x30bec, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3", 0x30bf0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI", 0x30bf4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4", 0x30bf8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI", 0x30bfc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5", 0x30c00, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI", 0x30c04, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6", 0x30c08, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI", 0x30c0c, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7", 0x30c10, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI", 0x30c14, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESTRANSMITTED", 0x30c18, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI", 0x30c1c, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESRECEIVED", 0x30c20, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI", 0x30c24, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_CONTROL", 0x30d00, 0 },
|
|
{ "Reset", 15, 1 },
|
|
{ "Loopback", 14, 1 },
|
|
{ "sppedsel1", 13, 1 },
|
|
{ "AN_EN", 12, 1 },
|
|
{ "PWRDWN", 11, 1 },
|
|
{ "Isolate", 10, 1 },
|
|
{ "AN_RESTART", 9, 1 },
|
|
{ "DPLX", 8, 1 },
|
|
{ "CollisionTest", 7, 1 },
|
|
{ "SpeedSel0", 6, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_STATUS", 0x30d04, 0 },
|
|
{ "100BaseT4", 15, 1 },
|
|
{ "100BaseXFullDplx", 14, 1 },
|
|
{ "100BaseXHalfDplx", 13, 1 },
|
|
{ "10MbpsFullDplx", 12, 1 },
|
|
{ "10MbpsHalfDplx", 11, 1 },
|
|
{ "100BaseT2FullDplx", 10, 1 },
|
|
{ "100BaseT2HalfDplx", 9, 1 },
|
|
{ "ExtdStatus", 8, 1 },
|
|
{ "AN_Complete", 5, 1 },
|
|
{ "SGMII_REM_FAULT", 4, 1 },
|
|
{ "AN_Ability", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "JabberDetect", 1, 1 },
|
|
{ "ExtdCapability", 0, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0", 0x30d08, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1", 0x30d0c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_DEV_ABILITY", 0x30d10, 0 },
|
|
{ "NP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "RF2", 13, 1 },
|
|
{ "RF1", 12, 1 },
|
|
{ "PS2", 8, 1 },
|
|
{ "PS1", 7, 1 },
|
|
{ "HD", 6, 1 },
|
|
{ "FD", 5, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_PARTNER_ABILITY", 0x30d14, 0 },
|
|
{ "CuLinkStatus", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "CuDplxStatus", 12, 1 },
|
|
{ "CuSpeed", 10, 2 },
|
|
{ "MAC_PORT_MTIP_SGMII_AN_EXPANSION", 0x30d18, 0 },
|
|
{ "PgRcvd", 1, 1 },
|
|
{ "RealTimePgRcvd", 0, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_DEVICE_NP", 0x30d1c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_PARTNER_NP", 0x30d20, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_EXTENDED_STATUS", 0x30d3c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_LINK_TIMER_LO", 0x30d48, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_LINK_TIMER_HI", 0x30d4c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_IF_MODE", 0x30d50, 0 },
|
|
{ "SGMII_PCS_ENABLE", 5, 1 },
|
|
{ "SGMII_HDUPLEX", 4, 1 },
|
|
{ "SGMII_SPEED", 2, 2 },
|
|
{ "USE_SGMII_AN", 1, 1 },
|
|
{ "SGMII_ENA", 0, 1 },
|
|
{ "MAC_PORT_MTIP_ACT_CTL_SEG", 0x31200, 0 },
|
|
{ "MAC_PORT_MTIP_MODE_CTL_SEG", 0x31204, 0 },
|
|
{ "MAC_PORT_MTIP_TXCLK_CTL_SEG", 0x31208, 0 },
|
|
{ "MAC_PORT_MTIP_TX_PRMBL_CTL_SEG", 0x3120c, 0 },
|
|
{ "MAC_PORT_MTIP_WAN_RS_COL_CNT", 0x31220, 0 },
|
|
{ "MAC_PORT_MTIP_VL_INTVL", 0x31240, 0 },
|
|
{ "VL_INTVL", 1, 1 },
|
|
{ "MAC_PORT_MTIP_MDIO_CFG_STATUS", 0x31600, 0 },
|
|
{ "CLK_DIV", 7, 9 },
|
|
{ "CL45_EN", 6, 1 },
|
|
{ "disable_preamble", 5, 1 },
|
|
{ "mdio_hold_time", 2, 3 },
|
|
{ "mdio_read_err", 1, 1 },
|
|
{ "mdio_busy", 0, 1 },
|
|
{ "MAC_PORT_MTIP_MDIO_COMMAND", 0x31604, 0 },
|
|
{ "read", 15, 1 },
|
|
{ "read_incr", 14, 1 },
|
|
{ "port_addr", 5, 5 },
|
|
{ "dev_addr", 0, 5 },
|
|
{ "MAC_PORT_MTIP_MDIO_DATA", 0x31608, 0 },
|
|
{ "readbusy", 31, 1 },
|
|
{ "data_word", 0, 16 },
|
|
{ "MAC_PORT_MTIP_MDIO_REGADDR", 0x3160c, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_0", 0x31a00, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_1", 0x31a04, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_2", 0x31a08, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_3", 0x31a0c, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_4", 0x31a10, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_5", 0x31a14, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_6", 0x31a18, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_7", 0x31a1c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_CTL", 0x31e00, 0 },
|
|
{ "RESET", 15, 1 },
|
|
{ "LPBK", 14, 1 },
|
|
{ "SPEED_SEL1", 13, 1 },
|
|
{ "LP_MODE", 11, 1 },
|
|
{ "SPEED_SEL0", 6, 1 },
|
|
{ "SPEED", 2, 4 },
|
|
{ "MAC_PORT_MTIP_PCS_STATUS1", 0x31e04, 0 },
|
|
{ "FaultDet", 7, 1 },
|
|
{ "rx_link_status", 2, 1 },
|
|
{ "LoPwrAbl", 1, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_DEVICE_ID0", 0x31e08, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_DEVICE_ID1", 0x31e0c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_SPEED_ABILITY", 0x31e10, 0 },
|
|
{ "100G", 8, 1 },
|
|
{ "40G", 7, 1 },
|
|
{ "10BASE_TL", 1, 1 },
|
|
{ "10G", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_DEVICE_PKG1", 0x31e14, 0 },
|
|
{ "TC", 6, 1 },
|
|
{ "DTEXS", 5, 1 },
|
|
{ "PHYXS", 4, 1 },
|
|
{ "PCS", 3, 1 },
|
|
{ "WIS", 2, 1 },
|
|
{ "PMD_PMA", 1, 1 },
|
|
{ "CL22", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_DEVICE_PKG2", 0x31e18, 0 },
|
|
{ "VendDev2", 15, 1 },
|
|
{ "VendDev1", 14, 1 },
|
|
{ "CL22EXT", 13, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_CTL2", 0x31e1c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_STATUS2", 0x31e20, 0 },
|
|
{ "Device", 15, 1 },
|
|
{ "TxFault", 7, 1 },
|
|
{ "RxFault", 6, 1 },
|
|
{ "100BASE_R", 5, 1 },
|
|
{ "40GBASE_R", 4, 1 },
|
|
{ "10GBASE_T", 3, 1 },
|
|
{ "10GBASE_W", 2, 1 },
|
|
{ "10GBASE_X", 1, 1 },
|
|
{ "10GBASE_R", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_PKG_ID0", 0x31e38, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_PKG_ID1", 0x31e3c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BASER_STATUS1", 0x31e80, 0 },
|
|
{ "RxLinkStatus", 12, 1 },
|
|
{ "RESEREVED", 4, 8 },
|
|
{ "10GPRBS9", 3, 1 },
|
|
{ "10GPRBS31", 2, 1 },
|
|
{ "HiBER", 1, 1 },
|
|
{ "blocklock", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_BASER_STATUS2", 0x31e84, 0 },
|
|
{ "blocklockLL", 15, 1 },
|
|
{ "HiBERLH", 14, 1 },
|
|
{ "HiBERCount", 8, 6 },
|
|
{ "ErrBlkCnt", 0, 8 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_A", 0x31e88, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_A1", 0x31e8c, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_A2", 0x31e90, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_A3", 0x31e94, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_B", 0x31e98, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_B1", 0x31e9c, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_B2", 0x31ea0, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_B3", 0x31ea4, 0 },
|
|
{ "MAC_PORT_MTIP_BASER_TEST_CTRL", 0x31ea8, 0 },
|
|
{ "TXPRBS9", 6, 1 },
|
|
{ "RXPRBS31", 5, 1 },
|
|
{ "TXPRBS31", 4, 1 },
|
|
{ "TxTestPatEn", 3, 1 },
|
|
{ "RxTestPatEn", 2, 1 },
|
|
{ "TestPatSel", 1, 1 },
|
|
{ "DataPatSel", 0, 1 },
|
|
{ "MAC_PORT_MTIP_BASER_TEST_ERR_CNT", 0x31eac, 0 },
|
|
{ "MAC_PORT_MTIP_BER_HIGH_ORDER_CNT", 0x31eb0, 0 },
|
|
{ "MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT", 0x31eb4, 0 },
|
|
{ "HiCountPrsnt", 15, 1 },
|
|
{ "BLOCK_CNT_HI", 0, 14 },
|
|
{ "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1", 0x31ec8, 0 },
|
|
{ "alignstatus", 12, 1 },
|
|
{ "Lane7", 7, 1 },
|
|
{ "Lane6", 6, 1 },
|
|
{ "Lane5", 5, 1 },
|
|
{ "Lane4", 4, 1 },
|
|
{ "Lane3", 3, 1 },
|
|
{ "Lane2", 2, 1 },
|
|
{ "Lane1", 1, 1 },
|
|
{ "Lane0", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2", 0x31ecc, 0 },
|
|
{ "Lane19", 11, 1 },
|
|
{ "Lane18", 10, 1 },
|
|
{ "Lane17", 9, 1 },
|
|
{ "Lane16", 8, 1 },
|
|
{ "Lane15", 7, 1 },
|
|
{ "Lane14", 6, 1 },
|
|
{ "Lane13", 5, 1 },
|
|
{ "Lane12", 4, 1 },
|
|
{ "Lane11", 3, 1 },
|
|
{ "Lane10", 2, 1 },
|
|
{ "Lane9", 1, 1 },
|
|
{ "Lane8", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3", 0x31ed0, 0 },
|
|
{ "AMLOCK7", 7, 1 },
|
|
{ "AMLOCK6", 6, 1 },
|
|
{ "AMLOCK5", 5, 1 },
|
|
{ "AMLOCK4", 4, 1 },
|
|
{ "AMLOCK3", 3, 1 },
|
|
{ "AMLOCK2", 2, 1 },
|
|
{ "AMLOCK1", 1, 1 },
|
|
{ "AMLOCK0", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4", 0x31ed4, 0 },
|
|
{ "AMLOCK19", 11, 1 },
|
|
{ "AMLOCK18", 10, 1 },
|
|
{ "AMLOCK17", 9, 1 },
|
|
{ "AMLOCK16", 8, 1 },
|
|
{ "AMLOCK15", 7, 1 },
|
|
{ "AMLOCK14", 6, 1 },
|
|
{ "AMLOCK13", 5, 1 },
|
|
{ "AMLOCK12", 4, 1 },
|
|
{ "AMLOCK11", 3, 1 },
|
|
{ "AMLOCK10", 2, 1 },
|
|
{ "AMLOCK9", 1, 1 },
|
|
{ "AMLOCK8", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0", 0x31f68, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1", 0x31f6c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2", 0x31f70, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3", 0x31f74, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4", 0x31f78, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5", 0x31f7c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6", 0x31f80, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7", 0x31f84, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8", 0x31f88, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9", 0x31f8c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10", 0x31f90, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11", 0x31f94, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12", 0x31f98, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13", 0x31f9c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14", 0x31fa0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15", 0x31fa4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16", 0x31fa8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17", 0x31fac, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18", 0x31fb0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19", 0x31fb4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_0", 0x31fb8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_1", 0x31fbc, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_2", 0x31fc0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_3", 0x31fc4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_4", 0x31fc8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_5", 0x31fcc, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_6", 0x31fd0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_7", 0x31fd4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_8", 0x31fd8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_9", 0x31fdc, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_10", 0x31fe0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_11", 0x31fe4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_12", 0x31fe8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_13", 0x31fec, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_14", 0x31ff0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_15", 0x31ff4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_16", 0x31ff8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_17", 0x31ffc, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_18", 0x32000, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_19", 0x32004, 0 },
|
|
{ "MAC_PORT_BEAN_CTL", 0x32200, 0 },
|
|
{ "AN_RESET", 15, 1 },
|
|
{ "EXT_NXP_CTRL", 13, 1 },
|
|
{ "BEAN_EN", 12, 1 },
|
|
{ "RESTART_BEAN", 9, 1 },
|
|
{ "MAC_PORT_BEAN_STATUS", 0x32204, 0 },
|
|
{ "PDF", 9, 1 },
|
|
{ "EXT_NXP_STATUS", 7, 1 },
|
|
{ "PAGE_RCVD", 6, 1 },
|
|
{ "BEAN_COMPLETE", 5, 1 },
|
|
{ "REM_FAULT_STATUS", 4, 1 },
|
|
{ "BEAN_ABILITY", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "LP_BEAN_ABILITY", 0, 1 },
|
|
{ "MAC_PORT_BEAN_ABILITY_0", 0x32208, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_1", 0x3220c, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_2", 0x32210, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_0", 0x32214, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_1", 0x32218, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_2", 0x3221c, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_MS_COUNT", 0x32220, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_0", 0x32224, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_BEAN_XNP_1", 0x32228, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_2", 0x3222c, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_0", 0x32230, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_1", 0x32234, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_2", 0x32238, 0 },
|
|
{ "MAC_PORT_BEAN_ETH_STATUS", 0x3223c, 0 },
|
|
{ "100GCR10", 8, 1 },
|
|
{ "40GCR4", 6, 1 },
|
|
{ "40GKR4", 5, 1 },
|
|
{ "FEC", 4, 1 },
|
|
{ "10GKR", 3, 1 },
|
|
{ "10GKX4", 2, 1 },
|
|
{ "1GKX", 1, 1 },
|
|
{ "MAC_PORT_BEAN_CTL_LANE1", 0x32240, 0 },
|
|
{ "AN_RESET", 15, 1 },
|
|
{ "EXT_NXP_CTRL", 13, 1 },
|
|
{ "BEAN_EN", 12, 1 },
|
|
{ "RESTART_BEAN", 9, 1 },
|
|
{ "MAC_PORT_BEAN_STATUS_LANE1", 0x32244, 0 },
|
|
{ "PDF", 9, 1 },
|
|
{ "EXT_NXP_STATUS", 7, 1 },
|
|
{ "PAGE_RCVD", 6, 1 },
|
|
{ "BEAN_COMPLETE", 5, 1 },
|
|
{ "REM_FAULT_STATUS", 4, 1 },
|
|
{ "BEAN_ABILITY", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "LP_BEAN_ABILITY", 0, 1 },
|
|
{ "MAC_PORT_BEAN_ABILITY_0_LANE1", 0x32248, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_1_LANE1", 0x3224c, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_2_LANE1", 0x32250, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_0_LANE1", 0x32254, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_1_LANE1", 0x32258, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_2_LANE1", 0x3225c, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_MS_COUNT_LANE1", 0x32260, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_0_LANE1", 0x32264, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_BEAN_XNP_1_LANE1", 0x32268, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_2_LANE1", 0x3226c, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_0_LANE1", 0x32270, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_1_LANE1", 0x32274, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_2_LANE1", 0x32278, 0 },
|
|
{ "MAC_PORT_BEAN_ETH_STATUS_LANE1", 0x3227c, 0 },
|
|
{ "100GCR10", 8, 1 },
|
|
{ "40GCR4", 6, 1 },
|
|
{ "40GKR4", 5, 1 },
|
|
{ "FEC", 4, 1 },
|
|
{ "10GKR", 3, 1 },
|
|
{ "10GKX4", 2, 1 },
|
|
{ "1GKX", 1, 1 },
|
|
{ "MAC_PORT_BEAN_CTL_LANE2", 0x32280, 0 },
|
|
{ "AN_RESET", 15, 1 },
|
|
{ "EXT_NXP_CTRL", 13, 1 },
|
|
{ "BEAN_EN", 12, 1 },
|
|
{ "RESTART_BEAN", 9, 1 },
|
|
{ "MAC_PORT_BEAN_STATUS_LANE2", 0x32284, 0 },
|
|
{ "PDF", 9, 1 },
|
|
{ "EXT_NXP_STATUS", 7, 1 },
|
|
{ "PAGE_RCVD", 6, 1 },
|
|
{ "BEAN_COMPLETE", 5, 1 },
|
|
{ "REM_FAULT_STATUS", 4, 1 },
|
|
{ "BEAN_ABILITY", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "LP_BEAN_ABILITY", 0, 1 },
|
|
{ "MAC_PORT_BEAN_ABILITY_0_LANE2", 0x32288, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_1_LANE2", 0x3228c, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_2_LANE2", 0x32290, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_0_LANE2", 0x32294, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_1_LANE2", 0x32298, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_2_LANE2", 0x3229c, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_MS_COUNT_LANE2", 0x322a0, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_0_LANE2", 0x322a4, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_BEAN_XNP_1_LANE2", 0x322a8, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_2_LANE2", 0x322ac, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_0_LANE2", 0x322b0, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_1_LANE2", 0x322b4, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_2_LANE2", 0x322b8, 0 },
|
|
{ "MAC_PORT_BEAN_ETH_STATUS_LANE2", 0x322bc, 0 },
|
|
{ "100GCR10", 8, 1 },
|
|
{ "40GCR4", 6, 1 },
|
|
{ "40GKR4", 5, 1 },
|
|
{ "FEC", 4, 1 },
|
|
{ "10GKR", 3, 1 },
|
|
{ "10GKX4", 2, 1 },
|
|
{ "1GKX", 1, 1 },
|
|
{ "MAC_PORT_BEAN_CTL_LANE3", 0x322c0, 0 },
|
|
{ "AN_RESET", 15, 1 },
|
|
{ "EXT_NXP_CTRL", 13, 1 },
|
|
{ "BEAN_EN", 12, 1 },
|
|
{ "RESTART_BEAN", 9, 1 },
|
|
{ "MAC_PORT_BEAN_STATUS_LANE3", 0x322c4, 0 },
|
|
{ "PDF", 9, 1 },
|
|
{ "EXT_NXP_STATUS", 7, 1 },
|
|
{ "PAGE_RCVD", 6, 1 },
|
|
{ "BEAN_COMPLETE", 5, 1 },
|
|
{ "REM_FAULT_STATUS", 4, 1 },
|
|
{ "BEAN_ABILITY", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "LP_BEAN_ABILITY", 0, 1 },
|
|
{ "MAC_PORT_BEAN_ABILITY_0_LANE3", 0x322c8, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_1_LANE3", 0x322cc, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_2_LANE3", 0x322d0, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_0_LANE3", 0x322d4, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_1_LANE3", 0x322d8, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_2_LANE3", 0x322dc, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_MS_COUNT_LANE3", 0x322e0, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_0_LANE3", 0x322e4, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_BEAN_XNP_1_LANE3", 0x322e8, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_2_LANE3", 0x322ec, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_0_LANE3", 0x322f0, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_1_LANE3", 0x322f4, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_2_LANE3", 0x322f8, 0 },
|
|
{ "MAC_PORT_BEAN_ETH_STATUS_LANE3", 0x322fc, 0 },
|
|
{ "100GCR10", 8, 1 },
|
|
{ "40GCR4", 6, 1 },
|
|
{ "40GKR4", 5, 1 },
|
|
{ "FEC", 4, 1 },
|
|
{ "10GKR", 3, 1 },
|
|
{ "10GKX4", 2, 1 },
|
|
{ "1GKX", 1, 1 },
|
|
{ "MAC_PORT_FEC_KR_CONTROL", 0x32600, 0 },
|
|
{ "enable_tr", 1, 1 },
|
|
{ "restart_tr", 0, 1 },
|
|
{ "MAC_PORT_FEC_KR_STATUS", 0x32604, 0 },
|
|
{ "fecKRsigdet", 15, 1 },
|
|
{ "train_fail", 3, 1 },
|
|
{ "startup_status", 2, 1 },
|
|
{ "frame_lock", 1, 1 },
|
|
{ "rx_status", 0, 1 },
|
|
{ "MAC_PORT_FEC_KR_LP_COEFF", 0x32608, 0 },
|
|
{ "Preset", 13, 1 },
|
|
{ "Initialize", 12, 1 },
|
|
{ "CP1_UPD", 4, 2 },
|
|
{ "C0_UPD", 2, 2 },
|
|
{ "CN1_UPD", 0, 2 },
|
|
{ "MAC_PORT_FEC_KR_LP_STAT", 0x3260c, 0 },
|
|
{ "rx_ready", 15, 1 },
|
|
{ "CP1_STAT", 4, 2 },
|
|
{ "C0_STAT", 2, 2 },
|
|
{ "CN1_STAT", 0, 2 },
|
|
{ "MAC_PORT_FEC_KR_LD_COEFF", 0x32610, 0 },
|
|
{ "Preset", 13, 1 },
|
|
{ "Initialize", 12, 1 },
|
|
{ "CP1_UPD", 4, 2 },
|
|
{ "C0_UPD", 2, 2 },
|
|
{ "CN1_UPD", 0, 2 },
|
|
{ "MAC_PORT_FEC_KR_LD_STAT", 0x32614, 0 },
|
|
{ "rx_ready", 15, 1 },
|
|
{ "CP1_STAT", 4, 2 },
|
|
{ "C0_STAT", 2, 2 },
|
|
{ "CN1_STAT", 0, 2 },
|
|
{ "MAC_PORT_FEC_ABILITY", 0x32618, 0 },
|
|
{ "fec_ind_ability", 1, 1 },
|
|
{ "ability", 0, 1 },
|
|
{ "MAC_PORT_FEC_CONTROL", 0x3261c, 0 },
|
|
{ "fec_en_err_ind", 1, 1 },
|
|
{ "fec_en", 0, 1 },
|
|
{ "MAC_PORT_FEC_STATUS", 0x32620, 0 },
|
|
{ "FEC_LOCKED_100", 1, 1 },
|
|
{ "FEC_LOCKED", 0, 1 },
|
|
{ "MAC_PORT_FEC_CERR_CNT_0", 0x32624, 0 },
|
|
{ "MAC_PORT_FEC_CERR_CNT_1", 0x32628, 0 },
|
|
{ "MAC_PORT_FEC_NCERR_CNT_0", 0x3262c, 0 },
|
|
{ "MAC_PORT_FEC_NCERR_CNT_1", 0x32630, 0 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ", 0x32a00, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT", 0x32a04, 0 },
|
|
{ "T5_AE0_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE0_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE0_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE0_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ", 0x32a08, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT", 0x32a0c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE", 0x32a10, 0 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL", 0x32a14, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL", 0x32a18, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE", 0x32a1c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ_1", 0x32a20, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT_1", 0x32a24, 0 },
|
|
{ "T5_AE1_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE1_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE1_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE1_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ_1", 0x32a28, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT_1", 0x32a2c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE_1", 0x32a30, 0 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL_1", 0x32a34, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL_1", 0x32a38, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE_1", 0x32a3c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ_2", 0x32a40, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT_2", 0x32a44, 0 },
|
|
{ "T5_AE2_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE2_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE2_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE2_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ_2", 0x32a48, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT_2", 0x32a4c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE_2", 0x32a50, 0 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL_2", 0x32a54, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL_2", 0x32a58, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE_2", 0x32a5c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ_3", 0x32a60, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT_3", 0x32a64, 0 },
|
|
{ "T5_AE3_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE3_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE3_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE3_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ_3", 0x32a68, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT_3", 0x32a6c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE_3", 0x32a70, 0 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL_3", 0x32a74, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL_3", 0x32a78, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE_3", 0x32a7c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_TX_DIS", 0x32a80, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL", 0x32a84, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET", 0x32a88, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS", 0x32a8c, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AE_TX_DIS_1", 0x32a90, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL_1", 0x32a94, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET_1", 0x32a98, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS_1", 0x32a9c, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AE_TX_DIS_2", 0x32aa0, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL_2", 0x32aa4, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET_2", 0x32aa8, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS_2", 0x32aac, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AE_TX_DIS_3", 0x32ab0, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL_3", 0x32ab4, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET_3", 0x32ab8, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS_3", 0x32abc, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_0", 0x32b00, 0 },
|
|
{ "EN_HOLD_FAIL", 14, 1 },
|
|
{ "INIT_METH", 12, 2 },
|
|
{ "CE_DECS", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_C1", 5, 1 },
|
|
{ "EN_MAX_ST", 4, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0", 0x32b04, 0 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_0", 0x32b08, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0", 0x32b0c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT6", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_0", 0x32b10, 0 },
|
|
{ "AET_STAT", 9, 4 },
|
|
{ "NEU_STATE", 5, 4 },
|
|
{ "CTRL_STATE", 0, 5 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_1", 0x32b20, 0 },
|
|
{ "EN_HOLD_FAIL", 14, 1 },
|
|
{ "INIT_METH", 12, 2 },
|
|
{ "CE_DECS", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_C1", 5, 1 },
|
|
{ "EN_MAX_ST", 4, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1", 0x32b24, 0 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_1", 0x32b28, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1", 0x32b2c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT6", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_1", 0x32b30, 0 },
|
|
{ "AET_STAT", 9, 4 },
|
|
{ "NEU_STATE", 5, 4 },
|
|
{ "CTRL_STATE", 0, 5 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_2", 0x32b40, 0 },
|
|
{ "EN_HOLD_FAIL", 14, 1 },
|
|
{ "INIT_METH", 12, 2 },
|
|
{ "CE_DECS", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_C1", 5, 1 },
|
|
{ "EN_MAX_ST", 4, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2", 0x32b44, 0 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_2", 0x32b48, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2", 0x32b4c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT6", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_2", 0x32b50, 0 },
|
|
{ "AET_STAT", 9, 4 },
|
|
{ "NEU_STATE", 5, 4 },
|
|
{ "CTRL_STATE", 0, 5 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_3", 0x32b60, 0 },
|
|
{ "EN_HOLD_FAIL", 14, 1 },
|
|
{ "INIT_METH", 12, 2 },
|
|
{ "CE_DECS", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_C1", 5, 1 },
|
|
{ "EN_MAX_ST", 4, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3", 0x32b64, 0 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_3", 0x32b68, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3", 0x32b6c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT6", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_3", 0x32b70, 0 },
|
|
{ "AET_STAT", 9, 4 },
|
|
{ "NEU_STATE", 5, 4 },
|
|
{ "CTRL_STATE", 0, 5 },
|
|
{ "MAC_PORT_ANALOG_TEST_MUX", 0x33814, 0 },
|
|
{ "MAC_PORT_BANDGAP_CONTROL", 0x3382c, 0 },
|
|
{ "MAC_PORT_RESISTOR_CALIBRATION_CONTROL", 0x33880, 0 },
|
|
{ "RCCTL1", 5, 1 },
|
|
{ "RCCTL0", 4, 1 },
|
|
{ "RCAMP1", 3, 1 },
|
|
{ "RCAMP0", 2, 1 },
|
|
{ "RCAMPEN", 1, 1 },
|
|
{ "RCRST", 0, 1 },
|
|
{ "MAC_PORT_RESISTOR_CALIBRATION_STATUS_1", 0x33884, 0 },
|
|
{ "RCERR", 1, 1 },
|
|
{ "RCCOMP", 0, 1 },
|
|
{ "MAC_PORT_RESISTOR_CALIBRATION_STATUS_2", 0x33888, 0 },
|
|
{ "MAC_PORT_RESISTOR_CALIBRATION_STATUS_3", 0x3388c, 0 },
|
|
{ "MAC_PORT_MACRO_TEST_CONTROL_6", 0x338e8, 0 },
|
|
{ "LBIST", 7, 1 },
|
|
{ "LOGICTEST", 6, 1 },
|
|
{ "MAVDHI", 5, 1 },
|
|
{ "AUXEN", 4, 1 },
|
|
{ "JTAGMD", 3, 1 },
|
|
{ "RXACMODE", 2, 1 },
|
|
{ "HSSACJPC", 1, 1 },
|
|
{ "HSSACJAC", 0, 1 },
|
|
{ "MAC_PORT_MACRO_TEST_CONTROL_5", 0x338ec, 0 },
|
|
{ "REFVALIDD", 6, 1 },
|
|
{ "REFVALIDC", 5, 1 },
|
|
{ "REFVALIDB", 4, 1 },
|
|
{ "REFVALIDA", 3, 1 },
|
|
{ "REFSELRESET", 2, 1 },
|
|
{ "SOFTRESET", 1, 1 },
|
|
{ "MACROTEST", 0, 1 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0", 0x33b00, 0 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1", 0x33b04, 0 },
|
|
{ "LDET", 4, 1 },
|
|
{ "CCERR", 3, 1 },
|
|
{ "CCCMP", 2, 1 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2", 0x33b08, 0 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3", 0x33b0c, 0 },
|
|
{ "FMIN", 3, 1 },
|
|
{ "FMAX", 2, 1 },
|
|
{ "CVHOLD", 1, 1 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4", 0x33b10, 0 },
|
|
{ "CMETH", 2, 1 },
|
|
{ "RECAL", 1, 1 },
|
|
{ "CCLD", 0, 1 },
|
|
{ "MAC_PORT_PLLA_CHARGE_PUMP_CONTROL", 0x33b28, 0 },
|
|
{ "MAC_PORT_PLLA_PCLK_CONTROL", 0x33b3c, 0 },
|
|
{ "SPEDIV", 3, 5 },
|
|
{ "PCKSEL", 0, 3 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL", 0x33b40, 0 },
|
|
{ "EMIL", 2, 1 },
|
|
{ "EMID", 1, 1 },
|
|
{ "EMIS", 0, 1 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1", 0x33b44, 0 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2", 0x33b48, 0 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3", 0x33b4c, 0 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4", 0x33b50, 0 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_4", 0x33bf0, 0 },
|
|
{ "VBST", 1, 3 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_3", 0x33bf4, 0 },
|
|
{ "RESYNC", 6, 1 },
|
|
{ "RXCLKSEL", 5, 1 },
|
|
{ "FRCBAND", 4, 1 },
|
|
{ "PLLBYP", 3, 1 },
|
|
{ "PDWNP", 2, 1 },
|
|
{ "VCOSEL", 1, 1 },
|
|
{ "DIVSEL8", 0, 1 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_2", 0x33bf8, 0 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_1", 0x33bfc, 0 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0", 0x33c00, 0 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1", 0x33c04, 0 },
|
|
{ "LDET", 4, 1 },
|
|
{ "CCERR", 3, 1 },
|
|
{ "CCCMP", 2, 1 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2", 0x33c08, 0 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3", 0x33c0c, 0 },
|
|
{ "FMIN", 3, 1 },
|
|
{ "FMAX", 2, 1 },
|
|
{ "CVHOLD", 1, 1 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4", 0x33c10, 0 },
|
|
{ "CMETH", 2, 1 },
|
|
{ "RECAL", 1, 1 },
|
|
{ "CCLD", 0, 1 },
|
|
{ "MAC_PORT_PLLB_CHARGE_PUMP_CONTROL", 0x33c28, 0 },
|
|
{ "MAC_PORT_PLLB_PCLK_CONTROL", 0x33c3c, 0 },
|
|
{ "SPEDIV", 3, 5 },
|
|
{ "PCKSEL", 0, 3 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL", 0x33c40, 0 },
|
|
{ "EMIL", 2, 1 },
|
|
{ "EMID", 1, 1 },
|
|
{ "EMIS", 0, 1 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1", 0x33c44, 0 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2", 0x33c48, 0 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3", 0x33c4c, 0 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4", 0x33c50, 0 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_4", 0x33cf0, 0 },
|
|
{ "VBST", 1, 3 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_3", 0x33cf4, 0 },
|
|
{ "RESYNC", 6, 1 },
|
|
{ "RXCLKSEL", 5, 1 },
|
|
{ "FRCBAND", 4, 1 },
|
|
{ "PLLBYP", 3, 1 },
|
|
{ "PDWNP", 2, 1 },
|
|
{ "VCOSEL", 1, 1 },
|
|
{ "DIVSEL8", 0, 1 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_2", 0x33cf8, 0 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_1", 0x33cfc, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE", 0x33000, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL", 0x33004, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL", 0x33008, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL", 0x3300c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33010, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33014, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33018, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3301c, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT", 0x33020, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT", 0x33024, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT", 0x33028, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE", 0x33030, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_POLARITY", 0x33034, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33038, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3303c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x33040, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x33044, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x33048, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x33060, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x33064, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x33068, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x33070, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x33074, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33078, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3307c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33080, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33084, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x33088, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL", 0x3308c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE", 0x33090, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED", 0x33094, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT", 0x33098, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL", 0x3309c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4", 0x330f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3", 0x330f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2", 0x330f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1", 0x330fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x30000, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x30008, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x30010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x30018, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x30020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x30028, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x30030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x30038, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x30040, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE", 0x33100, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL", 0x33104, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL", 0x33108, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL", 0x3310c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33110, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33114, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33118, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3311c, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT", 0x33120, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT", 0x33124, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT", 0x33128, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE", 0x33130, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_POLARITY", 0x33134, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33138, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3313c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x33140, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x33144, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x33148, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x33160, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x33164, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x33168, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x33170, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x33174, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33178, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3317c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33180, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33184, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x33188, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL", 0x3318c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE", 0x33190, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED", 0x33194, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT", 0x33198, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL", 0x3319c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4", 0x331f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3", 0x331f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2", 0x331f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1", 0x331fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x30000, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x30008, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x30010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x30018, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x30020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x30028, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x30030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x30038, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x30040, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE", 0x33400, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL", 0x33404, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL", 0x33408, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL", 0x3340c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33410, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33414, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33418, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3341c, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT", 0x33420, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT", 0x33424, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT", 0x33428, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE", 0x33430, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_POLARITY", 0x33434, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33438, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3343c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x33440, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x33444, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x33448, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x33460, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x33464, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x33468, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x33470, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x33474, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33478, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3347c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33480, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33484, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x33488, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL", 0x3348c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE", 0x33490, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED", 0x33494, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT", 0x33498, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL", 0x3349c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4", 0x334f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3", 0x334f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2", 0x334f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1", 0x334fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x30000, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x30008, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x30010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x30018, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x30020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x30028, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x30030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x30038, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x30040, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE", 0x33500, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL", 0x33504, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL", 0x33508, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL", 0x3350c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33510, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33514, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33518, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3351c, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT", 0x33520, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT", 0x33524, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT", 0x33528, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE", 0x33530, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_POLARITY", 0x33534, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33538, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3353c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x33540, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x33544, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x33548, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x33560, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x33564, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x33568, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x33570, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x33574, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33578, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3357c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33580, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33584, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x33588, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL", 0x3358c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE", 0x33590, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED", 0x33594, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT", 0x33598, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL", 0x3359c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4", 0x335f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3", 0x335f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2", 0x335f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1", 0x335fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x30000, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x30008, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x30010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x30018, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x30020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x30028, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x30030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x30038, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x30040, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE", 0x33900, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL", 0x33904, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL", 0x33908, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL", 0x3390c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x33910, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x33914, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x33918, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3391c, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT", 0x33920, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT", 0x33924, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT", 0x33928, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE", 0x33930, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY", 0x33934, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x33938, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3393c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x33940, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x33944, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x33948, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x33960, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x33964, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x33968, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x33970, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x33974, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x33978, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3397c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x33980, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x33984, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x33988, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL", 0x3398c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE", 0x33990, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED", 0x33994, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT", 0x33998, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL", 0x3399c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4", 0x339f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3", 0x339f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2", 0x339f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1", 0x339fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x30000, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x30008, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x30010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x30018, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x30020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x30028, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x30030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x30038, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x30040, 0 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE", 0x33200, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL", 0x33204, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL", 0x33208, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL", 0x3320c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1", 0x33210, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2", 0x33214, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33218, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3321c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_CONTROL", 0x33220, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1", 0x33224, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2", 0x33228, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1", 0x3322c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2", 0x33230, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3", 0x33234, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1", 0x33238, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3", 0x33240, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN", 0x33248, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ", 0x3324c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL", 0x33250, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3325c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x33260, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x33264, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33270, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC", 0x33274, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS", 0x33278, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1", 0x3327c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2", 0x33280, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2", 0x33284, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2", 0x33288, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4", 0x3328c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4", 0x33290, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET", 0x33294, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL", 0x33298, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL", 0x3329c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH", 0x332a0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET", 0x332a4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL", 0x332a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS", 0x332ac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x332b0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x332b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x332b8, 0 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_TAP_ENABLE", 0x332c0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1", 0x332c4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H2", 0x332c8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H3", 0x332cc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H4", 0x332d0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H5", 0x332d4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H6_AND_H7", 0x332d8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H8_AND_H9", 0x332dc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H10_AND_H11", 0x332e0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H12", 0x332e4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2", 0x332f8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1", 0x332fc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE", 0x33300, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL", 0x33304, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL", 0x33308, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL", 0x3330c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1", 0x33310, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2", 0x33314, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33318, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3331c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_CONTROL", 0x33320, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1", 0x33324, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2", 0x33328, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1", 0x3332c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2", 0x33330, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3", 0x33334, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1", 0x33338, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3", 0x33340, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN", 0x33348, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ", 0x3334c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL", 0x33350, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3335c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x33360, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x33364, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33370, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC", 0x33374, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS", 0x33378, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1", 0x3337c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2", 0x33380, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2", 0x33384, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2", 0x33388, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4", 0x3338c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4", 0x33390, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET", 0x33394, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL", 0x33398, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL", 0x3339c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH", 0x333a0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET", 0x333a4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL", 0x333a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS", 0x333ac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x333b0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x333b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x333b8, 0 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_TAP_ENABLE", 0x333c0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1", 0x333c4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H2", 0x333c8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H3", 0x333cc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H4", 0x333d0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H5", 0x333d4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H6_AND_H7", 0x333d8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H8_AND_H9", 0x333dc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H10_AND_H11", 0x333e0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H12", 0x333e4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2", 0x333f8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1", 0x333fc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE", 0x33600, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL", 0x33604, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL", 0x33608, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL", 0x3360c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1", 0x33610, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2", 0x33614, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33618, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3361c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_CONTROL", 0x33620, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1", 0x33624, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2", 0x33628, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1", 0x3362c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2", 0x33630, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3", 0x33634, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1", 0x33638, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3", 0x33640, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN", 0x33648, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ", 0x3364c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL", 0x33650, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3365c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x33660, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x33664, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33670, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC", 0x33674, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS", 0x33678, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1", 0x3367c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2", 0x33680, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2", 0x33684, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2", 0x33688, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4", 0x3368c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4", 0x33690, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET", 0x33694, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL", 0x33698, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL", 0x3369c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH", 0x336a0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET", 0x336a4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL", 0x336a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS", 0x336ac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x336b0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x336b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x336b8, 0 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_TAP_ENABLE", 0x336c0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1", 0x336c4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H2", 0x336c8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H3", 0x336cc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H4", 0x336d0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H5", 0x336d4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H6_AND_H7", 0x336d8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H8_AND_H9", 0x336dc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H10_AND_H11", 0x336e0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H12", 0x336e4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2", 0x336f8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1", 0x336fc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE", 0x33700, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL", 0x33704, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL", 0x33708, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL", 0x3370c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1", 0x33710, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2", 0x33714, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33718, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3371c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_CONTROL", 0x33720, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1", 0x33724, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2", 0x33728, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1", 0x3372c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2", 0x33730, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3", 0x33734, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1", 0x33738, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3", 0x33740, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN", 0x33748, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ", 0x3374c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL", 0x33750, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3375c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x33760, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x33764, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33770, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC", 0x33774, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS", 0x33778, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1", 0x3377c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2", 0x33780, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2", 0x33784, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2", 0x33788, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4", 0x3378c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4", 0x33790, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET", 0x33794, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL", 0x33798, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL", 0x3379c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH", 0x337a0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET", 0x337a4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL", 0x337a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS", 0x337ac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x337b0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x337b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x337b8, 0 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_TAP_ENABLE", 0x337c0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1", 0x337c4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H2", 0x337c8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H3", 0x337cc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H4", 0x337d0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H5", 0x337d4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H6_AND_H7", 0x337d8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H8_AND_H9", 0x337dc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H10_AND_H11", 0x337e0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H12", 0x337e4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2", 0x337f8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1", 0x337fc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE", 0x33a00, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL", 0x33a04, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL", 0x33a08, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL", 0x33a0c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1", 0x33a10, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2", 0x33a14, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x33a18, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x33a1c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_CONTROL", 0x33a20, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1", 0x33a24, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2", 0x33a28, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1", 0x33a2c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2", 0x33a30, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3", 0x33a34, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1", 0x33a38, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3", 0x33a40, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN", 0x33a48, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ", 0x33a4c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL", 0x33a50, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x33a5c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x33a60, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x33a64, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x33a70, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC", 0x33a74, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS", 0x33a78, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1", 0x33a7c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2", 0x33a80, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2", 0x33a84, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2", 0x33a88, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4", 0x33a8c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4", 0x33a90, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET", 0x33a94, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL", 0x33a98, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL", 0x33a9c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH", 0x33aa0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET", 0x33aa4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL", 0x33aa8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS", 0x33aac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x33ab0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x33ab4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x33ab8, 0 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE", 0x33ac0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1", 0x33ac4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H2", 0x33ac8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H3", 0x33acc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H4", 0x33ad0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H5", 0x33ad4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7", 0x33ad8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9", 0x33adc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11", 0x33ae0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H12", 0x33ae4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2", 0x33af8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1", 0x33afc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_CFG", 0x34800, 0 },
|
|
{ "MAC_Clk_Sel", 29, 3 },
|
|
{ "SinkTx", 27, 1 },
|
|
{ "SinkTxOnLinkDown", 26, 1 },
|
|
{ "LoopNoFwd", 24, 1 },
|
|
{ "Smux_Rx_Loop", 19, 1 },
|
|
{ "Rx_Lane_Swap", 18, 1 },
|
|
{ "Tx_Lane_Swap", 17, 1 },
|
|
{ "Signal_Det", 14, 1 },
|
|
{ "SmuxTxSel", 9, 1 },
|
|
{ "SmuxRxSel", 8, 1 },
|
|
{ "PortSpeed", 4, 2 },
|
|
{ "Rx_Byte_Swap", 3, 1 },
|
|
{ "Tx_Byte_Swap", 2, 1 },
|
|
{ "Port_Sel", 0, 1 },
|
|
{ "MAC_PORT_RESET_CTRL", 0x34804, 0 },
|
|
{ "TWGDSK_HSSC16B", 31, 1 },
|
|
{ "EEE_RESET", 30, 1 },
|
|
{ "PTP_TIMER", 29, 1 },
|
|
{ "MtipRefReset", 28, 1 },
|
|
{ "MtipTxffReset", 27, 1 },
|
|
{ "MtipRxffReset", 26, 1 },
|
|
{ "MtipRegReset", 25, 1 },
|
|
{ "AEC3Reset", 23, 1 },
|
|
{ "AEC2Reset", 22, 1 },
|
|
{ "AEC1Reset", 21, 1 },
|
|
{ "AEC0Reset", 20, 1 },
|
|
{ "AET3Reset", 19, 1 },
|
|
{ "AET2Reset", 18, 1 },
|
|
{ "AET1Reset", 17, 1 },
|
|
{ "AET0Reset", 16, 1 },
|
|
{ "TXIF_Reset", 12, 1 },
|
|
{ "RXIF_Reset", 11, 1 },
|
|
{ "AuxExt_Reset", 10, 1 },
|
|
{ "MtipSd3TxRst", 9, 1 },
|
|
{ "MtipSd2TxRst", 8, 1 },
|
|
{ "MtipSd1TxRst", 7, 1 },
|
|
{ "MtipSd0TxRst", 6, 1 },
|
|
{ "MtipSd3RxRst", 5, 1 },
|
|
{ "MtipSd2RxRst", 4, 1 },
|
|
{ "MtipSd1RxRst", 3, 1 },
|
|
{ "WOL_Reset", 2, 1 },
|
|
{ "MtipSd0RxRst", 1, 1 },
|
|
{ "HSS_Reset", 0, 1 },
|
|
{ "MAC_PORT_LED_CFG", 0x34808, 0 },
|
|
{ "Led1_Cfg", 5, 3 },
|
|
{ "Led1_Polarity_Inv", 4, 1 },
|
|
{ "Led0_Cfg", 1, 3 },
|
|
{ "Led0_Polarity_Inv", 0, 1 },
|
|
{ "MAC_PORT_LED_COUNTHI", 0x3480c, 0 },
|
|
{ "MAC_PORT_LED_COUNTLO", 0x34810, 0 },
|
|
{ "MAC_PORT_CFG3", 0x34814, 0 },
|
|
{ "FPGA_PTP_PORT", 26, 2 },
|
|
{ "FCSDisCtrl", 25, 1 },
|
|
{ "SigDetCtrl", 24, 1 },
|
|
{ "tx_lane", 23, 1 },
|
|
{ "rx_lane", 22, 1 },
|
|
{ "se_clr", 21, 1 },
|
|
{ "an_ena", 17, 4 },
|
|
{ "sd_rx_clk_ena", 13, 4 },
|
|
{ "sd_tx_clk_ena", 9, 4 },
|
|
{ "SGMIISEL", 8, 1 },
|
|
{ "HSSPLLSEL", 4, 4 },
|
|
{ "HSSC16C20SEL", 0, 4 },
|
|
{ "MAC_PORT_CFG2", 0x34818, 0 },
|
|
{ "Rx_Polarity_Inv", 28, 4 },
|
|
{ "Tx_Polarity_Inv", 24, 4 },
|
|
{ "InstanceNum", 22, 2 },
|
|
{ "StopOnPerr", 21, 1 },
|
|
{ "PatEn", 18, 1 },
|
|
{ "MagicEn", 17, 1 },
|
|
{ "T5_AEC_PMA_TX_READY", 4, 4 },
|
|
{ "T5_AEC_PMA_RX_READY", 0, 4 },
|
|
{ "MAC_PORT_PKT_COUNT", 0x3481c, 0 },
|
|
{ "tx_sop_count", 24, 8 },
|
|
{ "tx_eop_count", 16, 8 },
|
|
{ "rx_sop_count", 8, 8 },
|
|
{ "rx_eop_count", 0, 8 },
|
|
{ "MAC_PORT_CFG4", 0x34820, 0 },
|
|
{ "AEC3_RX_WIDTH", 14, 2 },
|
|
{ "AEC2_RX_WIDTH", 12, 2 },
|
|
{ "AEC1_RX_WIDTH", 10, 2 },
|
|
{ "AEC0_RX_WIDTH", 8, 2 },
|
|
{ "AEC3_TX_WIDTH", 6, 2 },
|
|
{ "AEC2_TX_WIDTH", 4, 2 },
|
|
{ "AEC1_TX_WIDTH", 2, 2 },
|
|
{ "AEC0_TX_WIDTH", 0, 2 },
|
|
{ "MAC_PORT_MAGIC_MACID_LO", 0x34824, 0 },
|
|
{ "MAC_PORT_MAGIC_MACID_HI", 0x34828, 0 },
|
|
{ "MAC_PORT_LINK_STATUS", 0x34834, 0 },
|
|
{ "an_done", 6, 1 },
|
|
{ "align_done", 5, 1 },
|
|
{ "block_lock", 4, 1 },
|
|
{ "remflt", 3, 1 },
|
|
{ "locflt", 2, 1 },
|
|
{ "linkup", 1, 1 },
|
|
{ "linkdn", 0, 1 },
|
|
{ "MAC_PORT_EPIO_DATA0", 0x348c0, 0 },
|
|
{ "MAC_PORT_EPIO_DATA1", 0x348c4, 0 },
|
|
{ "MAC_PORT_EPIO_DATA2", 0x348c8, 0 },
|
|
{ "MAC_PORT_EPIO_DATA3", 0x348cc, 0 },
|
|
{ "MAC_PORT_EPIO_OP", 0x348d0, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Write", 8, 1 },
|
|
{ "Address", 0, 8 },
|
|
{ "MAC_PORT_WOL_STATUS", 0x348d4, 0 },
|
|
{ "MagicDetected", 31, 1 },
|
|
{ "PatDetected", 30, 1 },
|
|
{ "ClearMagic", 4, 1 },
|
|
{ "ClearMatch", 3, 1 },
|
|
{ "MatchedFilter", 0, 3 },
|
|
{ "MAC_PORT_INT_EN", 0x348d8, 0 },
|
|
{ "tx_ts_avail", 29, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "an_page_rcvd", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "MAC_PORT_INT_CAUSE", 0x348dc, 0 },
|
|
{ "tx_ts_avail", 29, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "an_page_rcvd", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "MAC_PORT_PERR_INT_EN", 0x348e0, 0 },
|
|
{ "Perr_pkt_ram", 24, 1 },
|
|
{ "Perr_mask_ram", 23, 1 },
|
|
{ "Perr_crc_ram", 22, 1 },
|
|
{ "rx_dff_seg0", 21, 1 },
|
|
{ "rx_sff_seg0", 20, 1 },
|
|
{ "rx_dff_mac10", 19, 1 },
|
|
{ "rx_sff_mac10", 18, 1 },
|
|
{ "tx_dff_seg0", 17, 1 },
|
|
{ "tx_sff_seg0", 16, 1 },
|
|
{ "tx_dff_mac10", 15, 1 },
|
|
{ "tx_sff_mac10", 14, 1 },
|
|
{ "rx_stats", 13, 1 },
|
|
{ "tx_stats", 12, 1 },
|
|
{ "Perr3_rx_mix", 11, 1 },
|
|
{ "Perr3_rx_sd", 10, 1 },
|
|
{ "Perr3_tx", 9, 1 },
|
|
{ "Perr2_rx_mix", 8, 1 },
|
|
{ "Perr2_rx_sd", 7, 1 },
|
|
{ "Perr2_tx", 6, 1 },
|
|
{ "Perr1_rx_mix", 5, 1 },
|
|
{ "Perr1_rx_sd", 4, 1 },
|
|
{ "Perr1_tx", 3, 1 },
|
|
{ "Perr0_rx_mix", 2, 1 },
|
|
{ "Perr0_rx_sd", 1, 1 },
|
|
{ "Perr0_tx", 0, 1 },
|
|
{ "MAC_PORT_PERR_INT_CAUSE", 0x348e4, 0 },
|
|
{ "Perr_pkt_ram", 24, 1 },
|
|
{ "Perr_mask_ram", 23, 1 },
|
|
{ "Perr_crc_ram", 22, 1 },
|
|
{ "rx_dff_seg0", 21, 1 },
|
|
{ "rx_sff_seg0", 20, 1 },
|
|
{ "rx_dff_mac10", 19, 1 },
|
|
{ "rx_sff_mac10", 18, 1 },
|
|
{ "tx_dff_seg0", 17, 1 },
|
|
{ "tx_sff_seg0", 16, 1 },
|
|
{ "tx_dff_mac10", 15, 1 },
|
|
{ "tx_sff_mac10", 14, 1 },
|
|
{ "rx_stats", 13, 1 },
|
|
{ "tx_stats", 12, 1 },
|
|
{ "Perr3_rx_mix", 11, 1 },
|
|
{ "Perr3_rx_sd", 10, 1 },
|
|
{ "Perr3_tx", 9, 1 },
|
|
{ "Perr2_rx_mix", 8, 1 },
|
|
{ "Perr2_rx_sd", 7, 1 },
|
|
{ "Perr2_tx", 6, 1 },
|
|
{ "Perr1_rx_mix", 5, 1 },
|
|
{ "Perr1_rx_sd", 4, 1 },
|
|
{ "Perr1_tx", 3, 1 },
|
|
{ "Perr0_rx_mix", 2, 1 },
|
|
{ "Perr0_rx_sd", 1, 1 },
|
|
{ "Perr0_tx", 0, 1 },
|
|
{ "MAC_PORT_PERR_ENABLE", 0x348e8, 0 },
|
|
{ "Perr_pkt_ram", 24, 1 },
|
|
{ "Perr_mask_ram", 23, 1 },
|
|
{ "Perr_crc_ram", 22, 1 },
|
|
{ "rx_dff_seg0", 21, 1 },
|
|
{ "rx_sff_seg0", 20, 1 },
|
|
{ "rx_dff_mac10", 19, 1 },
|
|
{ "rx_sff_mac10", 18, 1 },
|
|
{ "tx_dff_seg0", 17, 1 },
|
|
{ "tx_sff_seg0", 16, 1 },
|
|
{ "tx_dff_mac10", 15, 1 },
|
|
{ "tx_sff_mac10", 14, 1 },
|
|
{ "rx_stats", 13, 1 },
|
|
{ "tx_stats", 12, 1 },
|
|
{ "Perr3_rx_mix", 11, 1 },
|
|
{ "Perr3_rx_sd", 10, 1 },
|
|
{ "Perr3_tx", 9, 1 },
|
|
{ "Perr2_rx_mix", 8, 1 },
|
|
{ "Perr2_rx_sd", 7, 1 },
|
|
{ "Perr2_tx", 6, 1 },
|
|
{ "Perr1_rx_mix", 5, 1 },
|
|
{ "Perr1_rx_sd", 4, 1 },
|
|
{ "Perr1_tx", 3, 1 },
|
|
{ "Perr0_rx_mix", 2, 1 },
|
|
{ "Perr0_rx_sd", 1, 1 },
|
|
{ "Perr0_tx", 0, 1 },
|
|
{ "MAC_PORT_PERR_INJECT", 0x348ec, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MAC_PORT_HSS_CFG0", 0x348f0, 0 },
|
|
{ "TXDTS", 31, 1 },
|
|
{ "TXCTS", 30, 1 },
|
|
{ "TXBTS", 29, 1 },
|
|
{ "TXATS", 28, 1 },
|
|
{ "TXDOBS", 27, 1 },
|
|
{ "TXCOBS", 26, 1 },
|
|
{ "TXBOBS", 25, 1 },
|
|
{ "TXAOBS", 24, 1 },
|
|
{ "HSSREFCLKVALIDA", 20, 1 },
|
|
{ "HSSREFCLKVALIDB", 19, 1 },
|
|
{ "HSSRESYNCA", 18, 1 },
|
|
{ "HSSAVDHI", 17, 1 },
|
|
{ "HSSRESYNCB", 16, 1 },
|
|
{ "HSSRECCALA", 15, 1 },
|
|
{ "HSSRXACMODE", 14, 1 },
|
|
{ "HSSRECCALB", 13, 1 },
|
|
{ "HSSPLLBYPA", 12, 1 },
|
|
{ "HSSPLLBYPB", 11, 1 },
|
|
{ "HSSPDWNPLLA", 10, 1 },
|
|
{ "HSSPDWNPLLB", 9, 1 },
|
|
{ "HSSVCOSELA", 8, 1 },
|
|
{ "HSSVCOSELB", 7, 1 },
|
|
{ "HSSCALCOMP", 6, 1 },
|
|
{ "HSSCALENAB", 5, 1 },
|
|
{ "HSSEXTC16SEL", 4, 1 },
|
|
{ "MAC_PORT_HSS_CFG1", 0x348f4, 0 },
|
|
{ "RXACONFIGSEL", 30, 2 },
|
|
{ "RXAQUIET", 29, 1 },
|
|
{ "RXAREFRESH", 28, 1 },
|
|
{ "RXBCONFIGSEL", 26, 2 },
|
|
{ "RXBQUIET", 25, 1 },
|
|
{ "RXBREFRESH", 24, 1 },
|
|
{ "RXCCONFIGSEL", 22, 2 },
|
|
{ "RXCQUIET", 21, 1 },
|
|
{ "RXCREFRESH", 20, 1 },
|
|
{ "RXDCONFIGSEL", 18, 2 },
|
|
{ "RXDQUIET", 17, 1 },
|
|
{ "RXDREFRESH", 16, 1 },
|
|
{ "TXACONFIGSEL", 14, 2 },
|
|
{ "TXAQUIET", 13, 1 },
|
|
{ "TXAREFRESH", 12, 1 },
|
|
{ "TXBCONFIGSEL", 10, 2 },
|
|
{ "TXBQUIET", 9, 1 },
|
|
{ "TXBREFRESH", 8, 1 },
|
|
{ "TXCCONFIGSEL", 6, 2 },
|
|
{ "TXCQUIET", 5, 1 },
|
|
{ "TXCREFRESH", 4, 1 },
|
|
{ "TXDCONFIGSEL", 2, 2 },
|
|
{ "TXDQUIET", 1, 1 },
|
|
{ "TXDREFRESH", 0, 1 },
|
|
{ "MAC_PORT_HSS_CFG2", 0x348f8, 0 },
|
|
{ "RXAASSTCLK", 31, 1 },
|
|
{ "T5RXAPRBSRST", 30, 1 },
|
|
{ "RXBASSTCLK", 29, 1 },
|
|
{ "T5RXBPRBSRST", 28, 1 },
|
|
{ "RXCASSTCLK", 27, 1 },
|
|
{ "T5RXCPRBSRST", 26, 1 },
|
|
{ "RXDASSTCLK", 25, 1 },
|
|
{ "T5RXDPRBSRST", 24, 1 },
|
|
{ "RXDDATASYNC", 23, 1 },
|
|
{ "RXCDATASYNC", 22, 1 },
|
|
{ "RXBDATASYNC", 21, 1 },
|
|
{ "RXADATASYNC", 20, 1 },
|
|
{ "RXDEARLYIN", 19, 1 },
|
|
{ "RXDLATEIN", 18, 1 },
|
|
{ "RXDPHSLOCK", 17, 1 },
|
|
{ "RXDPHSDNIN", 16, 1 },
|
|
{ "RXDPHSUPIN", 15, 1 },
|
|
{ "RXCEARLYIN", 14, 1 },
|
|
{ "RXCLATEIN", 13, 1 },
|
|
{ "RXCPHSLOCK", 12, 1 },
|
|
{ "RXCPHSDNIN", 11, 1 },
|
|
{ "RXCPHSUPIN", 10, 1 },
|
|
{ "RXBEARLYIN", 9, 1 },
|
|
{ "RXBLATEIN", 8, 1 },
|
|
{ "RXBPHSLOCK", 7, 1 },
|
|
{ "RXBPHSDNIN", 6, 1 },
|
|
{ "RXBPHSUPIN", 5, 1 },
|
|
{ "RXAEARLYIN", 4, 1 },
|
|
{ "RXALATEIN", 3, 1 },
|
|
{ "RXAPHSLOCK", 2, 1 },
|
|
{ "RXAPHSDNIN", 1, 1 },
|
|
{ "RXAPHSUPIN", 0, 1 },
|
|
{ "MAC_PORT_HSS_CFG3", 0x348fc, 0 },
|
|
{ "HSSCALSSTN", 25, 3 },
|
|
{ "HSSCALSSTP", 22, 3 },
|
|
{ "HSSVBOOSTDIVB", 19, 3 },
|
|
{ "HSSVBOOSTDIVA", 16, 3 },
|
|
{ "HSSPLLCONFIGB", 8, 8 },
|
|
{ "HSSPLLCONFIGA", 0, 8 },
|
|
{ "MAC_PORT_HSS_CFG4", 0x34900, 0 },
|
|
{ "HSSDIVSELA", 9, 9 },
|
|
{ "HSSDIVSELB", 0, 9 },
|
|
{ "MAC_PORT_HSS_STATUS", 0x34904, 0 },
|
|
{ "RXDPRBSSYNC", 15, 1 },
|
|
{ "RXCPRBSSYNC", 14, 1 },
|
|
{ "RXBPRBSSYNC", 13, 1 },
|
|
{ "RXAPRBSSYNC", 12, 1 },
|
|
{ "RXDPRBSERR", 11, 1 },
|
|
{ "RXCPRBSERR", 10, 1 },
|
|
{ "RXBPRBSERR", 9, 1 },
|
|
{ "RXAPRBSERR", 8, 1 },
|
|
{ "RXDSIGDET", 7, 1 },
|
|
{ "RXCSIGDET", 6, 1 },
|
|
{ "RXBSIGDET", 5, 1 },
|
|
{ "RXASIGDET", 4, 1 },
|
|
{ "HSSPLLLOCKB", 3, 1 },
|
|
{ "HSSPLLLOCKA", 2, 1 },
|
|
{ "HSSPRTREADYB", 1, 1 },
|
|
{ "HSSPRTREADYA", 0, 1 },
|
|
{ "MAC_PORT_HSS_EEE_STATUS", 0x34908, 0 },
|
|
{ "RXAQUIET_STATUS", 15, 1 },
|
|
{ "RXAREFRESH_STATUS", 14, 1 },
|
|
{ "RXBQUIET_STATUS", 13, 1 },
|
|
{ "RXBREFRESH_STATUS", 12, 1 },
|
|
{ "RXCQUIET_STATUS", 11, 1 },
|
|
{ "RXCREFRESH_STATUS", 10, 1 },
|
|
{ "RXDQUIET_STATUS", 9, 1 },
|
|
{ "RXDREFRESH_STATUS", 8, 1 },
|
|
{ "TXAQUIET_STATUS", 7, 1 },
|
|
{ "TXAREFRESH_STATUS", 6, 1 },
|
|
{ "TXBQUIET_STATUS", 5, 1 },
|
|
{ "TXBREFRESH_STATUS", 4, 1 },
|
|
{ "TXCQUIET_STATUS", 3, 1 },
|
|
{ "TXCREFRESH_STATUS", 2, 1 },
|
|
{ "TXDQUIET_STATUS", 1, 1 },
|
|
{ "TXDREFRESH_STATUS", 0, 1 },
|
|
{ "MAC_PORT_HSS_SIGDET_STATUS", 0x3490c, 0 },
|
|
{ "MAC_PORT_HSS_PL_CTL", 0x34910, 0 },
|
|
{ "TOV", 16, 8 },
|
|
{ "TSU", 8, 8 },
|
|
{ "IPW", 0, 8 },
|
|
{ "MAC_PORT_RUNT_FRAME", 0x34914, 0 },
|
|
{ "runtclear", 16, 1 },
|
|
{ "runt", 0, 16 },
|
|
{ "MAC_PORT_EEE_STATUS", 0x34918, 0 },
|
|
{ "eee_tx_10g_state", 10, 2 },
|
|
{ "eee_rx_10g_state", 8, 2 },
|
|
{ "eee_tx_1g_state", 6, 2 },
|
|
{ "eee_rx_1g_state", 4, 2 },
|
|
{ "pma_rx_refresh", 3, 1 },
|
|
{ "pma_rx_quiet", 2, 1 },
|
|
{ "pma_tx_refresh", 1, 1 },
|
|
{ "pma_tx_quiet", 0, 1 },
|
|
{ "MAC_PORT_CGEN", 0x3491c, 0 },
|
|
{ "CGEN", 8, 1 },
|
|
{ "sd7_CGEN", 7, 1 },
|
|
{ "sd6_CGEN", 6, 1 },
|
|
{ "sd5_CGEN", 5, 1 },
|
|
{ "sd4_CGEN", 4, 1 },
|
|
{ "sd3_CGEN", 3, 1 },
|
|
{ "sd2_CGEN", 2, 1 },
|
|
{ "sd1_CGEN", 1, 1 },
|
|
{ "sd0_CGEN", 0, 1 },
|
|
{ "MAC_PORT_CGEN_MTIP", 0x34920, 0 },
|
|
{ "MACSEG5_CGEN", 11, 1 },
|
|
{ "PCSSEG5_CGEN", 10, 1 },
|
|
{ "MACSEG4_CGEN", 9, 1 },
|
|
{ "PCSSEG4_CGEN", 8, 1 },
|
|
{ "MACSEG3_CGEN", 7, 1 },
|
|
{ "PCSSEG3_CGEN", 6, 1 },
|
|
{ "MACSEG2_CGEN", 5, 1 },
|
|
{ "PCSSEG2_CGEN", 4, 1 },
|
|
{ "MACSEG1_CGEN", 3, 1 },
|
|
{ "PCSSEG1_CGEN", 2, 1 },
|
|
{ "MACSEG0_CGEN", 1, 1 },
|
|
{ "PCSSEG0_CGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_TS_ID", 0x34924, 0 },
|
|
{ "MAC_PORT_TX_TS_VAL_LO", 0x34928, 0 },
|
|
{ "MAC_PORT_TX_TS_VAL_HI", 0x3492c, 0 },
|
|
{ "MAC_PORT_EEE_CTL", 0x34930, 0 },
|
|
{ "EEE_CTRL", 2, 30 },
|
|
{ "TICK_START", 1, 1 },
|
|
{ "En", 0, 1 },
|
|
{ "MAC_PORT_EEE_TX_CTL", 0x34934, 0 },
|
|
{ "WAKE_TIMER", 16, 16 },
|
|
{ "HSS_TIMER", 5, 4 },
|
|
{ "HSS_CTL", 4, 1 },
|
|
{ "LPI_ACTIVE", 3, 1 },
|
|
{ "LPI_TXHOLD", 2, 1 },
|
|
{ "LPI_REQ", 1, 1 },
|
|
{ "EEE_TX_RESET", 0, 1 },
|
|
{ "MAC_PORT_EEE_RX_CTL", 0x34938, 0 },
|
|
{ "WAKE_TIMER", 16, 16 },
|
|
{ "HSS_TIMER", 5, 4 },
|
|
{ "HSS_CTL", 4, 1 },
|
|
{ "LPI_IND", 1, 1 },
|
|
{ "EEE_RX_RESET", 0, 1 },
|
|
{ "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x3493c, 0 },
|
|
{ "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x34940, 0 },
|
|
{ "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x34944, 0 },
|
|
{ "MAC_PORT_EEE_TX_1G_SLEEP_TIMER", 0x34948, 0 },
|
|
{ "MAC_PORT_EEE_TX_1G_QUIET_TIMER", 0x3494c, 0 },
|
|
{ "MAC_PORT_EEE_TX_1G_REFRESH_TIMER", 0x34950, 0 },
|
|
{ "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x34954, 0 },
|
|
{ "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x34958, 0 },
|
|
{ "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x3495c, 0 },
|
|
{ "MAC_PORT_EEE_RX_1G_QUIET_TIMER", 0x34960, 0 },
|
|
{ "MAC_PORT_EEE_RX_1G_WAKE_TIMER", 0x34964, 0 },
|
|
{ "MAC_PORT_EEE_WF_COUNT", 0x34968, 0 },
|
|
{ "wake_cnt_clr", 16, 1 },
|
|
{ "wake_cnt", 0, 16 },
|
|
{ "MAC_PORT_PTP_TIMER_RD0_LO", 0x3496c, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_RD0_HI", 0x34970, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_RD1_LO", 0x34974, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_RD1_HI", 0x34978, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_WR_LO", 0x3497c, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_WR_HI", 0x34980, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_OFFSET_0", 0x34984, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_OFFSET_1", 0x34988, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_OFFSET_2", 0x3498c, 0 },
|
|
{ "MAC_PORT_PTP_SUM_LO", 0x34990, 0 },
|
|
{ "MAC_PORT_PTP_SUM_HI", 0x34994, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_INCR0", 0x34998, 0 },
|
|
{ "Y", 16, 16 },
|
|
{ "X", 0, 16 },
|
|
{ "MAC_PORT_PTP_TIMER_INCR1", 0x3499c, 0 },
|
|
{ "Y_TICK", 16, 16 },
|
|
{ "X_TICK", 0, 16 },
|
|
{ "MAC_PORT_PTP_DRIFT_ADJUST_COUNT", 0x349a0, 0 },
|
|
{ "MAC_PORT_PTP_OFFSET_ADJUST_FINE", 0x349a4, 0 },
|
|
{ "B", 16, 16 },
|
|
{ "A", 0, 16 },
|
|
{ "MAC_PORT_PTP_OFFSET_ADJUST_TOTAL", 0x349a8, 0 },
|
|
{ "MAC_PORT_PTP_CFG", 0x349ac, 0 },
|
|
{ "FRZ", 18, 1 },
|
|
{ "OFFSER_ADJUST_SIGN", 17, 1 },
|
|
{ "ADD_OFFSET", 16, 1 },
|
|
{ "CYCLE1", 8, 8 },
|
|
{ "Q", 0, 8 },
|
|
{ "MAC_PORT_MTIP_REVISION", 0x34a00, 0 },
|
|
{ "CUSTREV", 16, 16 },
|
|
{ "VER", 8, 8 },
|
|
{ "REV", 0, 8 },
|
|
{ "MAC_PORT_MTIP_SCRATCH", 0x34a04, 0 },
|
|
{ "MAC_PORT_MTIP_COMMAND_CONFIG", 0x34a08, 0 },
|
|
{ "TX_FLUSH", 22, 1 },
|
|
{ "RX_SFD_ANY", 21, 1 },
|
|
{ "PAUSE_PFC_COMP", 20, 1 },
|
|
{ "PFC_MODE", 19, 1 },
|
|
{ "RS_COL_CNT_EXT", 18, 1 },
|
|
{ "NO_LGTH_CHECK", 17, 1 },
|
|
{ "SEND_IDLE", 16, 1 },
|
|
{ "PHY_TXENA", 15, 1 },
|
|
{ "RX_ERR_DISC", 14, 1 },
|
|
{ "CMD_FRAME_ENA", 13, 1 },
|
|
{ "SW_RESET", 12, 1 },
|
|
{ "TX_PAD_EN", 11, 1 },
|
|
{ "LOOPBACK_EN", 10, 1 },
|
|
{ "TX_ADDR_INS", 9, 1 },
|
|
{ "PAUSE_IGNORE", 8, 1 },
|
|
{ "PAUSE_FWD", 7, 1 },
|
|
{ "CRC_FWD", 6, 1 },
|
|
{ "PAD_EN", 5, 1 },
|
|
{ "PROMIS_EN", 4, 1 },
|
|
{ "WAN_MODE", 3, 1 },
|
|
{ "RX_ENA", 1, 1 },
|
|
{ "TX_ENA", 0, 1 },
|
|
{ "MAC_PORT_MTIP_MAC_ADDR_0", 0x34a0c, 0 },
|
|
{ "MAC_PORT_MTIP_MAC_ADDR_1", 0x34a10, 0 },
|
|
{ "MAC_PORT_MTIP_FRM_LENGTH", 0x34a14, 0 },
|
|
{ "MAC_PORT_MTIP_RX_FIFO_SECTIONS", 0x34a1c, 0 },
|
|
{ "AVAIL", 16, 16 },
|
|
{ "EMPTY", 0, 16 },
|
|
{ "MAC_PORT_MTIP_TX_FIFO_SECTIONS", 0x34a20, 0 },
|
|
{ "AVAIL", 16, 16 },
|
|
{ "EMPTY", 0, 16 },
|
|
{ "MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E", 0x34a24, 0 },
|
|
{ "AlmstFull", 16, 16 },
|
|
{ "AlmstEmpty", 0, 16 },
|
|
{ "MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E", 0x34a28, 0 },
|
|
{ "AlmstFull", 16, 16 },
|
|
{ "AlmstEmpty", 0, 16 },
|
|
{ "MAC_PORT_MTIP_HASHTABLE_LOAD", 0x34a2c, 0 },
|
|
{ "ENABLE", 8, 1 },
|
|
{ "ADDR", 0, 6 },
|
|
{ "MAC_PORT_MTIP_MAC_STATUS", 0x34a40, 0 },
|
|
{ "TS_AVAIL", 3, 1 },
|
|
{ "PHY_LOS", 2, 1 },
|
|
{ "RX_REM_FAULT", 1, 1 },
|
|
{ "RX_LOC_FAULT", 0, 1 },
|
|
{ "MAC_PORT_MTIP_TX_IPG_LENGTH", 0x34a44, 0 },
|
|
{ "MAC_PORT_MTIP_MAC_CREDIT_TRIGGER", 0x34a48, 0 },
|
|
{ "MAC_PORT_MTIP_INIT_CREDIT", 0x34a4c, 0 },
|
|
{ "MAC_PORT_MTIP_CURRENT_CREDIT", 0x34a50, 0 },
|
|
{ "MAC_PORT_RX_PAUSE_STATUS", 0x34a74, 0 },
|
|
{ "MAC_PORT_MTIP_TS_TIMESTAMP", 0x34a7c, 0 },
|
|
{ "MAC_PORT_AFRAMESTRANSMITTEDOK", 0x34a80, 0 },
|
|
{ "MAC_PORT_AFRAMESTRANSMITTEDOKHI", 0x34a84, 0 },
|
|
{ "MAC_PORT_AFRAMESRECEIVEDOK", 0x34a88, 0 },
|
|
{ "MAC_PORT_AFRAMESRECEIVEDOKHI", 0x34a8c, 0 },
|
|
{ "MAC_PORT_AFRAMECHECKSEQUENCEERRORS", 0x34a90, 0 },
|
|
{ "MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI", 0x34a94, 0 },
|
|
{ "MAC_PORT_AALIGNMENTERRORS", 0x34a98, 0 },
|
|
{ "MAC_PORT_AALIGNMENTERRORSHI", 0x34a9c, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED", 0x34aa0, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI", 0x34aa4, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED", 0x34aa8, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI", 0x34aac, 0 },
|
|
{ "MAC_PORT_AFRAMETOOLONGERRORS", 0x34ab0, 0 },
|
|
{ "MAC_PORT_AFRAMETOOLONGERRORSHI", 0x34ab4, 0 },
|
|
{ "MAC_PORT_AINRANGELENGTHERRORS", 0x34ab8, 0 },
|
|
{ "MAC_PORT_AINRANGELENGTHERRORSHI", 0x34abc, 0 },
|
|
{ "MAC_PORT_VLANTRANSMITTEDOK", 0x34ac0, 0 },
|
|
{ "MAC_PORT_VLANTRANSMITTEDOKHI", 0x34ac4, 0 },
|
|
{ "MAC_PORT_VLANRECEIVEDOK", 0x34ac8, 0 },
|
|
{ "MAC_PORT_VLANRECEIVEDOKHI", 0x34acc, 0 },
|
|
{ "MAC_PORT_AOCTETSTRANSMITTEDOK", 0x34ad0, 0 },
|
|
{ "MAC_PORT_AOCTETSTRANSMITTEDOKHI", 0x34ad4, 0 },
|
|
{ "MAC_PORT_AOCTETSRECEIVEDOK", 0x34ad8, 0 },
|
|
{ "MAC_PORT_AOCTETSRECEIVEDOKHI", 0x34adc, 0 },
|
|
{ "MAC_PORT_IFINUCASTPKTS", 0x34ae0, 0 },
|
|
{ "MAC_PORT_IFINUCASTPKTSHI", 0x34ae4, 0 },
|
|
{ "MAC_PORT_IFINMULTICASTPKTS", 0x34ae8, 0 },
|
|
{ "MAC_PORT_IFINMULTICASTPKTSHI", 0x34aec, 0 },
|
|
{ "MAC_PORT_IFINBROADCASTPKTS", 0x34af0, 0 },
|
|
{ "MAC_PORT_IFINBROADCASTPKTSHI", 0x34af4, 0 },
|
|
{ "MAC_PORT_IFOUTERRORS", 0x34af8, 0 },
|
|
{ "MAC_PORT_IFOUTERRORSHI", 0x34afc, 0 },
|
|
{ "MAC_PORT_IFOUTUCASTPKTS", 0x34b08, 0 },
|
|
{ "MAC_PORT_IFOUTUCASTPKTSHI", 0x34b0c, 0 },
|
|
{ "MAC_PORT_IFOUTMULTICASTPKTS", 0x34b10, 0 },
|
|
{ "MAC_PORT_IFOUTMULTICASTPKTSHI", 0x34b14, 0 },
|
|
{ "MAC_PORT_IFOUTBROADCASTPKTS", 0x34b18, 0 },
|
|
{ "MAC_PORT_IFOUTBROADCASTPKTSHI", 0x34b1c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSDROPEVENTS", 0x34b20, 0 },
|
|
{ "MAC_PORT_ETHERSTATSDROPEVENTSHI", 0x34b24, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOCTETS", 0x34b28, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOCTETSHI", 0x34b2c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS", 0x34b30, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTSHI", 0x34b34, 0 },
|
|
{ "MAC_PORT_ETHERSTATSUNDERSIZEPKTS", 0x34b38, 0 },
|
|
{ "MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI", 0x34b3c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS64OCTETS", 0x34b40, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS64OCTETSHI", 0x34b44, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS65TO127OCTETS", 0x34b48, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI", 0x34b4c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS128TO255OCTETS", 0x34b50, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI", 0x34b54, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS256TO511OCTETS", 0x34b58, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI", 0x34b5c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS", 0x34b60, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI", 0x34b64, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS", 0x34b68, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x34b6c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS", 0x34b70, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI", 0x34b74, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOVERSIZEPKTS", 0x34b78, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOVERSIZEPKTSHI", 0x34b7c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSJABBERS", 0x34b80, 0 },
|
|
{ "MAC_PORT_ETHERSTATSJABBERSHI", 0x34b84, 0 },
|
|
{ "MAC_PORT_ETHERSTATSFRAGMENTS", 0x34b88, 0 },
|
|
{ "MAC_PORT_ETHERSTATSFRAGMENTSHI", 0x34b8c, 0 },
|
|
{ "MAC_PORT_IFINERRORS", 0x34b90, 0 },
|
|
{ "MAC_PORT_IFINERRORSHI", 0x34b94, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0", 0x34b98, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI", 0x34b9c, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1", 0x34ba0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI", 0x34ba4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2", 0x34ba8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI", 0x34bac, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3", 0x34bb0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI", 0x34bb4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4", 0x34bb8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI", 0x34bbc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5", 0x34bc0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI", 0x34bc4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6", 0x34bc8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI", 0x34bcc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7", 0x34bd0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI", 0x34bd4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0", 0x34bd8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI", 0x34bdc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1", 0x34be0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI", 0x34be4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2", 0x34be8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI", 0x34bec, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3", 0x34bf0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI", 0x34bf4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4", 0x34bf8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI", 0x34bfc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5", 0x34c00, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI", 0x34c04, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6", 0x34c08, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI", 0x34c0c, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7", 0x34c10, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI", 0x34c14, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESTRANSMITTED", 0x34c18, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI", 0x34c1c, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESRECEIVED", 0x34c20, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI", 0x34c24, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_CONTROL", 0x34d00, 0 },
|
|
{ "Reset", 15, 1 },
|
|
{ "Loopback", 14, 1 },
|
|
{ "sppedsel1", 13, 1 },
|
|
{ "AN_EN", 12, 1 },
|
|
{ "PWRDWN", 11, 1 },
|
|
{ "Isolate", 10, 1 },
|
|
{ "AN_RESTART", 9, 1 },
|
|
{ "DPLX", 8, 1 },
|
|
{ "CollisionTest", 7, 1 },
|
|
{ "SpeedSel0", 6, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_STATUS", 0x34d04, 0 },
|
|
{ "100BaseT4", 15, 1 },
|
|
{ "100BaseXFullDplx", 14, 1 },
|
|
{ "100BaseXHalfDplx", 13, 1 },
|
|
{ "10MbpsFullDplx", 12, 1 },
|
|
{ "10MbpsHalfDplx", 11, 1 },
|
|
{ "100BaseT2FullDplx", 10, 1 },
|
|
{ "100BaseT2HalfDplx", 9, 1 },
|
|
{ "ExtdStatus", 8, 1 },
|
|
{ "AN_Complete", 5, 1 },
|
|
{ "SGMII_REM_FAULT", 4, 1 },
|
|
{ "AN_Ability", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "JabberDetect", 1, 1 },
|
|
{ "ExtdCapability", 0, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0", 0x34d08, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1", 0x34d0c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_DEV_ABILITY", 0x34d10, 0 },
|
|
{ "NP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "RF2", 13, 1 },
|
|
{ "RF1", 12, 1 },
|
|
{ "PS2", 8, 1 },
|
|
{ "PS1", 7, 1 },
|
|
{ "HD", 6, 1 },
|
|
{ "FD", 5, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_PARTNER_ABILITY", 0x34d14, 0 },
|
|
{ "CuLinkStatus", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "CuDplxStatus", 12, 1 },
|
|
{ "CuSpeed", 10, 2 },
|
|
{ "MAC_PORT_MTIP_SGMII_AN_EXPANSION", 0x34d18, 0 },
|
|
{ "PgRcvd", 1, 1 },
|
|
{ "RealTimePgRcvd", 0, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_DEVICE_NP", 0x34d1c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_PARTNER_NP", 0x34d20, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_EXTENDED_STATUS", 0x34d3c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_LINK_TIMER_LO", 0x34d48, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_LINK_TIMER_HI", 0x34d4c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_IF_MODE", 0x34d50, 0 },
|
|
{ "SGMII_PCS_ENABLE", 5, 1 },
|
|
{ "SGMII_HDUPLEX", 4, 1 },
|
|
{ "SGMII_SPEED", 2, 2 },
|
|
{ "USE_SGMII_AN", 1, 1 },
|
|
{ "SGMII_ENA", 0, 1 },
|
|
{ "MAC_PORT_MTIP_ACT_CTL_SEG", 0x35200, 0 },
|
|
{ "MAC_PORT_MTIP_MODE_CTL_SEG", 0x35204, 0 },
|
|
{ "MAC_PORT_MTIP_TXCLK_CTL_SEG", 0x35208, 0 },
|
|
{ "MAC_PORT_MTIP_TX_PRMBL_CTL_SEG", 0x3520c, 0 },
|
|
{ "MAC_PORT_MTIP_WAN_RS_COL_CNT", 0x35220, 0 },
|
|
{ "MAC_PORT_MTIP_VL_INTVL", 0x35240, 0 },
|
|
{ "VL_INTVL", 1, 1 },
|
|
{ "MAC_PORT_MTIP_MDIO_CFG_STATUS", 0x35600, 0 },
|
|
{ "CLK_DIV", 7, 9 },
|
|
{ "CL45_EN", 6, 1 },
|
|
{ "disable_preamble", 5, 1 },
|
|
{ "mdio_hold_time", 2, 3 },
|
|
{ "mdio_read_err", 1, 1 },
|
|
{ "mdio_busy", 0, 1 },
|
|
{ "MAC_PORT_MTIP_MDIO_COMMAND", 0x35604, 0 },
|
|
{ "read", 15, 1 },
|
|
{ "read_incr", 14, 1 },
|
|
{ "port_addr", 5, 5 },
|
|
{ "dev_addr", 0, 5 },
|
|
{ "MAC_PORT_MTIP_MDIO_DATA", 0x35608, 0 },
|
|
{ "readbusy", 31, 1 },
|
|
{ "data_word", 0, 16 },
|
|
{ "MAC_PORT_MTIP_MDIO_REGADDR", 0x3560c, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_0", 0x35a00, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_1", 0x35a04, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_2", 0x35a08, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_3", 0x35a0c, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_4", 0x35a10, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_5", 0x35a14, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_6", 0x35a18, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_7", 0x35a1c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_CTL", 0x35e00, 0 },
|
|
{ "RESET", 15, 1 },
|
|
{ "LPBK", 14, 1 },
|
|
{ "SPEED_SEL1", 13, 1 },
|
|
{ "LP_MODE", 11, 1 },
|
|
{ "SPEED_SEL0", 6, 1 },
|
|
{ "SPEED", 2, 4 },
|
|
{ "MAC_PORT_MTIP_PCS_STATUS1", 0x35e04, 0 },
|
|
{ "FaultDet", 7, 1 },
|
|
{ "rx_link_status", 2, 1 },
|
|
{ "LoPwrAbl", 1, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_DEVICE_ID0", 0x35e08, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_DEVICE_ID1", 0x35e0c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_SPEED_ABILITY", 0x35e10, 0 },
|
|
{ "100G", 8, 1 },
|
|
{ "40G", 7, 1 },
|
|
{ "10BASE_TL", 1, 1 },
|
|
{ "10G", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_DEVICE_PKG1", 0x35e14, 0 },
|
|
{ "TC", 6, 1 },
|
|
{ "DTEXS", 5, 1 },
|
|
{ "PHYXS", 4, 1 },
|
|
{ "PCS", 3, 1 },
|
|
{ "WIS", 2, 1 },
|
|
{ "PMD_PMA", 1, 1 },
|
|
{ "CL22", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_DEVICE_PKG2", 0x35e18, 0 },
|
|
{ "VendDev2", 15, 1 },
|
|
{ "VendDev1", 14, 1 },
|
|
{ "CL22EXT", 13, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_CTL2", 0x35e1c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_STATUS2", 0x35e20, 0 },
|
|
{ "Device", 15, 1 },
|
|
{ "TxFault", 7, 1 },
|
|
{ "RxFault", 6, 1 },
|
|
{ "100BASE_R", 5, 1 },
|
|
{ "40GBASE_R", 4, 1 },
|
|
{ "10GBASE_T", 3, 1 },
|
|
{ "10GBASE_W", 2, 1 },
|
|
{ "10GBASE_X", 1, 1 },
|
|
{ "10GBASE_R", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_PKG_ID0", 0x35e38, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_PKG_ID1", 0x35e3c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BASER_STATUS1", 0x35e80, 0 },
|
|
{ "RxLinkStatus", 12, 1 },
|
|
{ "RESEREVED", 4, 8 },
|
|
{ "10GPRBS9", 3, 1 },
|
|
{ "10GPRBS31", 2, 1 },
|
|
{ "HiBER", 1, 1 },
|
|
{ "blocklock", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_BASER_STATUS2", 0x35e84, 0 },
|
|
{ "blocklockLL", 15, 1 },
|
|
{ "HiBERLH", 14, 1 },
|
|
{ "HiBERCount", 8, 6 },
|
|
{ "ErrBlkCnt", 0, 8 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_A", 0x35e88, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_A1", 0x35e8c, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_A2", 0x35e90, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_A3", 0x35e94, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_B", 0x35e98, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_B1", 0x35e9c, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_B2", 0x35ea0, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_B3", 0x35ea4, 0 },
|
|
{ "MAC_PORT_MTIP_BASER_TEST_CTRL", 0x35ea8, 0 },
|
|
{ "TXPRBS9", 6, 1 },
|
|
{ "RXPRBS31", 5, 1 },
|
|
{ "TXPRBS31", 4, 1 },
|
|
{ "TxTestPatEn", 3, 1 },
|
|
{ "RxTestPatEn", 2, 1 },
|
|
{ "TestPatSel", 1, 1 },
|
|
{ "DataPatSel", 0, 1 },
|
|
{ "MAC_PORT_MTIP_BASER_TEST_ERR_CNT", 0x35eac, 0 },
|
|
{ "MAC_PORT_MTIP_BER_HIGH_ORDER_CNT", 0x35eb0, 0 },
|
|
{ "MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT", 0x35eb4, 0 },
|
|
{ "HiCountPrsnt", 15, 1 },
|
|
{ "BLOCK_CNT_HI", 0, 14 },
|
|
{ "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1", 0x35ec8, 0 },
|
|
{ "alignstatus", 12, 1 },
|
|
{ "Lane7", 7, 1 },
|
|
{ "Lane6", 6, 1 },
|
|
{ "Lane5", 5, 1 },
|
|
{ "Lane4", 4, 1 },
|
|
{ "Lane3", 3, 1 },
|
|
{ "Lane2", 2, 1 },
|
|
{ "Lane1", 1, 1 },
|
|
{ "Lane0", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2", 0x35ecc, 0 },
|
|
{ "Lane19", 11, 1 },
|
|
{ "Lane18", 10, 1 },
|
|
{ "Lane17", 9, 1 },
|
|
{ "Lane16", 8, 1 },
|
|
{ "Lane15", 7, 1 },
|
|
{ "Lane14", 6, 1 },
|
|
{ "Lane13", 5, 1 },
|
|
{ "Lane12", 4, 1 },
|
|
{ "Lane11", 3, 1 },
|
|
{ "Lane10", 2, 1 },
|
|
{ "Lane9", 1, 1 },
|
|
{ "Lane8", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3", 0x35ed0, 0 },
|
|
{ "AMLOCK7", 7, 1 },
|
|
{ "AMLOCK6", 6, 1 },
|
|
{ "AMLOCK5", 5, 1 },
|
|
{ "AMLOCK4", 4, 1 },
|
|
{ "AMLOCK3", 3, 1 },
|
|
{ "AMLOCK2", 2, 1 },
|
|
{ "AMLOCK1", 1, 1 },
|
|
{ "AMLOCK0", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4", 0x35ed4, 0 },
|
|
{ "AMLOCK19", 11, 1 },
|
|
{ "AMLOCK18", 10, 1 },
|
|
{ "AMLOCK17", 9, 1 },
|
|
{ "AMLOCK16", 8, 1 },
|
|
{ "AMLOCK15", 7, 1 },
|
|
{ "AMLOCK14", 6, 1 },
|
|
{ "AMLOCK13", 5, 1 },
|
|
{ "AMLOCK12", 4, 1 },
|
|
{ "AMLOCK11", 3, 1 },
|
|
{ "AMLOCK10", 2, 1 },
|
|
{ "AMLOCK9", 1, 1 },
|
|
{ "AMLOCK8", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0", 0x35f68, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1", 0x35f6c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2", 0x35f70, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3", 0x35f74, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4", 0x35f78, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5", 0x35f7c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6", 0x35f80, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7", 0x35f84, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8", 0x35f88, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9", 0x35f8c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10", 0x35f90, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11", 0x35f94, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12", 0x35f98, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13", 0x35f9c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14", 0x35fa0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15", 0x35fa4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16", 0x35fa8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17", 0x35fac, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18", 0x35fb0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19", 0x35fb4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_0", 0x35fb8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_1", 0x35fbc, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_2", 0x35fc0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_3", 0x35fc4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_4", 0x35fc8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_5", 0x35fcc, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_6", 0x35fd0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_7", 0x35fd4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_8", 0x35fd8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_9", 0x35fdc, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_10", 0x35fe0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_11", 0x35fe4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_12", 0x35fe8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_13", 0x35fec, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_14", 0x35ff0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_15", 0x35ff4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_16", 0x35ff8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_17", 0x35ffc, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_18", 0x36000, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_19", 0x36004, 0 },
|
|
{ "MAC_PORT_BEAN_CTL", 0x36200, 0 },
|
|
{ "AN_RESET", 15, 1 },
|
|
{ "EXT_NXP_CTRL", 13, 1 },
|
|
{ "BEAN_EN", 12, 1 },
|
|
{ "RESTART_BEAN", 9, 1 },
|
|
{ "MAC_PORT_BEAN_STATUS", 0x36204, 0 },
|
|
{ "PDF", 9, 1 },
|
|
{ "EXT_NXP_STATUS", 7, 1 },
|
|
{ "PAGE_RCVD", 6, 1 },
|
|
{ "BEAN_COMPLETE", 5, 1 },
|
|
{ "REM_FAULT_STATUS", 4, 1 },
|
|
{ "BEAN_ABILITY", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "LP_BEAN_ABILITY", 0, 1 },
|
|
{ "MAC_PORT_BEAN_ABILITY_0", 0x36208, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_1", 0x3620c, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_2", 0x36210, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_0", 0x36214, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_1", 0x36218, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_2", 0x3621c, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_MS_COUNT", 0x36220, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_0", 0x36224, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_BEAN_XNP_1", 0x36228, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_2", 0x3622c, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_0", 0x36230, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_1", 0x36234, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_2", 0x36238, 0 },
|
|
{ "MAC_PORT_BEAN_ETH_STATUS", 0x3623c, 0 },
|
|
{ "100GCR10", 8, 1 },
|
|
{ "40GCR4", 6, 1 },
|
|
{ "40GKR4", 5, 1 },
|
|
{ "FEC", 4, 1 },
|
|
{ "10GKR", 3, 1 },
|
|
{ "10GKX4", 2, 1 },
|
|
{ "1GKX", 1, 1 },
|
|
{ "MAC_PORT_BEAN_CTL_LANE1", 0x36240, 0 },
|
|
{ "AN_RESET", 15, 1 },
|
|
{ "EXT_NXP_CTRL", 13, 1 },
|
|
{ "BEAN_EN", 12, 1 },
|
|
{ "RESTART_BEAN", 9, 1 },
|
|
{ "MAC_PORT_BEAN_STATUS_LANE1", 0x36244, 0 },
|
|
{ "PDF", 9, 1 },
|
|
{ "EXT_NXP_STATUS", 7, 1 },
|
|
{ "PAGE_RCVD", 6, 1 },
|
|
{ "BEAN_COMPLETE", 5, 1 },
|
|
{ "REM_FAULT_STATUS", 4, 1 },
|
|
{ "BEAN_ABILITY", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "LP_BEAN_ABILITY", 0, 1 },
|
|
{ "MAC_PORT_BEAN_ABILITY_0_LANE1", 0x36248, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_1_LANE1", 0x3624c, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_2_LANE1", 0x36250, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_0_LANE1", 0x36254, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_1_LANE1", 0x36258, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_2_LANE1", 0x3625c, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_MS_COUNT_LANE1", 0x36260, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_0_LANE1", 0x36264, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_BEAN_XNP_1_LANE1", 0x36268, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_2_LANE1", 0x3626c, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_0_LANE1", 0x36270, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_1_LANE1", 0x36274, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_2_LANE1", 0x36278, 0 },
|
|
{ "MAC_PORT_BEAN_ETH_STATUS_LANE1", 0x3627c, 0 },
|
|
{ "100GCR10", 8, 1 },
|
|
{ "40GCR4", 6, 1 },
|
|
{ "40GKR4", 5, 1 },
|
|
{ "FEC", 4, 1 },
|
|
{ "10GKR", 3, 1 },
|
|
{ "10GKX4", 2, 1 },
|
|
{ "1GKX", 1, 1 },
|
|
{ "MAC_PORT_BEAN_CTL_LANE2", 0x36280, 0 },
|
|
{ "AN_RESET", 15, 1 },
|
|
{ "EXT_NXP_CTRL", 13, 1 },
|
|
{ "BEAN_EN", 12, 1 },
|
|
{ "RESTART_BEAN", 9, 1 },
|
|
{ "MAC_PORT_BEAN_STATUS_LANE2", 0x36284, 0 },
|
|
{ "PDF", 9, 1 },
|
|
{ "EXT_NXP_STATUS", 7, 1 },
|
|
{ "PAGE_RCVD", 6, 1 },
|
|
{ "BEAN_COMPLETE", 5, 1 },
|
|
{ "REM_FAULT_STATUS", 4, 1 },
|
|
{ "BEAN_ABILITY", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "LP_BEAN_ABILITY", 0, 1 },
|
|
{ "MAC_PORT_BEAN_ABILITY_0_LANE2", 0x36288, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_1_LANE2", 0x3628c, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_2_LANE2", 0x36290, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_0_LANE2", 0x36294, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_1_LANE2", 0x36298, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_2_LANE2", 0x3629c, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_MS_COUNT_LANE2", 0x362a0, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_0_LANE2", 0x362a4, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_BEAN_XNP_1_LANE2", 0x362a8, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_2_LANE2", 0x362ac, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_0_LANE2", 0x362b0, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_1_LANE2", 0x362b4, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_2_LANE2", 0x362b8, 0 },
|
|
{ "MAC_PORT_BEAN_ETH_STATUS_LANE2", 0x362bc, 0 },
|
|
{ "100GCR10", 8, 1 },
|
|
{ "40GCR4", 6, 1 },
|
|
{ "40GKR4", 5, 1 },
|
|
{ "FEC", 4, 1 },
|
|
{ "10GKR", 3, 1 },
|
|
{ "10GKX4", 2, 1 },
|
|
{ "1GKX", 1, 1 },
|
|
{ "MAC_PORT_BEAN_CTL_LANE3", 0x362c0, 0 },
|
|
{ "AN_RESET", 15, 1 },
|
|
{ "EXT_NXP_CTRL", 13, 1 },
|
|
{ "BEAN_EN", 12, 1 },
|
|
{ "RESTART_BEAN", 9, 1 },
|
|
{ "MAC_PORT_BEAN_STATUS_LANE3", 0x362c4, 0 },
|
|
{ "PDF", 9, 1 },
|
|
{ "EXT_NXP_STATUS", 7, 1 },
|
|
{ "PAGE_RCVD", 6, 1 },
|
|
{ "BEAN_COMPLETE", 5, 1 },
|
|
{ "REM_FAULT_STATUS", 4, 1 },
|
|
{ "BEAN_ABILITY", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "LP_BEAN_ABILITY", 0, 1 },
|
|
{ "MAC_PORT_BEAN_ABILITY_0_LANE3", 0x362c8, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_1_LANE3", 0x362cc, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_2_LANE3", 0x362d0, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_0_LANE3", 0x362d4, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_1_LANE3", 0x362d8, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_2_LANE3", 0x362dc, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_MS_COUNT_LANE3", 0x362e0, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_0_LANE3", 0x362e4, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_BEAN_XNP_1_LANE3", 0x362e8, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_2_LANE3", 0x362ec, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_0_LANE3", 0x362f0, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_1_LANE3", 0x362f4, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_2_LANE3", 0x362f8, 0 },
|
|
{ "MAC_PORT_BEAN_ETH_STATUS_LANE3", 0x362fc, 0 },
|
|
{ "100GCR10", 8, 1 },
|
|
{ "40GCR4", 6, 1 },
|
|
{ "40GKR4", 5, 1 },
|
|
{ "FEC", 4, 1 },
|
|
{ "10GKR", 3, 1 },
|
|
{ "10GKX4", 2, 1 },
|
|
{ "1GKX", 1, 1 },
|
|
{ "MAC_PORT_FEC_KR_CONTROL", 0x36600, 0 },
|
|
{ "enable_tr", 1, 1 },
|
|
{ "restart_tr", 0, 1 },
|
|
{ "MAC_PORT_FEC_KR_STATUS", 0x36604, 0 },
|
|
{ "fecKRsigdet", 15, 1 },
|
|
{ "train_fail", 3, 1 },
|
|
{ "startup_status", 2, 1 },
|
|
{ "frame_lock", 1, 1 },
|
|
{ "rx_status", 0, 1 },
|
|
{ "MAC_PORT_FEC_KR_LP_COEFF", 0x36608, 0 },
|
|
{ "Preset", 13, 1 },
|
|
{ "Initialize", 12, 1 },
|
|
{ "CP1_UPD", 4, 2 },
|
|
{ "C0_UPD", 2, 2 },
|
|
{ "CN1_UPD", 0, 2 },
|
|
{ "MAC_PORT_FEC_KR_LP_STAT", 0x3660c, 0 },
|
|
{ "rx_ready", 15, 1 },
|
|
{ "CP1_STAT", 4, 2 },
|
|
{ "C0_STAT", 2, 2 },
|
|
{ "CN1_STAT", 0, 2 },
|
|
{ "MAC_PORT_FEC_KR_LD_COEFF", 0x36610, 0 },
|
|
{ "Preset", 13, 1 },
|
|
{ "Initialize", 12, 1 },
|
|
{ "CP1_UPD", 4, 2 },
|
|
{ "C0_UPD", 2, 2 },
|
|
{ "CN1_UPD", 0, 2 },
|
|
{ "MAC_PORT_FEC_KR_LD_STAT", 0x36614, 0 },
|
|
{ "rx_ready", 15, 1 },
|
|
{ "CP1_STAT", 4, 2 },
|
|
{ "C0_STAT", 2, 2 },
|
|
{ "CN1_STAT", 0, 2 },
|
|
{ "MAC_PORT_FEC_ABILITY", 0x36618, 0 },
|
|
{ "fec_ind_ability", 1, 1 },
|
|
{ "ability", 0, 1 },
|
|
{ "MAC_PORT_FEC_CONTROL", 0x3661c, 0 },
|
|
{ "fec_en_err_ind", 1, 1 },
|
|
{ "fec_en", 0, 1 },
|
|
{ "MAC_PORT_FEC_STATUS", 0x36620, 0 },
|
|
{ "FEC_LOCKED_100", 1, 1 },
|
|
{ "FEC_LOCKED", 0, 1 },
|
|
{ "MAC_PORT_FEC_CERR_CNT_0", 0x36624, 0 },
|
|
{ "MAC_PORT_FEC_CERR_CNT_1", 0x36628, 0 },
|
|
{ "MAC_PORT_FEC_NCERR_CNT_0", 0x3662c, 0 },
|
|
{ "MAC_PORT_FEC_NCERR_CNT_1", 0x36630, 0 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ", 0x36a00, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT", 0x36a04, 0 },
|
|
{ "T5_AE0_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE0_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE0_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE0_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ", 0x36a08, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT", 0x36a0c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE", 0x36a10, 0 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL", 0x36a14, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL", 0x36a18, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE", 0x36a1c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ_1", 0x36a20, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT_1", 0x36a24, 0 },
|
|
{ "T5_AE1_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE1_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE1_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE1_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ_1", 0x36a28, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT_1", 0x36a2c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE_1", 0x36a30, 0 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL_1", 0x36a34, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL_1", 0x36a38, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE_1", 0x36a3c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ_2", 0x36a40, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT_2", 0x36a44, 0 },
|
|
{ "T5_AE2_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE2_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE2_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE2_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ_2", 0x36a48, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT_2", 0x36a4c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE_2", 0x36a50, 0 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL_2", 0x36a54, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL_2", 0x36a58, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE_2", 0x36a5c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ_3", 0x36a60, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT_3", 0x36a64, 0 },
|
|
{ "T5_AE3_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE3_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE3_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE3_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ_3", 0x36a68, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT_3", 0x36a6c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE_3", 0x36a70, 0 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL_3", 0x36a74, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL_3", 0x36a78, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE_3", 0x36a7c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_TX_DIS", 0x36a80, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL", 0x36a84, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET", 0x36a88, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS", 0x36a8c, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AE_TX_DIS_1", 0x36a90, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL_1", 0x36a94, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET_1", 0x36a98, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS_1", 0x36a9c, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AE_TX_DIS_2", 0x36aa0, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL_2", 0x36aa4, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET_2", 0x36aa8, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS_2", 0x36aac, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AE_TX_DIS_3", 0x36ab0, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL_3", 0x36ab4, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET_3", 0x36ab8, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS_3", 0x36abc, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_0", 0x36b00, 0 },
|
|
{ "EN_HOLD_FAIL", 14, 1 },
|
|
{ "INIT_METH", 12, 2 },
|
|
{ "CE_DECS", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_C1", 5, 1 },
|
|
{ "EN_MAX_ST", 4, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0", 0x36b04, 0 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_0", 0x36b08, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0", 0x36b0c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT6", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_0", 0x36b10, 0 },
|
|
{ "AET_STAT", 9, 4 },
|
|
{ "NEU_STATE", 5, 4 },
|
|
{ "CTRL_STATE", 0, 5 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_1", 0x36b20, 0 },
|
|
{ "EN_HOLD_FAIL", 14, 1 },
|
|
{ "INIT_METH", 12, 2 },
|
|
{ "CE_DECS", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_C1", 5, 1 },
|
|
{ "EN_MAX_ST", 4, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1", 0x36b24, 0 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_1", 0x36b28, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1", 0x36b2c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT6", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_1", 0x36b30, 0 },
|
|
{ "AET_STAT", 9, 4 },
|
|
{ "NEU_STATE", 5, 4 },
|
|
{ "CTRL_STATE", 0, 5 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_2", 0x36b40, 0 },
|
|
{ "EN_HOLD_FAIL", 14, 1 },
|
|
{ "INIT_METH", 12, 2 },
|
|
{ "CE_DECS", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_C1", 5, 1 },
|
|
{ "EN_MAX_ST", 4, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2", 0x36b44, 0 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_2", 0x36b48, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2", 0x36b4c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT6", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_2", 0x36b50, 0 },
|
|
{ "AET_STAT", 9, 4 },
|
|
{ "NEU_STATE", 5, 4 },
|
|
{ "CTRL_STATE", 0, 5 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_3", 0x36b60, 0 },
|
|
{ "EN_HOLD_FAIL", 14, 1 },
|
|
{ "INIT_METH", 12, 2 },
|
|
{ "CE_DECS", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_C1", 5, 1 },
|
|
{ "EN_MAX_ST", 4, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3", 0x36b64, 0 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_3", 0x36b68, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3", 0x36b6c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT6", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_3", 0x36b70, 0 },
|
|
{ "AET_STAT", 9, 4 },
|
|
{ "NEU_STATE", 5, 4 },
|
|
{ "CTRL_STATE", 0, 5 },
|
|
{ "MAC_PORT_ANALOG_TEST_MUX", 0x37814, 0 },
|
|
{ "MAC_PORT_BANDGAP_CONTROL", 0x3782c, 0 },
|
|
{ "MAC_PORT_RESISTOR_CALIBRATION_CONTROL", 0x37880, 0 },
|
|
{ "RCCTL1", 5, 1 },
|
|
{ "RCCTL0", 4, 1 },
|
|
{ "RCAMP1", 3, 1 },
|
|
{ "RCAMP0", 2, 1 },
|
|
{ "RCAMPEN", 1, 1 },
|
|
{ "RCRST", 0, 1 },
|
|
{ "MAC_PORT_RESISTOR_CALIBRATION_STATUS_1", 0x37884, 0 },
|
|
{ "RCERR", 1, 1 },
|
|
{ "RCCOMP", 0, 1 },
|
|
{ "MAC_PORT_RESISTOR_CALIBRATION_STATUS_2", 0x37888, 0 },
|
|
{ "MAC_PORT_RESISTOR_CALIBRATION_STATUS_3", 0x3788c, 0 },
|
|
{ "MAC_PORT_MACRO_TEST_CONTROL_6", 0x378e8, 0 },
|
|
{ "LBIST", 7, 1 },
|
|
{ "LOGICTEST", 6, 1 },
|
|
{ "MAVDHI", 5, 1 },
|
|
{ "AUXEN", 4, 1 },
|
|
{ "JTAGMD", 3, 1 },
|
|
{ "RXACMODE", 2, 1 },
|
|
{ "HSSACJPC", 1, 1 },
|
|
{ "HSSACJAC", 0, 1 },
|
|
{ "MAC_PORT_MACRO_TEST_CONTROL_5", 0x378ec, 0 },
|
|
{ "REFVALIDD", 6, 1 },
|
|
{ "REFVALIDC", 5, 1 },
|
|
{ "REFVALIDB", 4, 1 },
|
|
{ "REFVALIDA", 3, 1 },
|
|
{ "REFSELRESET", 2, 1 },
|
|
{ "SOFTRESET", 1, 1 },
|
|
{ "MACROTEST", 0, 1 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0", 0x37b00, 0 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1", 0x37b04, 0 },
|
|
{ "LDET", 4, 1 },
|
|
{ "CCERR", 3, 1 },
|
|
{ "CCCMP", 2, 1 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2", 0x37b08, 0 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3", 0x37b0c, 0 },
|
|
{ "FMIN", 3, 1 },
|
|
{ "FMAX", 2, 1 },
|
|
{ "CVHOLD", 1, 1 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4", 0x37b10, 0 },
|
|
{ "CMETH", 2, 1 },
|
|
{ "RECAL", 1, 1 },
|
|
{ "CCLD", 0, 1 },
|
|
{ "MAC_PORT_PLLA_CHARGE_PUMP_CONTROL", 0x37b28, 0 },
|
|
{ "MAC_PORT_PLLA_PCLK_CONTROL", 0x37b3c, 0 },
|
|
{ "SPEDIV", 3, 5 },
|
|
{ "PCKSEL", 0, 3 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL", 0x37b40, 0 },
|
|
{ "EMIL", 2, 1 },
|
|
{ "EMID", 1, 1 },
|
|
{ "EMIS", 0, 1 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1", 0x37b44, 0 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2", 0x37b48, 0 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3", 0x37b4c, 0 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4", 0x37b50, 0 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_4", 0x37bf0, 0 },
|
|
{ "VBST", 1, 3 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_3", 0x37bf4, 0 },
|
|
{ "RESYNC", 6, 1 },
|
|
{ "RXCLKSEL", 5, 1 },
|
|
{ "FRCBAND", 4, 1 },
|
|
{ "PLLBYP", 3, 1 },
|
|
{ "PDWNP", 2, 1 },
|
|
{ "VCOSEL", 1, 1 },
|
|
{ "DIVSEL8", 0, 1 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_2", 0x37bf8, 0 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_1", 0x37bfc, 0 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0", 0x37c00, 0 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1", 0x37c04, 0 },
|
|
{ "LDET", 4, 1 },
|
|
{ "CCERR", 3, 1 },
|
|
{ "CCCMP", 2, 1 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2", 0x37c08, 0 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3", 0x37c0c, 0 },
|
|
{ "FMIN", 3, 1 },
|
|
{ "FMAX", 2, 1 },
|
|
{ "CVHOLD", 1, 1 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4", 0x37c10, 0 },
|
|
{ "CMETH", 2, 1 },
|
|
{ "RECAL", 1, 1 },
|
|
{ "CCLD", 0, 1 },
|
|
{ "MAC_PORT_PLLB_CHARGE_PUMP_CONTROL", 0x37c28, 0 },
|
|
{ "MAC_PORT_PLLB_PCLK_CONTROL", 0x37c3c, 0 },
|
|
{ "SPEDIV", 3, 5 },
|
|
{ "PCKSEL", 0, 3 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL", 0x37c40, 0 },
|
|
{ "EMIL", 2, 1 },
|
|
{ "EMID", 1, 1 },
|
|
{ "EMIS", 0, 1 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1", 0x37c44, 0 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2", 0x37c48, 0 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3", 0x37c4c, 0 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4", 0x37c50, 0 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_4", 0x37cf0, 0 },
|
|
{ "VBST", 1, 3 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_3", 0x37cf4, 0 },
|
|
{ "RESYNC", 6, 1 },
|
|
{ "RXCLKSEL", 5, 1 },
|
|
{ "FRCBAND", 4, 1 },
|
|
{ "PLLBYP", 3, 1 },
|
|
{ "PDWNP", 2, 1 },
|
|
{ "VCOSEL", 1, 1 },
|
|
{ "DIVSEL8", 0, 1 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_2", 0x37cf8, 0 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_1", 0x37cfc, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE", 0x37000, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL", 0x37004, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL", 0x37008, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL", 0x3700c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37010, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37014, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37018, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3701c, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT", 0x37020, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT", 0x37024, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT", 0x37028, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE", 0x37030, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_POLARITY", 0x37034, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37038, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3703c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x37040, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x37044, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x37048, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x37060, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x37064, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x37068, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x37070, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x37074, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37078, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3707c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37080, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37084, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x37088, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL", 0x3708c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE", 0x37090, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED", 0x37094, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT", 0x37098, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL", 0x3709c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4", 0x370f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3", 0x370f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2", 0x370f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1", 0x370fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x34000, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x34008, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x34010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x34018, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x34020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x34028, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x34030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x34038, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x34040, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE", 0x37100, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL", 0x37104, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL", 0x37108, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL", 0x3710c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37110, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37114, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37118, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3711c, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT", 0x37120, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT", 0x37124, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT", 0x37128, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE", 0x37130, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_POLARITY", 0x37134, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37138, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3713c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x37140, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x37144, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x37148, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x37160, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x37164, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x37168, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x37170, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x37174, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37178, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3717c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37180, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37184, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x37188, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL", 0x3718c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE", 0x37190, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED", 0x37194, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT", 0x37198, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL", 0x3719c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4", 0x371f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3", 0x371f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2", 0x371f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1", 0x371fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x34000, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x34008, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x34010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x34018, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x34020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x34028, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x34030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x34038, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x34040, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE", 0x37400, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL", 0x37404, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL", 0x37408, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL", 0x3740c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37410, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37414, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37418, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3741c, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT", 0x37420, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT", 0x37424, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT", 0x37428, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE", 0x37430, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_POLARITY", 0x37434, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37438, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3743c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x37440, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x37444, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x37448, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x37460, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x37464, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x37468, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x37470, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x37474, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37478, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3747c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37480, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37484, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x37488, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL", 0x3748c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE", 0x37490, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED", 0x37494, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT", 0x37498, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL", 0x3749c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4", 0x374f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3", 0x374f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2", 0x374f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1", 0x374fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x34000, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x34008, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x34010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x34018, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x34020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x34028, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x34030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x34038, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x34040, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE", 0x37500, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL", 0x37504, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL", 0x37508, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL", 0x3750c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37510, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37514, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37518, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3751c, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT", 0x37520, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT", 0x37524, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT", 0x37528, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE", 0x37530, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_POLARITY", 0x37534, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37538, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3753c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x37540, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x37544, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x37548, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x37560, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x37564, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x37568, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x37570, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x37574, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37578, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3757c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37580, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37584, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x37588, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL", 0x3758c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE", 0x37590, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED", 0x37594, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT", 0x37598, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL", 0x3759c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4", 0x375f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3", 0x375f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2", 0x375f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1", 0x375fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x34000, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x34008, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x34010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x34018, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x34020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x34028, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x34030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x34038, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x34040, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE", 0x37900, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL", 0x37904, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL", 0x37908, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL", 0x3790c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x37910, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x37914, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x37918, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3791c, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT", 0x37920, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT", 0x37924, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT", 0x37928, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE", 0x37930, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY", 0x37934, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x37938, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3793c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x37940, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x37944, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x37948, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x37960, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x37964, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x37968, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x37970, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x37974, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x37978, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3797c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x37980, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x37984, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x37988, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL", 0x3798c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE", 0x37990, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED", 0x37994, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT", 0x37998, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL", 0x3799c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4", 0x379f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3", 0x379f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2", 0x379f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1", 0x379fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x34000, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x34008, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x34010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x34018, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x34020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x34028, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x34030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x34038, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x34040, 0 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE", 0x37200, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL", 0x37204, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL", 0x37208, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL", 0x3720c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1", 0x37210, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2", 0x37214, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37218, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3721c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_CONTROL", 0x37220, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1", 0x37224, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2", 0x37228, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1", 0x3722c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2", 0x37230, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3", 0x37234, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1", 0x37238, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3", 0x37240, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN", 0x37248, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ", 0x3724c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL", 0x37250, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3725c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x37260, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x37264, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37270, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC", 0x37274, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS", 0x37278, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1", 0x3727c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2", 0x37280, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2", 0x37284, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2", 0x37288, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4", 0x3728c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4", 0x37290, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET", 0x37294, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL", 0x37298, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL", 0x3729c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH", 0x372a0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET", 0x372a4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL", 0x372a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS", 0x372ac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x372b0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x372b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x372b8, 0 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_TAP_ENABLE", 0x372c0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1", 0x372c4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H2", 0x372c8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H3", 0x372cc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H4", 0x372d0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H5", 0x372d4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H6_AND_H7", 0x372d8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H8_AND_H9", 0x372dc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H10_AND_H11", 0x372e0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H12", 0x372e4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2", 0x372f8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1", 0x372fc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE", 0x37300, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL", 0x37304, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL", 0x37308, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL", 0x3730c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1", 0x37310, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2", 0x37314, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37318, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3731c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_CONTROL", 0x37320, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1", 0x37324, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2", 0x37328, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1", 0x3732c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2", 0x37330, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3", 0x37334, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1", 0x37338, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3", 0x37340, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN", 0x37348, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ", 0x3734c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL", 0x37350, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3735c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x37360, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x37364, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37370, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC", 0x37374, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS", 0x37378, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1", 0x3737c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2", 0x37380, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2", 0x37384, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2", 0x37388, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4", 0x3738c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4", 0x37390, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET", 0x37394, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL", 0x37398, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL", 0x3739c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH", 0x373a0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET", 0x373a4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL", 0x373a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS", 0x373ac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x373b0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x373b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x373b8, 0 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_TAP_ENABLE", 0x373c0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1", 0x373c4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H2", 0x373c8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H3", 0x373cc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H4", 0x373d0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H5", 0x373d4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H6_AND_H7", 0x373d8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H8_AND_H9", 0x373dc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H10_AND_H11", 0x373e0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H12", 0x373e4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2", 0x373f8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1", 0x373fc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE", 0x37600, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL", 0x37604, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL", 0x37608, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL", 0x3760c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1", 0x37610, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2", 0x37614, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37618, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3761c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_CONTROL", 0x37620, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1", 0x37624, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2", 0x37628, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1", 0x3762c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2", 0x37630, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3", 0x37634, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1", 0x37638, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3", 0x37640, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN", 0x37648, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ", 0x3764c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL", 0x37650, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3765c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x37660, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x37664, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37670, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC", 0x37674, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS", 0x37678, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1", 0x3767c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2", 0x37680, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2", 0x37684, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2", 0x37688, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4", 0x3768c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4", 0x37690, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET", 0x37694, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL", 0x37698, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL", 0x3769c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH", 0x376a0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET", 0x376a4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL", 0x376a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS", 0x376ac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x376b0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x376b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x376b8, 0 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_TAP_ENABLE", 0x376c0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1", 0x376c4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H2", 0x376c8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H3", 0x376cc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H4", 0x376d0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H5", 0x376d4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H6_AND_H7", 0x376d8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H8_AND_H9", 0x376dc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H10_AND_H11", 0x376e0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H12", 0x376e4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2", 0x376f8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1", 0x376fc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE", 0x37700, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL", 0x37704, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL", 0x37708, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL", 0x3770c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1", 0x37710, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2", 0x37714, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37718, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3771c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_CONTROL", 0x37720, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1", 0x37724, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2", 0x37728, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1", 0x3772c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2", 0x37730, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3", 0x37734, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1", 0x37738, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3", 0x37740, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN", 0x37748, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ", 0x3774c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL", 0x37750, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3775c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x37760, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x37764, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37770, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC", 0x37774, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS", 0x37778, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1", 0x3777c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2", 0x37780, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2", 0x37784, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2", 0x37788, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4", 0x3778c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4", 0x37790, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET", 0x37794, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL", 0x37798, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL", 0x3779c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH", 0x377a0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET", 0x377a4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL", 0x377a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS", 0x377ac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x377b0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x377b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x377b8, 0 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_TAP_ENABLE", 0x377c0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1", 0x377c4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H2", 0x377c8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H3", 0x377cc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H4", 0x377d0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H5", 0x377d4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H6_AND_H7", 0x377d8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H8_AND_H9", 0x377dc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H10_AND_H11", 0x377e0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H12", 0x377e4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2", 0x377f8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1", 0x377fc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE", 0x37a00, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL", 0x37a04, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL", 0x37a08, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL", 0x37a0c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1", 0x37a10, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2", 0x37a14, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x37a18, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x37a1c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_CONTROL", 0x37a20, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1", 0x37a24, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2", 0x37a28, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1", 0x37a2c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2", 0x37a30, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3", 0x37a34, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1", 0x37a38, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3", 0x37a40, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN", 0x37a48, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ", 0x37a4c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL", 0x37a50, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x37a5c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x37a60, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x37a64, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x37a70, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC", 0x37a74, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS", 0x37a78, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1", 0x37a7c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2", 0x37a80, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2", 0x37a84, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2", 0x37a88, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4", 0x37a8c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4", 0x37a90, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET", 0x37a94, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL", 0x37a98, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL", 0x37a9c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH", 0x37aa0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET", 0x37aa4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL", 0x37aa8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS", 0x37aac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x37ab0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x37ab4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x37ab8, 0 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE", 0x37ac0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1", 0x37ac4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H2", 0x37ac8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H3", 0x37acc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H4", 0x37ad0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H5", 0x37ad4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7", 0x37ad8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9", 0x37adc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11", 0x37ae0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H12", 0x37ae4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2", 0x37af8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1", 0x37afc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_CFG", 0x38800, 0 },
|
|
{ "MAC_Clk_Sel", 29, 3 },
|
|
{ "SinkTx", 27, 1 },
|
|
{ "SinkTxOnLinkDown", 26, 1 },
|
|
{ "LoopNoFwd", 24, 1 },
|
|
{ "Smux_Rx_Loop", 19, 1 },
|
|
{ "Rx_Lane_Swap", 18, 1 },
|
|
{ "Tx_Lane_Swap", 17, 1 },
|
|
{ "Signal_Det", 14, 1 },
|
|
{ "SmuxTxSel", 9, 1 },
|
|
{ "SmuxRxSel", 8, 1 },
|
|
{ "PortSpeed", 4, 2 },
|
|
{ "Rx_Byte_Swap", 3, 1 },
|
|
{ "Tx_Byte_Swap", 2, 1 },
|
|
{ "Port_Sel", 0, 1 },
|
|
{ "MAC_PORT_RESET_CTRL", 0x38804, 0 },
|
|
{ "TWGDSK_HSSC16B", 31, 1 },
|
|
{ "EEE_RESET", 30, 1 },
|
|
{ "PTP_TIMER", 29, 1 },
|
|
{ "MtipRefReset", 28, 1 },
|
|
{ "MtipTxffReset", 27, 1 },
|
|
{ "MtipRxffReset", 26, 1 },
|
|
{ "MtipRegReset", 25, 1 },
|
|
{ "AEC3Reset", 23, 1 },
|
|
{ "AEC2Reset", 22, 1 },
|
|
{ "AEC1Reset", 21, 1 },
|
|
{ "AEC0Reset", 20, 1 },
|
|
{ "AET3Reset", 19, 1 },
|
|
{ "AET2Reset", 18, 1 },
|
|
{ "AET1Reset", 17, 1 },
|
|
{ "AET0Reset", 16, 1 },
|
|
{ "TXIF_Reset", 12, 1 },
|
|
{ "RXIF_Reset", 11, 1 },
|
|
{ "AuxExt_Reset", 10, 1 },
|
|
{ "MtipSd3TxRst", 9, 1 },
|
|
{ "MtipSd2TxRst", 8, 1 },
|
|
{ "MtipSd1TxRst", 7, 1 },
|
|
{ "MtipSd0TxRst", 6, 1 },
|
|
{ "MtipSd3RxRst", 5, 1 },
|
|
{ "MtipSd2RxRst", 4, 1 },
|
|
{ "MtipSd1RxRst", 3, 1 },
|
|
{ "WOL_Reset", 2, 1 },
|
|
{ "MtipSd0RxRst", 1, 1 },
|
|
{ "HSS_Reset", 0, 1 },
|
|
{ "MAC_PORT_LED_CFG", 0x38808, 0 },
|
|
{ "Led1_Cfg", 5, 3 },
|
|
{ "Led1_Polarity_Inv", 4, 1 },
|
|
{ "Led0_Cfg", 1, 3 },
|
|
{ "Led0_Polarity_Inv", 0, 1 },
|
|
{ "MAC_PORT_LED_COUNTHI", 0x3880c, 0 },
|
|
{ "MAC_PORT_LED_COUNTLO", 0x38810, 0 },
|
|
{ "MAC_PORT_CFG3", 0x38814, 0 },
|
|
{ "FPGA_PTP_PORT", 26, 2 },
|
|
{ "FCSDisCtrl", 25, 1 },
|
|
{ "SigDetCtrl", 24, 1 },
|
|
{ "tx_lane", 23, 1 },
|
|
{ "rx_lane", 22, 1 },
|
|
{ "se_clr", 21, 1 },
|
|
{ "an_ena", 17, 4 },
|
|
{ "sd_rx_clk_ena", 13, 4 },
|
|
{ "sd_tx_clk_ena", 9, 4 },
|
|
{ "SGMIISEL", 8, 1 },
|
|
{ "HSSPLLSEL", 4, 4 },
|
|
{ "HSSC16C20SEL", 0, 4 },
|
|
{ "MAC_PORT_CFG2", 0x38818, 0 },
|
|
{ "Rx_Polarity_Inv", 28, 4 },
|
|
{ "Tx_Polarity_Inv", 24, 4 },
|
|
{ "InstanceNum", 22, 2 },
|
|
{ "StopOnPerr", 21, 1 },
|
|
{ "PatEn", 18, 1 },
|
|
{ "MagicEn", 17, 1 },
|
|
{ "T5_AEC_PMA_TX_READY", 4, 4 },
|
|
{ "T5_AEC_PMA_RX_READY", 0, 4 },
|
|
{ "MAC_PORT_PKT_COUNT", 0x3881c, 0 },
|
|
{ "tx_sop_count", 24, 8 },
|
|
{ "tx_eop_count", 16, 8 },
|
|
{ "rx_sop_count", 8, 8 },
|
|
{ "rx_eop_count", 0, 8 },
|
|
{ "MAC_PORT_CFG4", 0x38820, 0 },
|
|
{ "AEC3_RX_WIDTH", 14, 2 },
|
|
{ "AEC2_RX_WIDTH", 12, 2 },
|
|
{ "AEC1_RX_WIDTH", 10, 2 },
|
|
{ "AEC0_RX_WIDTH", 8, 2 },
|
|
{ "AEC3_TX_WIDTH", 6, 2 },
|
|
{ "AEC2_TX_WIDTH", 4, 2 },
|
|
{ "AEC1_TX_WIDTH", 2, 2 },
|
|
{ "AEC0_TX_WIDTH", 0, 2 },
|
|
{ "MAC_PORT_MAGIC_MACID_LO", 0x38824, 0 },
|
|
{ "MAC_PORT_MAGIC_MACID_HI", 0x38828, 0 },
|
|
{ "MAC_PORT_LINK_STATUS", 0x38834, 0 },
|
|
{ "an_done", 6, 1 },
|
|
{ "align_done", 5, 1 },
|
|
{ "block_lock", 4, 1 },
|
|
{ "remflt", 3, 1 },
|
|
{ "locflt", 2, 1 },
|
|
{ "linkup", 1, 1 },
|
|
{ "linkdn", 0, 1 },
|
|
{ "MAC_PORT_EPIO_DATA0", 0x388c0, 0 },
|
|
{ "MAC_PORT_EPIO_DATA1", 0x388c4, 0 },
|
|
{ "MAC_PORT_EPIO_DATA2", 0x388c8, 0 },
|
|
{ "MAC_PORT_EPIO_DATA3", 0x388cc, 0 },
|
|
{ "MAC_PORT_EPIO_OP", 0x388d0, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Write", 8, 1 },
|
|
{ "Address", 0, 8 },
|
|
{ "MAC_PORT_WOL_STATUS", 0x388d4, 0 },
|
|
{ "MagicDetected", 31, 1 },
|
|
{ "PatDetected", 30, 1 },
|
|
{ "ClearMagic", 4, 1 },
|
|
{ "ClearMatch", 3, 1 },
|
|
{ "MatchedFilter", 0, 3 },
|
|
{ "MAC_PORT_INT_EN", 0x388d8, 0 },
|
|
{ "tx_ts_avail", 29, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "an_page_rcvd", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "MAC_PORT_INT_CAUSE", 0x388dc, 0 },
|
|
{ "tx_ts_avail", 29, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "an_page_rcvd", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "MAC_PORT_PERR_INT_EN", 0x388e0, 0 },
|
|
{ "Perr_pkt_ram", 24, 1 },
|
|
{ "Perr_mask_ram", 23, 1 },
|
|
{ "Perr_crc_ram", 22, 1 },
|
|
{ "rx_dff_seg0", 21, 1 },
|
|
{ "rx_sff_seg0", 20, 1 },
|
|
{ "rx_dff_mac10", 19, 1 },
|
|
{ "rx_sff_mac10", 18, 1 },
|
|
{ "tx_dff_seg0", 17, 1 },
|
|
{ "tx_sff_seg0", 16, 1 },
|
|
{ "tx_dff_mac10", 15, 1 },
|
|
{ "tx_sff_mac10", 14, 1 },
|
|
{ "rx_stats", 13, 1 },
|
|
{ "tx_stats", 12, 1 },
|
|
{ "Perr3_rx_mix", 11, 1 },
|
|
{ "Perr3_rx_sd", 10, 1 },
|
|
{ "Perr3_tx", 9, 1 },
|
|
{ "Perr2_rx_mix", 8, 1 },
|
|
{ "Perr2_rx_sd", 7, 1 },
|
|
{ "Perr2_tx", 6, 1 },
|
|
{ "Perr1_rx_mix", 5, 1 },
|
|
{ "Perr1_rx_sd", 4, 1 },
|
|
{ "Perr1_tx", 3, 1 },
|
|
{ "Perr0_rx_mix", 2, 1 },
|
|
{ "Perr0_rx_sd", 1, 1 },
|
|
{ "Perr0_tx", 0, 1 },
|
|
{ "MAC_PORT_PERR_INT_CAUSE", 0x388e4, 0 },
|
|
{ "Perr_pkt_ram", 24, 1 },
|
|
{ "Perr_mask_ram", 23, 1 },
|
|
{ "Perr_crc_ram", 22, 1 },
|
|
{ "rx_dff_seg0", 21, 1 },
|
|
{ "rx_sff_seg0", 20, 1 },
|
|
{ "rx_dff_mac10", 19, 1 },
|
|
{ "rx_sff_mac10", 18, 1 },
|
|
{ "tx_dff_seg0", 17, 1 },
|
|
{ "tx_sff_seg0", 16, 1 },
|
|
{ "tx_dff_mac10", 15, 1 },
|
|
{ "tx_sff_mac10", 14, 1 },
|
|
{ "rx_stats", 13, 1 },
|
|
{ "tx_stats", 12, 1 },
|
|
{ "Perr3_rx_mix", 11, 1 },
|
|
{ "Perr3_rx_sd", 10, 1 },
|
|
{ "Perr3_tx", 9, 1 },
|
|
{ "Perr2_rx_mix", 8, 1 },
|
|
{ "Perr2_rx_sd", 7, 1 },
|
|
{ "Perr2_tx", 6, 1 },
|
|
{ "Perr1_rx_mix", 5, 1 },
|
|
{ "Perr1_rx_sd", 4, 1 },
|
|
{ "Perr1_tx", 3, 1 },
|
|
{ "Perr0_rx_mix", 2, 1 },
|
|
{ "Perr0_rx_sd", 1, 1 },
|
|
{ "Perr0_tx", 0, 1 },
|
|
{ "MAC_PORT_PERR_ENABLE", 0x388e8, 0 },
|
|
{ "Perr_pkt_ram", 24, 1 },
|
|
{ "Perr_mask_ram", 23, 1 },
|
|
{ "Perr_crc_ram", 22, 1 },
|
|
{ "rx_dff_seg0", 21, 1 },
|
|
{ "rx_sff_seg0", 20, 1 },
|
|
{ "rx_dff_mac10", 19, 1 },
|
|
{ "rx_sff_mac10", 18, 1 },
|
|
{ "tx_dff_seg0", 17, 1 },
|
|
{ "tx_sff_seg0", 16, 1 },
|
|
{ "tx_dff_mac10", 15, 1 },
|
|
{ "tx_sff_mac10", 14, 1 },
|
|
{ "rx_stats", 13, 1 },
|
|
{ "tx_stats", 12, 1 },
|
|
{ "Perr3_rx_mix", 11, 1 },
|
|
{ "Perr3_rx_sd", 10, 1 },
|
|
{ "Perr3_tx", 9, 1 },
|
|
{ "Perr2_rx_mix", 8, 1 },
|
|
{ "Perr2_rx_sd", 7, 1 },
|
|
{ "Perr2_tx", 6, 1 },
|
|
{ "Perr1_rx_mix", 5, 1 },
|
|
{ "Perr1_rx_sd", 4, 1 },
|
|
{ "Perr1_tx", 3, 1 },
|
|
{ "Perr0_rx_mix", 2, 1 },
|
|
{ "Perr0_rx_sd", 1, 1 },
|
|
{ "Perr0_tx", 0, 1 },
|
|
{ "MAC_PORT_PERR_INJECT", 0x388ec, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MAC_PORT_HSS_CFG0", 0x388f0, 0 },
|
|
{ "TXDTS", 31, 1 },
|
|
{ "TXCTS", 30, 1 },
|
|
{ "TXBTS", 29, 1 },
|
|
{ "TXATS", 28, 1 },
|
|
{ "TXDOBS", 27, 1 },
|
|
{ "TXCOBS", 26, 1 },
|
|
{ "TXBOBS", 25, 1 },
|
|
{ "TXAOBS", 24, 1 },
|
|
{ "HSSREFCLKVALIDA", 20, 1 },
|
|
{ "HSSREFCLKVALIDB", 19, 1 },
|
|
{ "HSSRESYNCA", 18, 1 },
|
|
{ "HSSAVDHI", 17, 1 },
|
|
{ "HSSRESYNCB", 16, 1 },
|
|
{ "HSSRECCALA", 15, 1 },
|
|
{ "HSSRXACMODE", 14, 1 },
|
|
{ "HSSRECCALB", 13, 1 },
|
|
{ "HSSPLLBYPA", 12, 1 },
|
|
{ "HSSPLLBYPB", 11, 1 },
|
|
{ "HSSPDWNPLLA", 10, 1 },
|
|
{ "HSSPDWNPLLB", 9, 1 },
|
|
{ "HSSVCOSELA", 8, 1 },
|
|
{ "HSSVCOSELB", 7, 1 },
|
|
{ "HSSCALCOMP", 6, 1 },
|
|
{ "HSSCALENAB", 5, 1 },
|
|
{ "HSSEXTC16SEL", 4, 1 },
|
|
{ "MAC_PORT_HSS_CFG1", 0x388f4, 0 },
|
|
{ "RXACONFIGSEL", 30, 2 },
|
|
{ "RXAQUIET", 29, 1 },
|
|
{ "RXAREFRESH", 28, 1 },
|
|
{ "RXBCONFIGSEL", 26, 2 },
|
|
{ "RXBQUIET", 25, 1 },
|
|
{ "RXBREFRESH", 24, 1 },
|
|
{ "RXCCONFIGSEL", 22, 2 },
|
|
{ "RXCQUIET", 21, 1 },
|
|
{ "RXCREFRESH", 20, 1 },
|
|
{ "RXDCONFIGSEL", 18, 2 },
|
|
{ "RXDQUIET", 17, 1 },
|
|
{ "RXDREFRESH", 16, 1 },
|
|
{ "TXACONFIGSEL", 14, 2 },
|
|
{ "TXAQUIET", 13, 1 },
|
|
{ "TXAREFRESH", 12, 1 },
|
|
{ "TXBCONFIGSEL", 10, 2 },
|
|
{ "TXBQUIET", 9, 1 },
|
|
{ "TXBREFRESH", 8, 1 },
|
|
{ "TXCCONFIGSEL", 6, 2 },
|
|
{ "TXCQUIET", 5, 1 },
|
|
{ "TXCREFRESH", 4, 1 },
|
|
{ "TXDCONFIGSEL", 2, 2 },
|
|
{ "TXDQUIET", 1, 1 },
|
|
{ "TXDREFRESH", 0, 1 },
|
|
{ "MAC_PORT_HSS_CFG2", 0x388f8, 0 },
|
|
{ "RXAASSTCLK", 31, 1 },
|
|
{ "T5RXAPRBSRST", 30, 1 },
|
|
{ "RXBASSTCLK", 29, 1 },
|
|
{ "T5RXBPRBSRST", 28, 1 },
|
|
{ "RXCASSTCLK", 27, 1 },
|
|
{ "T5RXCPRBSRST", 26, 1 },
|
|
{ "RXDASSTCLK", 25, 1 },
|
|
{ "T5RXDPRBSRST", 24, 1 },
|
|
{ "RXDDATASYNC", 23, 1 },
|
|
{ "RXCDATASYNC", 22, 1 },
|
|
{ "RXBDATASYNC", 21, 1 },
|
|
{ "RXADATASYNC", 20, 1 },
|
|
{ "RXDEARLYIN", 19, 1 },
|
|
{ "RXDLATEIN", 18, 1 },
|
|
{ "RXDPHSLOCK", 17, 1 },
|
|
{ "RXDPHSDNIN", 16, 1 },
|
|
{ "RXDPHSUPIN", 15, 1 },
|
|
{ "RXCEARLYIN", 14, 1 },
|
|
{ "RXCLATEIN", 13, 1 },
|
|
{ "RXCPHSLOCK", 12, 1 },
|
|
{ "RXCPHSDNIN", 11, 1 },
|
|
{ "RXCPHSUPIN", 10, 1 },
|
|
{ "RXBEARLYIN", 9, 1 },
|
|
{ "RXBLATEIN", 8, 1 },
|
|
{ "RXBPHSLOCK", 7, 1 },
|
|
{ "RXBPHSDNIN", 6, 1 },
|
|
{ "RXBPHSUPIN", 5, 1 },
|
|
{ "RXAEARLYIN", 4, 1 },
|
|
{ "RXALATEIN", 3, 1 },
|
|
{ "RXAPHSLOCK", 2, 1 },
|
|
{ "RXAPHSDNIN", 1, 1 },
|
|
{ "RXAPHSUPIN", 0, 1 },
|
|
{ "MAC_PORT_HSS_CFG3", 0x388fc, 0 },
|
|
{ "HSSCALSSTN", 25, 3 },
|
|
{ "HSSCALSSTP", 22, 3 },
|
|
{ "HSSVBOOSTDIVB", 19, 3 },
|
|
{ "HSSVBOOSTDIVA", 16, 3 },
|
|
{ "HSSPLLCONFIGB", 8, 8 },
|
|
{ "HSSPLLCONFIGA", 0, 8 },
|
|
{ "MAC_PORT_HSS_CFG4", 0x38900, 0 },
|
|
{ "HSSDIVSELA", 9, 9 },
|
|
{ "HSSDIVSELB", 0, 9 },
|
|
{ "MAC_PORT_HSS_STATUS", 0x38904, 0 },
|
|
{ "RXDPRBSSYNC", 15, 1 },
|
|
{ "RXCPRBSSYNC", 14, 1 },
|
|
{ "RXBPRBSSYNC", 13, 1 },
|
|
{ "RXAPRBSSYNC", 12, 1 },
|
|
{ "RXDPRBSERR", 11, 1 },
|
|
{ "RXCPRBSERR", 10, 1 },
|
|
{ "RXBPRBSERR", 9, 1 },
|
|
{ "RXAPRBSERR", 8, 1 },
|
|
{ "RXDSIGDET", 7, 1 },
|
|
{ "RXCSIGDET", 6, 1 },
|
|
{ "RXBSIGDET", 5, 1 },
|
|
{ "RXASIGDET", 4, 1 },
|
|
{ "HSSPLLLOCKB", 3, 1 },
|
|
{ "HSSPLLLOCKA", 2, 1 },
|
|
{ "HSSPRTREADYB", 1, 1 },
|
|
{ "HSSPRTREADYA", 0, 1 },
|
|
{ "MAC_PORT_HSS_EEE_STATUS", 0x38908, 0 },
|
|
{ "RXAQUIET_STATUS", 15, 1 },
|
|
{ "RXAREFRESH_STATUS", 14, 1 },
|
|
{ "RXBQUIET_STATUS", 13, 1 },
|
|
{ "RXBREFRESH_STATUS", 12, 1 },
|
|
{ "RXCQUIET_STATUS", 11, 1 },
|
|
{ "RXCREFRESH_STATUS", 10, 1 },
|
|
{ "RXDQUIET_STATUS", 9, 1 },
|
|
{ "RXDREFRESH_STATUS", 8, 1 },
|
|
{ "TXAQUIET_STATUS", 7, 1 },
|
|
{ "TXAREFRESH_STATUS", 6, 1 },
|
|
{ "TXBQUIET_STATUS", 5, 1 },
|
|
{ "TXBREFRESH_STATUS", 4, 1 },
|
|
{ "TXCQUIET_STATUS", 3, 1 },
|
|
{ "TXCREFRESH_STATUS", 2, 1 },
|
|
{ "TXDQUIET_STATUS", 1, 1 },
|
|
{ "TXDREFRESH_STATUS", 0, 1 },
|
|
{ "MAC_PORT_HSS_SIGDET_STATUS", 0x3890c, 0 },
|
|
{ "MAC_PORT_HSS_PL_CTL", 0x38910, 0 },
|
|
{ "TOV", 16, 8 },
|
|
{ "TSU", 8, 8 },
|
|
{ "IPW", 0, 8 },
|
|
{ "MAC_PORT_RUNT_FRAME", 0x38914, 0 },
|
|
{ "runtclear", 16, 1 },
|
|
{ "runt", 0, 16 },
|
|
{ "MAC_PORT_EEE_STATUS", 0x38918, 0 },
|
|
{ "eee_tx_10g_state", 10, 2 },
|
|
{ "eee_rx_10g_state", 8, 2 },
|
|
{ "eee_tx_1g_state", 6, 2 },
|
|
{ "eee_rx_1g_state", 4, 2 },
|
|
{ "pma_rx_refresh", 3, 1 },
|
|
{ "pma_rx_quiet", 2, 1 },
|
|
{ "pma_tx_refresh", 1, 1 },
|
|
{ "pma_tx_quiet", 0, 1 },
|
|
{ "MAC_PORT_CGEN", 0x3891c, 0 },
|
|
{ "CGEN", 8, 1 },
|
|
{ "sd7_CGEN", 7, 1 },
|
|
{ "sd6_CGEN", 6, 1 },
|
|
{ "sd5_CGEN", 5, 1 },
|
|
{ "sd4_CGEN", 4, 1 },
|
|
{ "sd3_CGEN", 3, 1 },
|
|
{ "sd2_CGEN", 2, 1 },
|
|
{ "sd1_CGEN", 1, 1 },
|
|
{ "sd0_CGEN", 0, 1 },
|
|
{ "MAC_PORT_CGEN_MTIP", 0x38920, 0 },
|
|
{ "MACSEG5_CGEN", 11, 1 },
|
|
{ "PCSSEG5_CGEN", 10, 1 },
|
|
{ "MACSEG4_CGEN", 9, 1 },
|
|
{ "PCSSEG4_CGEN", 8, 1 },
|
|
{ "MACSEG3_CGEN", 7, 1 },
|
|
{ "PCSSEG3_CGEN", 6, 1 },
|
|
{ "MACSEG2_CGEN", 5, 1 },
|
|
{ "PCSSEG2_CGEN", 4, 1 },
|
|
{ "MACSEG1_CGEN", 3, 1 },
|
|
{ "PCSSEG1_CGEN", 2, 1 },
|
|
{ "MACSEG0_CGEN", 1, 1 },
|
|
{ "PCSSEG0_CGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_TS_ID", 0x38924, 0 },
|
|
{ "MAC_PORT_TX_TS_VAL_LO", 0x38928, 0 },
|
|
{ "MAC_PORT_TX_TS_VAL_HI", 0x3892c, 0 },
|
|
{ "MAC_PORT_EEE_CTL", 0x38930, 0 },
|
|
{ "EEE_CTRL", 2, 30 },
|
|
{ "TICK_START", 1, 1 },
|
|
{ "En", 0, 1 },
|
|
{ "MAC_PORT_EEE_TX_CTL", 0x38934, 0 },
|
|
{ "WAKE_TIMER", 16, 16 },
|
|
{ "HSS_TIMER", 5, 4 },
|
|
{ "HSS_CTL", 4, 1 },
|
|
{ "LPI_ACTIVE", 3, 1 },
|
|
{ "LPI_TXHOLD", 2, 1 },
|
|
{ "LPI_REQ", 1, 1 },
|
|
{ "EEE_TX_RESET", 0, 1 },
|
|
{ "MAC_PORT_EEE_RX_CTL", 0x38938, 0 },
|
|
{ "WAKE_TIMER", 16, 16 },
|
|
{ "HSS_TIMER", 5, 4 },
|
|
{ "HSS_CTL", 4, 1 },
|
|
{ "LPI_IND", 1, 1 },
|
|
{ "EEE_RX_RESET", 0, 1 },
|
|
{ "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x3893c, 0 },
|
|
{ "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x38940, 0 },
|
|
{ "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x38944, 0 },
|
|
{ "MAC_PORT_EEE_TX_1G_SLEEP_TIMER", 0x38948, 0 },
|
|
{ "MAC_PORT_EEE_TX_1G_QUIET_TIMER", 0x3894c, 0 },
|
|
{ "MAC_PORT_EEE_TX_1G_REFRESH_TIMER", 0x38950, 0 },
|
|
{ "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x38954, 0 },
|
|
{ "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x38958, 0 },
|
|
{ "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x3895c, 0 },
|
|
{ "MAC_PORT_EEE_RX_1G_QUIET_TIMER", 0x38960, 0 },
|
|
{ "MAC_PORT_EEE_RX_1G_WAKE_TIMER", 0x38964, 0 },
|
|
{ "MAC_PORT_EEE_WF_COUNT", 0x38968, 0 },
|
|
{ "wake_cnt_clr", 16, 1 },
|
|
{ "wake_cnt", 0, 16 },
|
|
{ "MAC_PORT_PTP_TIMER_RD0_LO", 0x3896c, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_RD0_HI", 0x38970, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_RD1_LO", 0x38974, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_RD1_HI", 0x38978, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_WR_LO", 0x3897c, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_WR_HI", 0x38980, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_OFFSET_0", 0x38984, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_OFFSET_1", 0x38988, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_OFFSET_2", 0x3898c, 0 },
|
|
{ "MAC_PORT_PTP_SUM_LO", 0x38990, 0 },
|
|
{ "MAC_PORT_PTP_SUM_HI", 0x38994, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_INCR0", 0x38998, 0 },
|
|
{ "Y", 16, 16 },
|
|
{ "X", 0, 16 },
|
|
{ "MAC_PORT_PTP_TIMER_INCR1", 0x3899c, 0 },
|
|
{ "Y_TICK", 16, 16 },
|
|
{ "X_TICK", 0, 16 },
|
|
{ "MAC_PORT_PTP_DRIFT_ADJUST_COUNT", 0x389a0, 0 },
|
|
{ "MAC_PORT_PTP_OFFSET_ADJUST_FINE", 0x389a4, 0 },
|
|
{ "B", 16, 16 },
|
|
{ "A", 0, 16 },
|
|
{ "MAC_PORT_PTP_OFFSET_ADJUST_TOTAL", 0x389a8, 0 },
|
|
{ "MAC_PORT_PTP_CFG", 0x389ac, 0 },
|
|
{ "FRZ", 18, 1 },
|
|
{ "OFFSER_ADJUST_SIGN", 17, 1 },
|
|
{ "ADD_OFFSET", 16, 1 },
|
|
{ "CYCLE1", 8, 8 },
|
|
{ "Q", 0, 8 },
|
|
{ "MAC_PORT_MTIP_REVISION", 0x38a00, 0 },
|
|
{ "CUSTREV", 16, 16 },
|
|
{ "VER", 8, 8 },
|
|
{ "REV", 0, 8 },
|
|
{ "MAC_PORT_MTIP_SCRATCH", 0x38a04, 0 },
|
|
{ "MAC_PORT_MTIP_COMMAND_CONFIG", 0x38a08, 0 },
|
|
{ "TX_FLUSH", 22, 1 },
|
|
{ "RX_SFD_ANY", 21, 1 },
|
|
{ "PAUSE_PFC_COMP", 20, 1 },
|
|
{ "PFC_MODE", 19, 1 },
|
|
{ "RS_COL_CNT_EXT", 18, 1 },
|
|
{ "NO_LGTH_CHECK", 17, 1 },
|
|
{ "SEND_IDLE", 16, 1 },
|
|
{ "PHY_TXENA", 15, 1 },
|
|
{ "RX_ERR_DISC", 14, 1 },
|
|
{ "CMD_FRAME_ENA", 13, 1 },
|
|
{ "SW_RESET", 12, 1 },
|
|
{ "TX_PAD_EN", 11, 1 },
|
|
{ "LOOPBACK_EN", 10, 1 },
|
|
{ "TX_ADDR_INS", 9, 1 },
|
|
{ "PAUSE_IGNORE", 8, 1 },
|
|
{ "PAUSE_FWD", 7, 1 },
|
|
{ "CRC_FWD", 6, 1 },
|
|
{ "PAD_EN", 5, 1 },
|
|
{ "PROMIS_EN", 4, 1 },
|
|
{ "WAN_MODE", 3, 1 },
|
|
{ "RX_ENA", 1, 1 },
|
|
{ "TX_ENA", 0, 1 },
|
|
{ "MAC_PORT_MTIP_MAC_ADDR_0", 0x38a0c, 0 },
|
|
{ "MAC_PORT_MTIP_MAC_ADDR_1", 0x38a10, 0 },
|
|
{ "MAC_PORT_MTIP_FRM_LENGTH", 0x38a14, 0 },
|
|
{ "MAC_PORT_MTIP_RX_FIFO_SECTIONS", 0x38a1c, 0 },
|
|
{ "AVAIL", 16, 16 },
|
|
{ "EMPTY", 0, 16 },
|
|
{ "MAC_PORT_MTIP_TX_FIFO_SECTIONS", 0x38a20, 0 },
|
|
{ "AVAIL", 16, 16 },
|
|
{ "EMPTY", 0, 16 },
|
|
{ "MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E", 0x38a24, 0 },
|
|
{ "AlmstFull", 16, 16 },
|
|
{ "AlmstEmpty", 0, 16 },
|
|
{ "MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E", 0x38a28, 0 },
|
|
{ "AlmstFull", 16, 16 },
|
|
{ "AlmstEmpty", 0, 16 },
|
|
{ "MAC_PORT_MTIP_HASHTABLE_LOAD", 0x38a2c, 0 },
|
|
{ "ENABLE", 8, 1 },
|
|
{ "ADDR", 0, 6 },
|
|
{ "MAC_PORT_MTIP_MAC_STATUS", 0x38a40, 0 },
|
|
{ "TS_AVAIL", 3, 1 },
|
|
{ "PHY_LOS", 2, 1 },
|
|
{ "RX_REM_FAULT", 1, 1 },
|
|
{ "RX_LOC_FAULT", 0, 1 },
|
|
{ "MAC_PORT_MTIP_TX_IPG_LENGTH", 0x38a44, 0 },
|
|
{ "MAC_PORT_MTIP_MAC_CREDIT_TRIGGER", 0x38a48, 0 },
|
|
{ "MAC_PORT_MTIP_INIT_CREDIT", 0x38a4c, 0 },
|
|
{ "MAC_PORT_MTIP_CURRENT_CREDIT", 0x38a50, 0 },
|
|
{ "MAC_PORT_RX_PAUSE_STATUS", 0x38a74, 0 },
|
|
{ "MAC_PORT_MTIP_TS_TIMESTAMP", 0x38a7c, 0 },
|
|
{ "MAC_PORT_AFRAMESTRANSMITTEDOK", 0x38a80, 0 },
|
|
{ "MAC_PORT_AFRAMESTRANSMITTEDOKHI", 0x38a84, 0 },
|
|
{ "MAC_PORT_AFRAMESRECEIVEDOK", 0x38a88, 0 },
|
|
{ "MAC_PORT_AFRAMESRECEIVEDOKHI", 0x38a8c, 0 },
|
|
{ "MAC_PORT_AFRAMECHECKSEQUENCEERRORS", 0x38a90, 0 },
|
|
{ "MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI", 0x38a94, 0 },
|
|
{ "MAC_PORT_AALIGNMENTERRORS", 0x38a98, 0 },
|
|
{ "MAC_PORT_AALIGNMENTERRORSHI", 0x38a9c, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED", 0x38aa0, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI", 0x38aa4, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED", 0x38aa8, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI", 0x38aac, 0 },
|
|
{ "MAC_PORT_AFRAMETOOLONGERRORS", 0x38ab0, 0 },
|
|
{ "MAC_PORT_AFRAMETOOLONGERRORSHI", 0x38ab4, 0 },
|
|
{ "MAC_PORT_AINRANGELENGTHERRORS", 0x38ab8, 0 },
|
|
{ "MAC_PORT_AINRANGELENGTHERRORSHI", 0x38abc, 0 },
|
|
{ "MAC_PORT_VLANTRANSMITTEDOK", 0x38ac0, 0 },
|
|
{ "MAC_PORT_VLANTRANSMITTEDOKHI", 0x38ac4, 0 },
|
|
{ "MAC_PORT_VLANRECEIVEDOK", 0x38ac8, 0 },
|
|
{ "MAC_PORT_VLANRECEIVEDOKHI", 0x38acc, 0 },
|
|
{ "MAC_PORT_AOCTETSTRANSMITTEDOK", 0x38ad0, 0 },
|
|
{ "MAC_PORT_AOCTETSTRANSMITTEDOKHI", 0x38ad4, 0 },
|
|
{ "MAC_PORT_AOCTETSRECEIVEDOK", 0x38ad8, 0 },
|
|
{ "MAC_PORT_AOCTETSRECEIVEDOKHI", 0x38adc, 0 },
|
|
{ "MAC_PORT_IFINUCASTPKTS", 0x38ae0, 0 },
|
|
{ "MAC_PORT_IFINUCASTPKTSHI", 0x38ae4, 0 },
|
|
{ "MAC_PORT_IFINMULTICASTPKTS", 0x38ae8, 0 },
|
|
{ "MAC_PORT_IFINMULTICASTPKTSHI", 0x38aec, 0 },
|
|
{ "MAC_PORT_IFINBROADCASTPKTS", 0x38af0, 0 },
|
|
{ "MAC_PORT_IFINBROADCASTPKTSHI", 0x38af4, 0 },
|
|
{ "MAC_PORT_IFOUTERRORS", 0x38af8, 0 },
|
|
{ "MAC_PORT_IFOUTERRORSHI", 0x38afc, 0 },
|
|
{ "MAC_PORT_IFOUTUCASTPKTS", 0x38b08, 0 },
|
|
{ "MAC_PORT_IFOUTUCASTPKTSHI", 0x38b0c, 0 },
|
|
{ "MAC_PORT_IFOUTMULTICASTPKTS", 0x38b10, 0 },
|
|
{ "MAC_PORT_IFOUTMULTICASTPKTSHI", 0x38b14, 0 },
|
|
{ "MAC_PORT_IFOUTBROADCASTPKTS", 0x38b18, 0 },
|
|
{ "MAC_PORT_IFOUTBROADCASTPKTSHI", 0x38b1c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSDROPEVENTS", 0x38b20, 0 },
|
|
{ "MAC_PORT_ETHERSTATSDROPEVENTSHI", 0x38b24, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOCTETS", 0x38b28, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOCTETSHI", 0x38b2c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS", 0x38b30, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTSHI", 0x38b34, 0 },
|
|
{ "MAC_PORT_ETHERSTATSUNDERSIZEPKTS", 0x38b38, 0 },
|
|
{ "MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI", 0x38b3c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS64OCTETS", 0x38b40, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS64OCTETSHI", 0x38b44, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS65TO127OCTETS", 0x38b48, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI", 0x38b4c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS128TO255OCTETS", 0x38b50, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI", 0x38b54, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS256TO511OCTETS", 0x38b58, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI", 0x38b5c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS", 0x38b60, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI", 0x38b64, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS", 0x38b68, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x38b6c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS", 0x38b70, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI", 0x38b74, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOVERSIZEPKTS", 0x38b78, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOVERSIZEPKTSHI", 0x38b7c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSJABBERS", 0x38b80, 0 },
|
|
{ "MAC_PORT_ETHERSTATSJABBERSHI", 0x38b84, 0 },
|
|
{ "MAC_PORT_ETHERSTATSFRAGMENTS", 0x38b88, 0 },
|
|
{ "MAC_PORT_ETHERSTATSFRAGMENTSHI", 0x38b8c, 0 },
|
|
{ "MAC_PORT_IFINERRORS", 0x38b90, 0 },
|
|
{ "MAC_PORT_IFINERRORSHI", 0x38b94, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0", 0x38b98, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI", 0x38b9c, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1", 0x38ba0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI", 0x38ba4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2", 0x38ba8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI", 0x38bac, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3", 0x38bb0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI", 0x38bb4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4", 0x38bb8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI", 0x38bbc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5", 0x38bc0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI", 0x38bc4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6", 0x38bc8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI", 0x38bcc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7", 0x38bd0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI", 0x38bd4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0", 0x38bd8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI", 0x38bdc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1", 0x38be0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI", 0x38be4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2", 0x38be8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI", 0x38bec, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3", 0x38bf0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI", 0x38bf4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4", 0x38bf8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI", 0x38bfc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5", 0x38c00, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI", 0x38c04, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6", 0x38c08, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI", 0x38c0c, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7", 0x38c10, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI", 0x38c14, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESTRANSMITTED", 0x38c18, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI", 0x38c1c, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESRECEIVED", 0x38c20, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI", 0x38c24, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_CONTROL", 0x38d00, 0 },
|
|
{ "Reset", 15, 1 },
|
|
{ "Loopback", 14, 1 },
|
|
{ "sppedsel1", 13, 1 },
|
|
{ "AN_EN", 12, 1 },
|
|
{ "PWRDWN", 11, 1 },
|
|
{ "Isolate", 10, 1 },
|
|
{ "AN_RESTART", 9, 1 },
|
|
{ "DPLX", 8, 1 },
|
|
{ "CollisionTest", 7, 1 },
|
|
{ "SpeedSel0", 6, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_STATUS", 0x38d04, 0 },
|
|
{ "100BaseT4", 15, 1 },
|
|
{ "100BaseXFullDplx", 14, 1 },
|
|
{ "100BaseXHalfDplx", 13, 1 },
|
|
{ "10MbpsFullDplx", 12, 1 },
|
|
{ "10MbpsHalfDplx", 11, 1 },
|
|
{ "100BaseT2FullDplx", 10, 1 },
|
|
{ "100BaseT2HalfDplx", 9, 1 },
|
|
{ "ExtdStatus", 8, 1 },
|
|
{ "AN_Complete", 5, 1 },
|
|
{ "SGMII_REM_FAULT", 4, 1 },
|
|
{ "AN_Ability", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "JabberDetect", 1, 1 },
|
|
{ "ExtdCapability", 0, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0", 0x38d08, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1", 0x38d0c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_DEV_ABILITY", 0x38d10, 0 },
|
|
{ "NP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "RF2", 13, 1 },
|
|
{ "RF1", 12, 1 },
|
|
{ "PS2", 8, 1 },
|
|
{ "PS1", 7, 1 },
|
|
{ "HD", 6, 1 },
|
|
{ "FD", 5, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_PARTNER_ABILITY", 0x38d14, 0 },
|
|
{ "CuLinkStatus", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "CuDplxStatus", 12, 1 },
|
|
{ "CuSpeed", 10, 2 },
|
|
{ "MAC_PORT_MTIP_SGMII_AN_EXPANSION", 0x38d18, 0 },
|
|
{ "PgRcvd", 1, 1 },
|
|
{ "RealTimePgRcvd", 0, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_DEVICE_NP", 0x38d1c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_PARTNER_NP", 0x38d20, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_EXTENDED_STATUS", 0x38d3c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_LINK_TIMER_LO", 0x38d48, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_LINK_TIMER_HI", 0x38d4c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_IF_MODE", 0x38d50, 0 },
|
|
{ "SGMII_PCS_ENABLE", 5, 1 },
|
|
{ "SGMII_HDUPLEX", 4, 1 },
|
|
{ "SGMII_SPEED", 2, 2 },
|
|
{ "USE_SGMII_AN", 1, 1 },
|
|
{ "SGMII_ENA", 0, 1 },
|
|
{ "MAC_PORT_MTIP_ACT_CTL_SEG", 0x39200, 0 },
|
|
{ "MAC_PORT_MTIP_MODE_CTL_SEG", 0x39204, 0 },
|
|
{ "MAC_PORT_MTIP_TXCLK_CTL_SEG", 0x39208, 0 },
|
|
{ "MAC_PORT_MTIP_TX_PRMBL_CTL_SEG", 0x3920c, 0 },
|
|
{ "MAC_PORT_MTIP_WAN_RS_COL_CNT", 0x39220, 0 },
|
|
{ "MAC_PORT_MTIP_VL_INTVL", 0x39240, 0 },
|
|
{ "VL_INTVL", 1, 1 },
|
|
{ "MAC_PORT_MTIP_MDIO_CFG_STATUS", 0x39600, 0 },
|
|
{ "CLK_DIV", 7, 9 },
|
|
{ "CL45_EN", 6, 1 },
|
|
{ "disable_preamble", 5, 1 },
|
|
{ "mdio_hold_time", 2, 3 },
|
|
{ "mdio_read_err", 1, 1 },
|
|
{ "mdio_busy", 0, 1 },
|
|
{ "MAC_PORT_MTIP_MDIO_COMMAND", 0x39604, 0 },
|
|
{ "read", 15, 1 },
|
|
{ "read_incr", 14, 1 },
|
|
{ "port_addr", 5, 5 },
|
|
{ "dev_addr", 0, 5 },
|
|
{ "MAC_PORT_MTIP_MDIO_DATA", 0x39608, 0 },
|
|
{ "readbusy", 31, 1 },
|
|
{ "data_word", 0, 16 },
|
|
{ "MAC_PORT_MTIP_MDIO_REGADDR", 0x3960c, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_0", 0x39a00, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_1", 0x39a04, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_2", 0x39a08, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_3", 0x39a0c, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_4", 0x39a10, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_5", 0x39a14, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_6", 0x39a18, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_7", 0x39a1c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_CTL", 0x39e00, 0 },
|
|
{ "RESET", 15, 1 },
|
|
{ "LPBK", 14, 1 },
|
|
{ "SPEED_SEL1", 13, 1 },
|
|
{ "LP_MODE", 11, 1 },
|
|
{ "SPEED_SEL0", 6, 1 },
|
|
{ "SPEED", 2, 4 },
|
|
{ "MAC_PORT_MTIP_PCS_STATUS1", 0x39e04, 0 },
|
|
{ "FaultDet", 7, 1 },
|
|
{ "rx_link_status", 2, 1 },
|
|
{ "LoPwrAbl", 1, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_DEVICE_ID0", 0x39e08, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_DEVICE_ID1", 0x39e0c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_SPEED_ABILITY", 0x39e10, 0 },
|
|
{ "100G", 8, 1 },
|
|
{ "40G", 7, 1 },
|
|
{ "10BASE_TL", 1, 1 },
|
|
{ "10G", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_DEVICE_PKG1", 0x39e14, 0 },
|
|
{ "TC", 6, 1 },
|
|
{ "DTEXS", 5, 1 },
|
|
{ "PHYXS", 4, 1 },
|
|
{ "PCS", 3, 1 },
|
|
{ "WIS", 2, 1 },
|
|
{ "PMD_PMA", 1, 1 },
|
|
{ "CL22", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_DEVICE_PKG2", 0x39e18, 0 },
|
|
{ "VendDev2", 15, 1 },
|
|
{ "VendDev1", 14, 1 },
|
|
{ "CL22EXT", 13, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_CTL2", 0x39e1c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_STATUS2", 0x39e20, 0 },
|
|
{ "Device", 15, 1 },
|
|
{ "TxFault", 7, 1 },
|
|
{ "RxFault", 6, 1 },
|
|
{ "100BASE_R", 5, 1 },
|
|
{ "40GBASE_R", 4, 1 },
|
|
{ "10GBASE_T", 3, 1 },
|
|
{ "10GBASE_W", 2, 1 },
|
|
{ "10GBASE_X", 1, 1 },
|
|
{ "10GBASE_R", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_PKG_ID0", 0x39e38, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_PKG_ID1", 0x39e3c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BASER_STATUS1", 0x39e80, 0 },
|
|
{ "RxLinkStatus", 12, 1 },
|
|
{ "RESEREVED", 4, 8 },
|
|
{ "10GPRBS9", 3, 1 },
|
|
{ "10GPRBS31", 2, 1 },
|
|
{ "HiBER", 1, 1 },
|
|
{ "blocklock", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_BASER_STATUS2", 0x39e84, 0 },
|
|
{ "blocklockLL", 15, 1 },
|
|
{ "HiBERLH", 14, 1 },
|
|
{ "HiBERCount", 8, 6 },
|
|
{ "ErrBlkCnt", 0, 8 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_A", 0x39e88, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_A1", 0x39e8c, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_A2", 0x39e90, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_A3", 0x39e94, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_B", 0x39e98, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_B1", 0x39e9c, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_B2", 0x39ea0, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_B3", 0x39ea4, 0 },
|
|
{ "MAC_PORT_MTIP_BASER_TEST_CTRL", 0x39ea8, 0 },
|
|
{ "TXPRBS9", 6, 1 },
|
|
{ "RXPRBS31", 5, 1 },
|
|
{ "TXPRBS31", 4, 1 },
|
|
{ "TxTestPatEn", 3, 1 },
|
|
{ "RxTestPatEn", 2, 1 },
|
|
{ "TestPatSel", 1, 1 },
|
|
{ "DataPatSel", 0, 1 },
|
|
{ "MAC_PORT_MTIP_BASER_TEST_ERR_CNT", 0x39eac, 0 },
|
|
{ "MAC_PORT_MTIP_BER_HIGH_ORDER_CNT", 0x39eb0, 0 },
|
|
{ "MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT", 0x39eb4, 0 },
|
|
{ "HiCountPrsnt", 15, 1 },
|
|
{ "BLOCK_CNT_HI", 0, 14 },
|
|
{ "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1", 0x39ec8, 0 },
|
|
{ "alignstatus", 12, 1 },
|
|
{ "Lane7", 7, 1 },
|
|
{ "Lane6", 6, 1 },
|
|
{ "Lane5", 5, 1 },
|
|
{ "Lane4", 4, 1 },
|
|
{ "Lane3", 3, 1 },
|
|
{ "Lane2", 2, 1 },
|
|
{ "Lane1", 1, 1 },
|
|
{ "Lane0", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2", 0x39ecc, 0 },
|
|
{ "Lane19", 11, 1 },
|
|
{ "Lane18", 10, 1 },
|
|
{ "Lane17", 9, 1 },
|
|
{ "Lane16", 8, 1 },
|
|
{ "Lane15", 7, 1 },
|
|
{ "Lane14", 6, 1 },
|
|
{ "Lane13", 5, 1 },
|
|
{ "Lane12", 4, 1 },
|
|
{ "Lane11", 3, 1 },
|
|
{ "Lane10", 2, 1 },
|
|
{ "Lane9", 1, 1 },
|
|
{ "Lane8", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3", 0x39ed0, 0 },
|
|
{ "AMLOCK7", 7, 1 },
|
|
{ "AMLOCK6", 6, 1 },
|
|
{ "AMLOCK5", 5, 1 },
|
|
{ "AMLOCK4", 4, 1 },
|
|
{ "AMLOCK3", 3, 1 },
|
|
{ "AMLOCK2", 2, 1 },
|
|
{ "AMLOCK1", 1, 1 },
|
|
{ "AMLOCK0", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4", 0x39ed4, 0 },
|
|
{ "AMLOCK19", 11, 1 },
|
|
{ "AMLOCK18", 10, 1 },
|
|
{ "AMLOCK17", 9, 1 },
|
|
{ "AMLOCK16", 8, 1 },
|
|
{ "AMLOCK15", 7, 1 },
|
|
{ "AMLOCK14", 6, 1 },
|
|
{ "AMLOCK13", 5, 1 },
|
|
{ "AMLOCK12", 4, 1 },
|
|
{ "AMLOCK11", 3, 1 },
|
|
{ "AMLOCK10", 2, 1 },
|
|
{ "AMLOCK9", 1, 1 },
|
|
{ "AMLOCK8", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0", 0x39f68, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1", 0x39f6c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2", 0x39f70, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3", 0x39f74, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4", 0x39f78, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5", 0x39f7c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6", 0x39f80, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7", 0x39f84, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8", 0x39f88, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9", 0x39f8c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10", 0x39f90, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11", 0x39f94, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12", 0x39f98, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13", 0x39f9c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14", 0x39fa0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15", 0x39fa4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16", 0x39fa8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17", 0x39fac, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18", 0x39fb0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19", 0x39fb4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_0", 0x39fb8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_1", 0x39fbc, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_2", 0x39fc0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_3", 0x39fc4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_4", 0x39fc8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_5", 0x39fcc, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_6", 0x39fd0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_7", 0x39fd4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_8", 0x39fd8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_9", 0x39fdc, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_10", 0x39fe0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_11", 0x39fe4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_12", 0x39fe8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_13", 0x39fec, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_14", 0x39ff0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_15", 0x39ff4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_16", 0x39ff8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_17", 0x39ffc, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_18", 0x3a000, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_19", 0x3a004, 0 },
|
|
{ "MAC_PORT_BEAN_CTL", 0x3a200, 0 },
|
|
{ "AN_RESET", 15, 1 },
|
|
{ "EXT_NXP_CTRL", 13, 1 },
|
|
{ "BEAN_EN", 12, 1 },
|
|
{ "RESTART_BEAN", 9, 1 },
|
|
{ "MAC_PORT_BEAN_STATUS", 0x3a204, 0 },
|
|
{ "PDF", 9, 1 },
|
|
{ "EXT_NXP_STATUS", 7, 1 },
|
|
{ "PAGE_RCVD", 6, 1 },
|
|
{ "BEAN_COMPLETE", 5, 1 },
|
|
{ "REM_FAULT_STATUS", 4, 1 },
|
|
{ "BEAN_ABILITY", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "LP_BEAN_ABILITY", 0, 1 },
|
|
{ "MAC_PORT_BEAN_ABILITY_0", 0x3a208, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_1", 0x3a20c, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_2", 0x3a210, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_0", 0x3a214, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_1", 0x3a218, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_2", 0x3a21c, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_MS_COUNT", 0x3a220, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_0", 0x3a224, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_BEAN_XNP_1", 0x3a228, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_2", 0x3a22c, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_0", 0x3a230, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_1", 0x3a234, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_2", 0x3a238, 0 },
|
|
{ "MAC_PORT_BEAN_ETH_STATUS", 0x3a23c, 0 },
|
|
{ "100GCR10", 8, 1 },
|
|
{ "40GCR4", 6, 1 },
|
|
{ "40GKR4", 5, 1 },
|
|
{ "FEC", 4, 1 },
|
|
{ "10GKR", 3, 1 },
|
|
{ "10GKX4", 2, 1 },
|
|
{ "1GKX", 1, 1 },
|
|
{ "MAC_PORT_BEAN_CTL_LANE1", 0x3a240, 0 },
|
|
{ "AN_RESET", 15, 1 },
|
|
{ "EXT_NXP_CTRL", 13, 1 },
|
|
{ "BEAN_EN", 12, 1 },
|
|
{ "RESTART_BEAN", 9, 1 },
|
|
{ "MAC_PORT_BEAN_STATUS_LANE1", 0x3a244, 0 },
|
|
{ "PDF", 9, 1 },
|
|
{ "EXT_NXP_STATUS", 7, 1 },
|
|
{ "PAGE_RCVD", 6, 1 },
|
|
{ "BEAN_COMPLETE", 5, 1 },
|
|
{ "REM_FAULT_STATUS", 4, 1 },
|
|
{ "BEAN_ABILITY", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "LP_BEAN_ABILITY", 0, 1 },
|
|
{ "MAC_PORT_BEAN_ABILITY_0_LANE1", 0x3a248, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_1_LANE1", 0x3a24c, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_2_LANE1", 0x3a250, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_0_LANE1", 0x3a254, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_1_LANE1", 0x3a258, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_2_LANE1", 0x3a25c, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_MS_COUNT_LANE1", 0x3a260, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_0_LANE1", 0x3a264, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_BEAN_XNP_1_LANE1", 0x3a268, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_2_LANE1", 0x3a26c, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_0_LANE1", 0x3a270, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_1_LANE1", 0x3a274, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_2_LANE1", 0x3a278, 0 },
|
|
{ "MAC_PORT_BEAN_ETH_STATUS_LANE1", 0x3a27c, 0 },
|
|
{ "100GCR10", 8, 1 },
|
|
{ "40GCR4", 6, 1 },
|
|
{ "40GKR4", 5, 1 },
|
|
{ "FEC", 4, 1 },
|
|
{ "10GKR", 3, 1 },
|
|
{ "10GKX4", 2, 1 },
|
|
{ "1GKX", 1, 1 },
|
|
{ "MAC_PORT_BEAN_CTL_LANE2", 0x3a280, 0 },
|
|
{ "AN_RESET", 15, 1 },
|
|
{ "EXT_NXP_CTRL", 13, 1 },
|
|
{ "BEAN_EN", 12, 1 },
|
|
{ "RESTART_BEAN", 9, 1 },
|
|
{ "MAC_PORT_BEAN_STATUS_LANE2", 0x3a284, 0 },
|
|
{ "PDF", 9, 1 },
|
|
{ "EXT_NXP_STATUS", 7, 1 },
|
|
{ "PAGE_RCVD", 6, 1 },
|
|
{ "BEAN_COMPLETE", 5, 1 },
|
|
{ "REM_FAULT_STATUS", 4, 1 },
|
|
{ "BEAN_ABILITY", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "LP_BEAN_ABILITY", 0, 1 },
|
|
{ "MAC_PORT_BEAN_ABILITY_0_LANE2", 0x3a288, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_1_LANE2", 0x3a28c, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_2_LANE2", 0x3a290, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_0_LANE2", 0x3a294, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_1_LANE2", 0x3a298, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_2_LANE2", 0x3a29c, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_MS_COUNT_LANE2", 0x3a2a0, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_0_LANE2", 0x3a2a4, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_BEAN_XNP_1_LANE2", 0x3a2a8, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_2_LANE2", 0x3a2ac, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_0_LANE2", 0x3a2b0, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_1_LANE2", 0x3a2b4, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_2_LANE2", 0x3a2b8, 0 },
|
|
{ "MAC_PORT_BEAN_ETH_STATUS_LANE2", 0x3a2bc, 0 },
|
|
{ "100GCR10", 8, 1 },
|
|
{ "40GCR4", 6, 1 },
|
|
{ "40GKR4", 5, 1 },
|
|
{ "FEC", 4, 1 },
|
|
{ "10GKR", 3, 1 },
|
|
{ "10GKX4", 2, 1 },
|
|
{ "1GKX", 1, 1 },
|
|
{ "MAC_PORT_BEAN_CTL_LANE3", 0x3a2c0, 0 },
|
|
{ "AN_RESET", 15, 1 },
|
|
{ "EXT_NXP_CTRL", 13, 1 },
|
|
{ "BEAN_EN", 12, 1 },
|
|
{ "RESTART_BEAN", 9, 1 },
|
|
{ "MAC_PORT_BEAN_STATUS_LANE3", 0x3a2c4, 0 },
|
|
{ "PDF", 9, 1 },
|
|
{ "EXT_NXP_STATUS", 7, 1 },
|
|
{ "PAGE_RCVD", 6, 1 },
|
|
{ "BEAN_COMPLETE", 5, 1 },
|
|
{ "REM_FAULT_STATUS", 4, 1 },
|
|
{ "BEAN_ABILITY", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "LP_BEAN_ABILITY", 0, 1 },
|
|
{ "MAC_PORT_BEAN_ABILITY_0_LANE3", 0x3a2c8, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_1_LANE3", 0x3a2cc, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_2_LANE3", 0x3a2d0, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_0_LANE3", 0x3a2d4, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_1_LANE3", 0x3a2d8, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_2_LANE3", 0x3a2dc, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_MS_COUNT_LANE3", 0x3a2e0, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_0_LANE3", 0x3a2e4, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_BEAN_XNP_1_LANE3", 0x3a2e8, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_2_LANE3", 0x3a2ec, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_0_LANE3", 0x3a2f0, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_1_LANE3", 0x3a2f4, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_2_LANE3", 0x3a2f8, 0 },
|
|
{ "MAC_PORT_BEAN_ETH_STATUS_LANE3", 0x3a2fc, 0 },
|
|
{ "100GCR10", 8, 1 },
|
|
{ "40GCR4", 6, 1 },
|
|
{ "40GKR4", 5, 1 },
|
|
{ "FEC", 4, 1 },
|
|
{ "10GKR", 3, 1 },
|
|
{ "10GKX4", 2, 1 },
|
|
{ "1GKX", 1, 1 },
|
|
{ "MAC_PORT_FEC_KR_CONTROL", 0x3a600, 0 },
|
|
{ "enable_tr", 1, 1 },
|
|
{ "restart_tr", 0, 1 },
|
|
{ "MAC_PORT_FEC_KR_STATUS", 0x3a604, 0 },
|
|
{ "fecKRsigdet", 15, 1 },
|
|
{ "train_fail", 3, 1 },
|
|
{ "startup_status", 2, 1 },
|
|
{ "frame_lock", 1, 1 },
|
|
{ "rx_status", 0, 1 },
|
|
{ "MAC_PORT_FEC_KR_LP_COEFF", 0x3a608, 0 },
|
|
{ "Preset", 13, 1 },
|
|
{ "Initialize", 12, 1 },
|
|
{ "CP1_UPD", 4, 2 },
|
|
{ "C0_UPD", 2, 2 },
|
|
{ "CN1_UPD", 0, 2 },
|
|
{ "MAC_PORT_FEC_KR_LP_STAT", 0x3a60c, 0 },
|
|
{ "rx_ready", 15, 1 },
|
|
{ "CP1_STAT", 4, 2 },
|
|
{ "C0_STAT", 2, 2 },
|
|
{ "CN1_STAT", 0, 2 },
|
|
{ "MAC_PORT_FEC_KR_LD_COEFF", 0x3a610, 0 },
|
|
{ "Preset", 13, 1 },
|
|
{ "Initialize", 12, 1 },
|
|
{ "CP1_UPD", 4, 2 },
|
|
{ "C0_UPD", 2, 2 },
|
|
{ "CN1_UPD", 0, 2 },
|
|
{ "MAC_PORT_FEC_KR_LD_STAT", 0x3a614, 0 },
|
|
{ "rx_ready", 15, 1 },
|
|
{ "CP1_STAT", 4, 2 },
|
|
{ "C0_STAT", 2, 2 },
|
|
{ "CN1_STAT", 0, 2 },
|
|
{ "MAC_PORT_FEC_ABILITY", 0x3a618, 0 },
|
|
{ "fec_ind_ability", 1, 1 },
|
|
{ "ability", 0, 1 },
|
|
{ "MAC_PORT_FEC_CONTROL", 0x3a61c, 0 },
|
|
{ "fec_en_err_ind", 1, 1 },
|
|
{ "fec_en", 0, 1 },
|
|
{ "MAC_PORT_FEC_STATUS", 0x3a620, 0 },
|
|
{ "FEC_LOCKED_100", 1, 1 },
|
|
{ "FEC_LOCKED", 0, 1 },
|
|
{ "MAC_PORT_FEC_CERR_CNT_0", 0x3a624, 0 },
|
|
{ "MAC_PORT_FEC_CERR_CNT_1", 0x3a628, 0 },
|
|
{ "MAC_PORT_FEC_NCERR_CNT_0", 0x3a62c, 0 },
|
|
{ "MAC_PORT_FEC_NCERR_CNT_1", 0x3a630, 0 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ", 0x3aa00, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT", 0x3aa04, 0 },
|
|
{ "T5_AE0_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE0_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE0_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE0_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ", 0x3aa08, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT", 0x3aa0c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE", 0x3aa10, 0 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL", 0x3aa14, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL", 0x3aa18, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE", 0x3aa1c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ_1", 0x3aa20, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT_1", 0x3aa24, 0 },
|
|
{ "T5_AE1_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE1_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE1_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE1_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ_1", 0x3aa28, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT_1", 0x3aa2c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE_1", 0x3aa30, 0 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL_1", 0x3aa34, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL_1", 0x3aa38, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE_1", 0x3aa3c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ_2", 0x3aa40, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT_2", 0x3aa44, 0 },
|
|
{ "T5_AE2_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE2_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE2_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE2_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ_2", 0x3aa48, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT_2", 0x3aa4c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE_2", 0x3aa50, 0 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL_2", 0x3aa54, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL_2", 0x3aa58, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE_2", 0x3aa5c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ_3", 0x3aa60, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT_3", 0x3aa64, 0 },
|
|
{ "T5_AE3_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE3_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE3_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE3_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ_3", 0x3aa68, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT_3", 0x3aa6c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE_3", 0x3aa70, 0 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL_3", 0x3aa74, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL_3", 0x3aa78, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE_3", 0x3aa7c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_TX_DIS", 0x3aa80, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL", 0x3aa84, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET", 0x3aa88, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS", 0x3aa8c, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AE_TX_DIS_1", 0x3aa90, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL_1", 0x3aa94, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET_1", 0x3aa98, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS_1", 0x3aa9c, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AE_TX_DIS_2", 0x3aaa0, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL_2", 0x3aaa4, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET_2", 0x3aaa8, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS_2", 0x3aaac, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AE_TX_DIS_3", 0x3aab0, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL_3", 0x3aab4, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET_3", 0x3aab8, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS_3", 0x3aabc, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_0", 0x3ab00, 0 },
|
|
{ "EN_HOLD_FAIL", 14, 1 },
|
|
{ "INIT_METH", 12, 2 },
|
|
{ "CE_DECS", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_C1", 5, 1 },
|
|
{ "EN_MAX_ST", 4, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0", 0x3ab04, 0 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_0", 0x3ab08, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0", 0x3ab0c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT6", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_0", 0x3ab10, 0 },
|
|
{ "AET_STAT", 9, 4 },
|
|
{ "NEU_STATE", 5, 4 },
|
|
{ "CTRL_STATE", 0, 5 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_1", 0x3ab20, 0 },
|
|
{ "EN_HOLD_FAIL", 14, 1 },
|
|
{ "INIT_METH", 12, 2 },
|
|
{ "CE_DECS", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_C1", 5, 1 },
|
|
{ "EN_MAX_ST", 4, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1", 0x3ab24, 0 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_1", 0x3ab28, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1", 0x3ab2c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT6", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_1", 0x3ab30, 0 },
|
|
{ "AET_STAT", 9, 4 },
|
|
{ "NEU_STATE", 5, 4 },
|
|
{ "CTRL_STATE", 0, 5 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_2", 0x3ab40, 0 },
|
|
{ "EN_HOLD_FAIL", 14, 1 },
|
|
{ "INIT_METH", 12, 2 },
|
|
{ "CE_DECS", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_C1", 5, 1 },
|
|
{ "EN_MAX_ST", 4, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2", 0x3ab44, 0 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_2", 0x3ab48, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2", 0x3ab4c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT6", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_2", 0x3ab50, 0 },
|
|
{ "AET_STAT", 9, 4 },
|
|
{ "NEU_STATE", 5, 4 },
|
|
{ "CTRL_STATE", 0, 5 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_3", 0x3ab60, 0 },
|
|
{ "EN_HOLD_FAIL", 14, 1 },
|
|
{ "INIT_METH", 12, 2 },
|
|
{ "CE_DECS", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_C1", 5, 1 },
|
|
{ "EN_MAX_ST", 4, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3", 0x3ab64, 0 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_3", 0x3ab68, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3", 0x3ab6c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT6", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_3", 0x3ab70, 0 },
|
|
{ "AET_STAT", 9, 4 },
|
|
{ "NEU_STATE", 5, 4 },
|
|
{ "CTRL_STATE", 0, 5 },
|
|
{ "MAC_PORT_ANALOG_TEST_MUX", 0x3b814, 0 },
|
|
{ "MAC_PORT_BANDGAP_CONTROL", 0x3b82c, 0 },
|
|
{ "MAC_PORT_RESISTOR_CALIBRATION_CONTROL", 0x3b880, 0 },
|
|
{ "RCCTL1", 5, 1 },
|
|
{ "RCCTL0", 4, 1 },
|
|
{ "RCAMP1", 3, 1 },
|
|
{ "RCAMP0", 2, 1 },
|
|
{ "RCAMPEN", 1, 1 },
|
|
{ "RCRST", 0, 1 },
|
|
{ "MAC_PORT_RESISTOR_CALIBRATION_STATUS_1", 0x3b884, 0 },
|
|
{ "RCERR", 1, 1 },
|
|
{ "RCCOMP", 0, 1 },
|
|
{ "MAC_PORT_RESISTOR_CALIBRATION_STATUS_2", 0x3b888, 0 },
|
|
{ "MAC_PORT_RESISTOR_CALIBRATION_STATUS_3", 0x3b88c, 0 },
|
|
{ "MAC_PORT_MACRO_TEST_CONTROL_6", 0x3b8e8, 0 },
|
|
{ "LBIST", 7, 1 },
|
|
{ "LOGICTEST", 6, 1 },
|
|
{ "MAVDHI", 5, 1 },
|
|
{ "AUXEN", 4, 1 },
|
|
{ "JTAGMD", 3, 1 },
|
|
{ "RXACMODE", 2, 1 },
|
|
{ "HSSACJPC", 1, 1 },
|
|
{ "HSSACJAC", 0, 1 },
|
|
{ "MAC_PORT_MACRO_TEST_CONTROL_5", 0x3b8ec, 0 },
|
|
{ "REFVALIDD", 6, 1 },
|
|
{ "REFVALIDC", 5, 1 },
|
|
{ "REFVALIDB", 4, 1 },
|
|
{ "REFVALIDA", 3, 1 },
|
|
{ "REFSELRESET", 2, 1 },
|
|
{ "SOFTRESET", 1, 1 },
|
|
{ "MACROTEST", 0, 1 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0", 0x3bb00, 0 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1", 0x3bb04, 0 },
|
|
{ "LDET", 4, 1 },
|
|
{ "CCERR", 3, 1 },
|
|
{ "CCCMP", 2, 1 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2", 0x3bb08, 0 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3", 0x3bb0c, 0 },
|
|
{ "FMIN", 3, 1 },
|
|
{ "FMAX", 2, 1 },
|
|
{ "CVHOLD", 1, 1 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4", 0x3bb10, 0 },
|
|
{ "CMETH", 2, 1 },
|
|
{ "RECAL", 1, 1 },
|
|
{ "CCLD", 0, 1 },
|
|
{ "MAC_PORT_PLLA_CHARGE_PUMP_CONTROL", 0x3bb28, 0 },
|
|
{ "MAC_PORT_PLLA_PCLK_CONTROL", 0x3bb3c, 0 },
|
|
{ "SPEDIV", 3, 5 },
|
|
{ "PCKSEL", 0, 3 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL", 0x3bb40, 0 },
|
|
{ "EMIL", 2, 1 },
|
|
{ "EMID", 1, 1 },
|
|
{ "EMIS", 0, 1 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1", 0x3bb44, 0 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2", 0x3bb48, 0 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3", 0x3bb4c, 0 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4", 0x3bb50, 0 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_4", 0x3bbf0, 0 },
|
|
{ "VBST", 1, 3 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_3", 0x3bbf4, 0 },
|
|
{ "RESYNC", 6, 1 },
|
|
{ "RXCLKSEL", 5, 1 },
|
|
{ "FRCBAND", 4, 1 },
|
|
{ "PLLBYP", 3, 1 },
|
|
{ "PDWNP", 2, 1 },
|
|
{ "VCOSEL", 1, 1 },
|
|
{ "DIVSEL8", 0, 1 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_2", 0x3bbf8, 0 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_1", 0x3bbfc, 0 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0", 0x3bc00, 0 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1", 0x3bc04, 0 },
|
|
{ "LDET", 4, 1 },
|
|
{ "CCERR", 3, 1 },
|
|
{ "CCCMP", 2, 1 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2", 0x3bc08, 0 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3", 0x3bc0c, 0 },
|
|
{ "FMIN", 3, 1 },
|
|
{ "FMAX", 2, 1 },
|
|
{ "CVHOLD", 1, 1 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4", 0x3bc10, 0 },
|
|
{ "CMETH", 2, 1 },
|
|
{ "RECAL", 1, 1 },
|
|
{ "CCLD", 0, 1 },
|
|
{ "MAC_PORT_PLLB_CHARGE_PUMP_CONTROL", 0x3bc28, 0 },
|
|
{ "MAC_PORT_PLLB_PCLK_CONTROL", 0x3bc3c, 0 },
|
|
{ "SPEDIV", 3, 5 },
|
|
{ "PCKSEL", 0, 3 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL", 0x3bc40, 0 },
|
|
{ "EMIL", 2, 1 },
|
|
{ "EMID", 1, 1 },
|
|
{ "EMIS", 0, 1 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1", 0x3bc44, 0 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2", 0x3bc48, 0 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3", 0x3bc4c, 0 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4", 0x3bc50, 0 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_4", 0x3bcf0, 0 },
|
|
{ "VBST", 1, 3 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_3", 0x3bcf4, 0 },
|
|
{ "RESYNC", 6, 1 },
|
|
{ "RXCLKSEL", 5, 1 },
|
|
{ "FRCBAND", 4, 1 },
|
|
{ "PLLBYP", 3, 1 },
|
|
{ "PDWNP", 2, 1 },
|
|
{ "VCOSEL", 1, 1 },
|
|
{ "DIVSEL8", 0, 1 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_2", 0x3bcf8, 0 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_1", 0x3bcfc, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE", 0x3b000, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL", 0x3b004, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL", 0x3b008, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL", 0x3b00c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3b010, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3b014, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3b018, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3b01c, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT", 0x3b020, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT", 0x3b024, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT", 0x3b028, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE", 0x3b030, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_POLARITY", 0x3b034, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3b038, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3b03c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3b040, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3b044, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3b048, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3b060, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3b064, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3b068, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3b070, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3b074, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3b078, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3b07c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3b080, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3b084, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3b088, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL", 0x3b08c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE", 0x3b090, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED", 0x3b094, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT", 0x3b098, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL", 0x3b09c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3b0f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3b0f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3b0f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3b0fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x38000, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x38008, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x38010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x38018, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x38020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x38028, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x38030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x38038, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x38040, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE", 0x3b100, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL", 0x3b104, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL", 0x3b108, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL", 0x3b10c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3b110, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3b114, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3b118, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3b11c, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT", 0x3b120, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT", 0x3b124, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT", 0x3b128, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE", 0x3b130, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_POLARITY", 0x3b134, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3b138, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3b13c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3b140, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3b144, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3b148, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3b160, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3b164, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3b168, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3b170, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3b174, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3b178, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3b17c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3b180, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3b184, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3b188, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL", 0x3b18c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE", 0x3b190, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED", 0x3b194, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT", 0x3b198, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL", 0x3b19c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3b1f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3b1f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3b1f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3b1fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x38000, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x38008, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x38010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x38018, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x38020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x38028, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x38030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x38038, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x38040, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE", 0x3b400, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL", 0x3b404, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL", 0x3b408, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL", 0x3b40c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3b410, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3b414, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3b418, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3b41c, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT", 0x3b420, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT", 0x3b424, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT", 0x3b428, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE", 0x3b430, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_POLARITY", 0x3b434, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3b438, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3b43c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3b440, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3b444, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3b448, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3b460, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3b464, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3b468, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3b470, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3b474, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3b478, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3b47c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3b480, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3b484, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3b488, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL", 0x3b48c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE", 0x3b490, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED", 0x3b494, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT", 0x3b498, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL", 0x3b49c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3b4f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3b4f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3b4f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3b4fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x38000, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x38008, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x38010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x38018, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x38020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x38028, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x38030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x38038, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x38040, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE", 0x3b500, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL", 0x3b504, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL", 0x3b508, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL", 0x3b50c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3b510, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3b514, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3b518, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3b51c, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT", 0x3b520, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT", 0x3b524, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT", 0x3b528, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE", 0x3b530, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_POLARITY", 0x3b534, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3b538, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3b53c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3b540, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3b544, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3b548, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3b560, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3b564, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3b568, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3b570, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3b574, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3b578, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3b57c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3b580, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3b584, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3b588, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL", 0x3b58c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE", 0x3b590, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED", 0x3b594, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT", 0x3b598, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL", 0x3b59c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3b5f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3b5f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3b5f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3b5fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x38000, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x38008, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x38010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x38018, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x38020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x38028, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x38030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x38038, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x38040, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE", 0x3b900, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL", 0x3b904, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL", 0x3b908, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL", 0x3b90c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3b910, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3b914, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3b918, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3b91c, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT", 0x3b920, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT", 0x3b924, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT", 0x3b928, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE", 0x3b930, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY", 0x3b934, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3b938, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3b93c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3b940, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3b944, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3b948, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3b960, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3b964, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3b968, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3b970, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3b974, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3b978, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3b97c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3b980, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3b984, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3b988, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL", 0x3b98c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE", 0x3b990, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED", 0x3b994, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT", 0x3b998, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL", 0x3b99c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3b9f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3b9f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3b9f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3b9fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x38000, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x38008, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x38010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x38018, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x38020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x38028, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x38030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x38038, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x38040, 0 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE", 0x3b200, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL", 0x3b204, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL", 0x3b208, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL", 0x3b20c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1", 0x3b210, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2", 0x3b214, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3b218, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3b21c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_CONTROL", 0x3b220, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1", 0x3b224, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2", 0x3b228, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1", 0x3b22c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2", 0x3b230, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3", 0x3b234, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1", 0x3b238, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3", 0x3b240, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN", 0x3b248, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ", 0x3b24c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL", 0x3b250, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3b25c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3b260, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3b264, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3b270, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC", 0x3b274, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS", 0x3b278, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1", 0x3b27c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2", 0x3b280, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2", 0x3b284, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2", 0x3b288, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4", 0x3b28c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4", 0x3b290, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET", 0x3b294, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL", 0x3b298, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL", 0x3b29c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3b2a0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET", 0x3b2a4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL", 0x3b2a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS", 0x3b2ac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3b2b0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3b2b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3b2b8, 0 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_TAP_ENABLE", 0x3b2c0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1", 0x3b2c4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H2", 0x3b2c8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H3", 0x3b2cc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H4", 0x3b2d0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H5", 0x3b2d4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H6_AND_H7", 0x3b2d8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H8_AND_H9", 0x3b2dc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H10_AND_H11", 0x3b2e0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H12", 0x3b2e4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2", 0x3b2f8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1", 0x3b2fc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE", 0x3b300, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL", 0x3b304, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL", 0x3b308, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL", 0x3b30c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1", 0x3b310, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2", 0x3b314, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3b318, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3b31c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_CONTROL", 0x3b320, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1", 0x3b324, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2", 0x3b328, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1", 0x3b32c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2", 0x3b330, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3", 0x3b334, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1", 0x3b338, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3", 0x3b340, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN", 0x3b348, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ", 0x3b34c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL", 0x3b350, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3b35c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3b360, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3b364, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3b370, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC", 0x3b374, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS", 0x3b378, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1", 0x3b37c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2", 0x3b380, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2", 0x3b384, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2", 0x3b388, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4", 0x3b38c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4", 0x3b390, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET", 0x3b394, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL", 0x3b398, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL", 0x3b39c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3b3a0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET", 0x3b3a4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL", 0x3b3a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS", 0x3b3ac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3b3b0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3b3b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3b3b8, 0 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_TAP_ENABLE", 0x3b3c0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1", 0x3b3c4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H2", 0x3b3c8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H3", 0x3b3cc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H4", 0x3b3d0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H5", 0x3b3d4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H6_AND_H7", 0x3b3d8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H8_AND_H9", 0x3b3dc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H10_AND_H11", 0x3b3e0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H12", 0x3b3e4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2", 0x3b3f8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1", 0x3b3fc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE", 0x3b600, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL", 0x3b604, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL", 0x3b608, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL", 0x3b60c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1", 0x3b610, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2", 0x3b614, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3b618, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3b61c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_CONTROL", 0x3b620, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1", 0x3b624, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2", 0x3b628, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1", 0x3b62c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2", 0x3b630, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3", 0x3b634, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1", 0x3b638, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3", 0x3b640, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN", 0x3b648, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ", 0x3b64c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL", 0x3b650, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3b65c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3b660, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3b664, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3b670, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC", 0x3b674, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS", 0x3b678, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1", 0x3b67c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2", 0x3b680, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2", 0x3b684, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2", 0x3b688, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4", 0x3b68c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4", 0x3b690, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET", 0x3b694, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL", 0x3b698, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL", 0x3b69c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3b6a0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET", 0x3b6a4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL", 0x3b6a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS", 0x3b6ac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3b6b0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3b6b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3b6b8, 0 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_TAP_ENABLE", 0x3b6c0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1", 0x3b6c4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H2", 0x3b6c8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H3", 0x3b6cc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H4", 0x3b6d0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H5", 0x3b6d4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H6_AND_H7", 0x3b6d8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H8_AND_H9", 0x3b6dc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H10_AND_H11", 0x3b6e0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H12", 0x3b6e4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2", 0x3b6f8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1", 0x3b6fc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE", 0x3b700, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL", 0x3b704, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL", 0x3b708, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL", 0x3b70c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1", 0x3b710, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2", 0x3b714, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3b718, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3b71c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_CONTROL", 0x3b720, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1", 0x3b724, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2", 0x3b728, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1", 0x3b72c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2", 0x3b730, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3", 0x3b734, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1", 0x3b738, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3", 0x3b740, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN", 0x3b748, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ", 0x3b74c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL", 0x3b750, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3b75c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3b760, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3b764, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3b770, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC", 0x3b774, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS", 0x3b778, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1", 0x3b77c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2", 0x3b780, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2", 0x3b784, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2", 0x3b788, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4", 0x3b78c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4", 0x3b790, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET", 0x3b794, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL", 0x3b798, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL", 0x3b79c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3b7a0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET", 0x3b7a4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL", 0x3b7a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS", 0x3b7ac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3b7b0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3b7b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3b7b8, 0 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_TAP_ENABLE", 0x3b7c0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1", 0x3b7c4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H2", 0x3b7c8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H3", 0x3b7cc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H4", 0x3b7d0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H5", 0x3b7d4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H6_AND_H7", 0x3b7d8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H8_AND_H9", 0x3b7dc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H10_AND_H11", 0x3b7e0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H12", 0x3b7e4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2", 0x3b7f8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1", 0x3b7fc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE", 0x3ba00, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL", 0x3ba04, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL", 0x3ba08, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL", 0x3ba0c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1", 0x3ba10, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2", 0x3ba14, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3ba18, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3ba1c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_CONTROL", 0x3ba20, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1", 0x3ba24, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2", 0x3ba28, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1", 0x3ba2c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2", 0x3ba30, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3", 0x3ba34, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1", 0x3ba38, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3", 0x3ba40, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN", 0x3ba48, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ", 0x3ba4c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL", 0x3ba50, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3ba5c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3ba60, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3ba64, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3ba70, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC", 0x3ba74, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS", 0x3ba78, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1", 0x3ba7c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2", 0x3ba80, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2", 0x3ba84, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2", 0x3ba88, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4", 0x3ba8c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4", 0x3ba90, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET", 0x3ba94, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL", 0x3ba98, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL", 0x3ba9c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3baa0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET", 0x3baa4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL", 0x3baa8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS", 0x3baac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3bab0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3bab4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3bab8, 0 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE", 0x3bac0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1", 0x3bac4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H2", 0x3bac8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H3", 0x3bacc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H4", 0x3bad0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H5", 0x3bad4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7", 0x3bad8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9", 0x3badc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11", 0x3bae0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H12", 0x3bae4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2", 0x3baf8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1", 0x3bafc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_CFG", 0x3c800, 0 },
|
|
{ "MAC_Clk_Sel", 29, 3 },
|
|
{ "SinkTx", 27, 1 },
|
|
{ "SinkTxOnLinkDown", 26, 1 },
|
|
{ "LoopNoFwd", 24, 1 },
|
|
{ "Smux_Rx_Loop", 19, 1 },
|
|
{ "Rx_Lane_Swap", 18, 1 },
|
|
{ "Tx_Lane_Swap", 17, 1 },
|
|
{ "Signal_Det", 14, 1 },
|
|
{ "SmuxTxSel", 9, 1 },
|
|
{ "SmuxRxSel", 8, 1 },
|
|
{ "PortSpeed", 4, 2 },
|
|
{ "Rx_Byte_Swap", 3, 1 },
|
|
{ "Tx_Byte_Swap", 2, 1 },
|
|
{ "Port_Sel", 0, 1 },
|
|
{ "MAC_PORT_RESET_CTRL", 0x3c804, 0 },
|
|
{ "TWGDSK_HSSC16B", 31, 1 },
|
|
{ "EEE_RESET", 30, 1 },
|
|
{ "PTP_TIMER", 29, 1 },
|
|
{ "MtipRefReset", 28, 1 },
|
|
{ "MtipTxffReset", 27, 1 },
|
|
{ "MtipRxffReset", 26, 1 },
|
|
{ "MtipRegReset", 25, 1 },
|
|
{ "AEC3Reset", 23, 1 },
|
|
{ "AEC2Reset", 22, 1 },
|
|
{ "AEC1Reset", 21, 1 },
|
|
{ "AEC0Reset", 20, 1 },
|
|
{ "AET3Reset", 19, 1 },
|
|
{ "AET2Reset", 18, 1 },
|
|
{ "AET1Reset", 17, 1 },
|
|
{ "AET0Reset", 16, 1 },
|
|
{ "TXIF_Reset", 12, 1 },
|
|
{ "RXIF_Reset", 11, 1 },
|
|
{ "AuxExt_Reset", 10, 1 },
|
|
{ "MtipSd3TxRst", 9, 1 },
|
|
{ "MtipSd2TxRst", 8, 1 },
|
|
{ "MtipSd1TxRst", 7, 1 },
|
|
{ "MtipSd0TxRst", 6, 1 },
|
|
{ "MtipSd3RxRst", 5, 1 },
|
|
{ "MtipSd2RxRst", 4, 1 },
|
|
{ "MtipSd1RxRst", 3, 1 },
|
|
{ "WOL_Reset", 2, 1 },
|
|
{ "MtipSd0RxRst", 1, 1 },
|
|
{ "HSS_Reset", 0, 1 },
|
|
{ "MAC_PORT_LED_CFG", 0x3c808, 0 },
|
|
{ "Led1_Cfg", 5, 3 },
|
|
{ "Led1_Polarity_Inv", 4, 1 },
|
|
{ "Led0_Cfg", 1, 3 },
|
|
{ "Led0_Polarity_Inv", 0, 1 },
|
|
{ "MAC_PORT_LED_COUNTHI", 0x3c80c, 0 },
|
|
{ "MAC_PORT_LED_COUNTLO", 0x3c810, 0 },
|
|
{ "MAC_PORT_CFG3", 0x3c814, 0 },
|
|
{ "FPGA_PTP_PORT", 26, 2 },
|
|
{ "FCSDisCtrl", 25, 1 },
|
|
{ "SigDetCtrl", 24, 1 },
|
|
{ "tx_lane", 23, 1 },
|
|
{ "rx_lane", 22, 1 },
|
|
{ "se_clr", 21, 1 },
|
|
{ "an_ena", 17, 4 },
|
|
{ "sd_rx_clk_ena", 13, 4 },
|
|
{ "sd_tx_clk_ena", 9, 4 },
|
|
{ "SGMIISEL", 8, 1 },
|
|
{ "HSSPLLSEL", 4, 4 },
|
|
{ "HSSC16C20SEL", 0, 4 },
|
|
{ "MAC_PORT_CFG2", 0x3c818, 0 },
|
|
{ "Rx_Polarity_Inv", 28, 4 },
|
|
{ "Tx_Polarity_Inv", 24, 4 },
|
|
{ "InstanceNum", 22, 2 },
|
|
{ "StopOnPerr", 21, 1 },
|
|
{ "PatEn", 18, 1 },
|
|
{ "MagicEn", 17, 1 },
|
|
{ "T5_AEC_PMA_TX_READY", 4, 4 },
|
|
{ "T5_AEC_PMA_RX_READY", 0, 4 },
|
|
{ "MAC_PORT_PKT_COUNT", 0x3c81c, 0 },
|
|
{ "tx_sop_count", 24, 8 },
|
|
{ "tx_eop_count", 16, 8 },
|
|
{ "rx_sop_count", 8, 8 },
|
|
{ "rx_eop_count", 0, 8 },
|
|
{ "MAC_PORT_CFG4", 0x3c820, 0 },
|
|
{ "AEC3_RX_WIDTH", 14, 2 },
|
|
{ "AEC2_RX_WIDTH", 12, 2 },
|
|
{ "AEC1_RX_WIDTH", 10, 2 },
|
|
{ "AEC0_RX_WIDTH", 8, 2 },
|
|
{ "AEC3_TX_WIDTH", 6, 2 },
|
|
{ "AEC2_TX_WIDTH", 4, 2 },
|
|
{ "AEC1_TX_WIDTH", 2, 2 },
|
|
{ "AEC0_TX_WIDTH", 0, 2 },
|
|
{ "MAC_PORT_MAGIC_MACID_LO", 0x3c824, 0 },
|
|
{ "MAC_PORT_MAGIC_MACID_HI", 0x3c828, 0 },
|
|
{ "MAC_PORT_LINK_STATUS", 0x3c834, 0 },
|
|
{ "an_done", 6, 1 },
|
|
{ "align_done", 5, 1 },
|
|
{ "block_lock", 4, 1 },
|
|
{ "remflt", 3, 1 },
|
|
{ "locflt", 2, 1 },
|
|
{ "linkup", 1, 1 },
|
|
{ "linkdn", 0, 1 },
|
|
{ "MAC_PORT_EPIO_DATA0", 0x3c8c0, 0 },
|
|
{ "MAC_PORT_EPIO_DATA1", 0x3c8c4, 0 },
|
|
{ "MAC_PORT_EPIO_DATA2", 0x3c8c8, 0 },
|
|
{ "MAC_PORT_EPIO_DATA3", 0x3c8cc, 0 },
|
|
{ "MAC_PORT_EPIO_OP", 0x3c8d0, 0 },
|
|
{ "Busy", 31, 1 },
|
|
{ "Write", 8, 1 },
|
|
{ "Address", 0, 8 },
|
|
{ "MAC_PORT_WOL_STATUS", 0x3c8d4, 0 },
|
|
{ "MagicDetected", 31, 1 },
|
|
{ "PatDetected", 30, 1 },
|
|
{ "ClearMagic", 4, 1 },
|
|
{ "ClearMatch", 3, 1 },
|
|
{ "MatchedFilter", 0, 3 },
|
|
{ "MAC_PORT_INT_EN", 0x3c8d8, 0 },
|
|
{ "tx_ts_avail", 29, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "an_page_rcvd", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "MAC_PORT_INT_CAUSE", 0x3c8dc, 0 },
|
|
{ "tx_ts_avail", 29, 1 },
|
|
{ "PatDetWake", 26, 1 },
|
|
{ "MagicWake", 25, 1 },
|
|
{ "SigDetChg", 24, 1 },
|
|
{ "AE_Train_Local", 22, 1 },
|
|
{ "HSSPLL_LOCK", 21, 1 },
|
|
{ "HSSPRT_READY", 20, 1 },
|
|
{ "AutoNeg_Done", 19, 1 },
|
|
{ "PCS_Link_Good", 12, 1 },
|
|
{ "PCS_Link_Fail", 11, 1 },
|
|
{ "RxFifoOverFlow", 10, 1 },
|
|
{ "HSSPRBSErr", 9, 1 },
|
|
{ "HSSEyeQual", 8, 1 },
|
|
{ "RemoteFault", 7, 1 },
|
|
{ "LocalFault", 6, 1 },
|
|
{ "MAC_Link_Down", 5, 1 },
|
|
{ "MAC_Link_Up", 4, 1 },
|
|
{ "an_page_rcvd", 2, 1 },
|
|
{ "TxFifo_prty_err", 1, 1 },
|
|
{ "RxFifo_prty_err", 0, 1 },
|
|
{ "MAC_PORT_PERR_INT_EN", 0x3c8e0, 0 },
|
|
{ "Perr_pkt_ram", 24, 1 },
|
|
{ "Perr_mask_ram", 23, 1 },
|
|
{ "Perr_crc_ram", 22, 1 },
|
|
{ "rx_dff_seg0", 21, 1 },
|
|
{ "rx_sff_seg0", 20, 1 },
|
|
{ "rx_dff_mac10", 19, 1 },
|
|
{ "rx_sff_mac10", 18, 1 },
|
|
{ "tx_dff_seg0", 17, 1 },
|
|
{ "tx_sff_seg0", 16, 1 },
|
|
{ "tx_dff_mac10", 15, 1 },
|
|
{ "tx_sff_mac10", 14, 1 },
|
|
{ "rx_stats", 13, 1 },
|
|
{ "tx_stats", 12, 1 },
|
|
{ "Perr3_rx_mix", 11, 1 },
|
|
{ "Perr3_rx_sd", 10, 1 },
|
|
{ "Perr3_tx", 9, 1 },
|
|
{ "Perr2_rx_mix", 8, 1 },
|
|
{ "Perr2_rx_sd", 7, 1 },
|
|
{ "Perr2_tx", 6, 1 },
|
|
{ "Perr1_rx_mix", 5, 1 },
|
|
{ "Perr1_rx_sd", 4, 1 },
|
|
{ "Perr1_tx", 3, 1 },
|
|
{ "Perr0_rx_mix", 2, 1 },
|
|
{ "Perr0_rx_sd", 1, 1 },
|
|
{ "Perr0_tx", 0, 1 },
|
|
{ "MAC_PORT_PERR_INT_CAUSE", 0x3c8e4, 0 },
|
|
{ "Perr_pkt_ram", 24, 1 },
|
|
{ "Perr_mask_ram", 23, 1 },
|
|
{ "Perr_crc_ram", 22, 1 },
|
|
{ "rx_dff_seg0", 21, 1 },
|
|
{ "rx_sff_seg0", 20, 1 },
|
|
{ "rx_dff_mac10", 19, 1 },
|
|
{ "rx_sff_mac10", 18, 1 },
|
|
{ "tx_dff_seg0", 17, 1 },
|
|
{ "tx_sff_seg0", 16, 1 },
|
|
{ "tx_dff_mac10", 15, 1 },
|
|
{ "tx_sff_mac10", 14, 1 },
|
|
{ "rx_stats", 13, 1 },
|
|
{ "tx_stats", 12, 1 },
|
|
{ "Perr3_rx_mix", 11, 1 },
|
|
{ "Perr3_rx_sd", 10, 1 },
|
|
{ "Perr3_tx", 9, 1 },
|
|
{ "Perr2_rx_mix", 8, 1 },
|
|
{ "Perr2_rx_sd", 7, 1 },
|
|
{ "Perr2_tx", 6, 1 },
|
|
{ "Perr1_rx_mix", 5, 1 },
|
|
{ "Perr1_rx_sd", 4, 1 },
|
|
{ "Perr1_tx", 3, 1 },
|
|
{ "Perr0_rx_mix", 2, 1 },
|
|
{ "Perr0_rx_sd", 1, 1 },
|
|
{ "Perr0_tx", 0, 1 },
|
|
{ "MAC_PORT_PERR_ENABLE", 0x3c8e8, 0 },
|
|
{ "Perr_pkt_ram", 24, 1 },
|
|
{ "Perr_mask_ram", 23, 1 },
|
|
{ "Perr_crc_ram", 22, 1 },
|
|
{ "rx_dff_seg0", 21, 1 },
|
|
{ "rx_sff_seg0", 20, 1 },
|
|
{ "rx_dff_mac10", 19, 1 },
|
|
{ "rx_sff_mac10", 18, 1 },
|
|
{ "tx_dff_seg0", 17, 1 },
|
|
{ "tx_sff_seg0", 16, 1 },
|
|
{ "tx_dff_mac10", 15, 1 },
|
|
{ "tx_sff_mac10", 14, 1 },
|
|
{ "rx_stats", 13, 1 },
|
|
{ "tx_stats", 12, 1 },
|
|
{ "Perr3_rx_mix", 11, 1 },
|
|
{ "Perr3_rx_sd", 10, 1 },
|
|
{ "Perr3_tx", 9, 1 },
|
|
{ "Perr2_rx_mix", 8, 1 },
|
|
{ "Perr2_rx_sd", 7, 1 },
|
|
{ "Perr2_tx", 6, 1 },
|
|
{ "Perr1_rx_mix", 5, 1 },
|
|
{ "Perr1_rx_sd", 4, 1 },
|
|
{ "Perr1_tx", 3, 1 },
|
|
{ "Perr0_rx_mix", 2, 1 },
|
|
{ "Perr0_rx_sd", 1, 1 },
|
|
{ "Perr0_tx", 0, 1 },
|
|
{ "MAC_PORT_PERR_INJECT", 0x3c8ec, 0 },
|
|
{ "MemSel", 1, 5 },
|
|
{ "InjectDataErr", 0, 1 },
|
|
{ "MAC_PORT_HSS_CFG0", 0x3c8f0, 0 },
|
|
{ "TXDTS", 31, 1 },
|
|
{ "TXCTS", 30, 1 },
|
|
{ "TXBTS", 29, 1 },
|
|
{ "TXATS", 28, 1 },
|
|
{ "TXDOBS", 27, 1 },
|
|
{ "TXCOBS", 26, 1 },
|
|
{ "TXBOBS", 25, 1 },
|
|
{ "TXAOBS", 24, 1 },
|
|
{ "HSSREFCLKVALIDA", 20, 1 },
|
|
{ "HSSREFCLKVALIDB", 19, 1 },
|
|
{ "HSSRESYNCA", 18, 1 },
|
|
{ "HSSAVDHI", 17, 1 },
|
|
{ "HSSRESYNCB", 16, 1 },
|
|
{ "HSSRECCALA", 15, 1 },
|
|
{ "HSSRXACMODE", 14, 1 },
|
|
{ "HSSRECCALB", 13, 1 },
|
|
{ "HSSPLLBYPA", 12, 1 },
|
|
{ "HSSPLLBYPB", 11, 1 },
|
|
{ "HSSPDWNPLLA", 10, 1 },
|
|
{ "HSSPDWNPLLB", 9, 1 },
|
|
{ "HSSVCOSELA", 8, 1 },
|
|
{ "HSSVCOSELB", 7, 1 },
|
|
{ "HSSCALCOMP", 6, 1 },
|
|
{ "HSSCALENAB", 5, 1 },
|
|
{ "HSSEXTC16SEL", 4, 1 },
|
|
{ "MAC_PORT_HSS_CFG1", 0x3c8f4, 0 },
|
|
{ "RXACONFIGSEL", 30, 2 },
|
|
{ "RXAQUIET", 29, 1 },
|
|
{ "RXAREFRESH", 28, 1 },
|
|
{ "RXBCONFIGSEL", 26, 2 },
|
|
{ "RXBQUIET", 25, 1 },
|
|
{ "RXBREFRESH", 24, 1 },
|
|
{ "RXCCONFIGSEL", 22, 2 },
|
|
{ "RXCQUIET", 21, 1 },
|
|
{ "RXCREFRESH", 20, 1 },
|
|
{ "RXDCONFIGSEL", 18, 2 },
|
|
{ "RXDQUIET", 17, 1 },
|
|
{ "RXDREFRESH", 16, 1 },
|
|
{ "TXACONFIGSEL", 14, 2 },
|
|
{ "TXAQUIET", 13, 1 },
|
|
{ "TXAREFRESH", 12, 1 },
|
|
{ "TXBCONFIGSEL", 10, 2 },
|
|
{ "TXBQUIET", 9, 1 },
|
|
{ "TXBREFRESH", 8, 1 },
|
|
{ "TXCCONFIGSEL", 6, 2 },
|
|
{ "TXCQUIET", 5, 1 },
|
|
{ "TXCREFRESH", 4, 1 },
|
|
{ "TXDCONFIGSEL", 2, 2 },
|
|
{ "TXDQUIET", 1, 1 },
|
|
{ "TXDREFRESH", 0, 1 },
|
|
{ "MAC_PORT_HSS_CFG2", 0x3c8f8, 0 },
|
|
{ "RXAASSTCLK", 31, 1 },
|
|
{ "T5RXAPRBSRST", 30, 1 },
|
|
{ "RXBASSTCLK", 29, 1 },
|
|
{ "T5RXBPRBSRST", 28, 1 },
|
|
{ "RXCASSTCLK", 27, 1 },
|
|
{ "T5RXCPRBSRST", 26, 1 },
|
|
{ "RXDASSTCLK", 25, 1 },
|
|
{ "T5RXDPRBSRST", 24, 1 },
|
|
{ "RXDDATASYNC", 23, 1 },
|
|
{ "RXCDATASYNC", 22, 1 },
|
|
{ "RXBDATASYNC", 21, 1 },
|
|
{ "RXADATASYNC", 20, 1 },
|
|
{ "RXDEARLYIN", 19, 1 },
|
|
{ "RXDLATEIN", 18, 1 },
|
|
{ "RXDPHSLOCK", 17, 1 },
|
|
{ "RXDPHSDNIN", 16, 1 },
|
|
{ "RXDPHSUPIN", 15, 1 },
|
|
{ "RXCEARLYIN", 14, 1 },
|
|
{ "RXCLATEIN", 13, 1 },
|
|
{ "RXCPHSLOCK", 12, 1 },
|
|
{ "RXCPHSDNIN", 11, 1 },
|
|
{ "RXCPHSUPIN", 10, 1 },
|
|
{ "RXBEARLYIN", 9, 1 },
|
|
{ "RXBLATEIN", 8, 1 },
|
|
{ "RXBPHSLOCK", 7, 1 },
|
|
{ "RXBPHSDNIN", 6, 1 },
|
|
{ "RXBPHSUPIN", 5, 1 },
|
|
{ "RXAEARLYIN", 4, 1 },
|
|
{ "RXALATEIN", 3, 1 },
|
|
{ "RXAPHSLOCK", 2, 1 },
|
|
{ "RXAPHSDNIN", 1, 1 },
|
|
{ "RXAPHSUPIN", 0, 1 },
|
|
{ "MAC_PORT_HSS_CFG3", 0x3c8fc, 0 },
|
|
{ "HSSCALSSTN", 25, 3 },
|
|
{ "HSSCALSSTP", 22, 3 },
|
|
{ "HSSVBOOSTDIVB", 19, 3 },
|
|
{ "HSSVBOOSTDIVA", 16, 3 },
|
|
{ "HSSPLLCONFIGB", 8, 8 },
|
|
{ "HSSPLLCONFIGA", 0, 8 },
|
|
{ "MAC_PORT_HSS_CFG4", 0x3c900, 0 },
|
|
{ "HSSDIVSELA", 9, 9 },
|
|
{ "HSSDIVSELB", 0, 9 },
|
|
{ "MAC_PORT_HSS_STATUS", 0x3c904, 0 },
|
|
{ "RXDPRBSSYNC", 15, 1 },
|
|
{ "RXCPRBSSYNC", 14, 1 },
|
|
{ "RXBPRBSSYNC", 13, 1 },
|
|
{ "RXAPRBSSYNC", 12, 1 },
|
|
{ "RXDPRBSERR", 11, 1 },
|
|
{ "RXCPRBSERR", 10, 1 },
|
|
{ "RXBPRBSERR", 9, 1 },
|
|
{ "RXAPRBSERR", 8, 1 },
|
|
{ "RXDSIGDET", 7, 1 },
|
|
{ "RXCSIGDET", 6, 1 },
|
|
{ "RXBSIGDET", 5, 1 },
|
|
{ "RXASIGDET", 4, 1 },
|
|
{ "HSSPLLLOCKB", 3, 1 },
|
|
{ "HSSPLLLOCKA", 2, 1 },
|
|
{ "HSSPRTREADYB", 1, 1 },
|
|
{ "HSSPRTREADYA", 0, 1 },
|
|
{ "MAC_PORT_HSS_EEE_STATUS", 0x3c908, 0 },
|
|
{ "RXAQUIET_STATUS", 15, 1 },
|
|
{ "RXAREFRESH_STATUS", 14, 1 },
|
|
{ "RXBQUIET_STATUS", 13, 1 },
|
|
{ "RXBREFRESH_STATUS", 12, 1 },
|
|
{ "RXCQUIET_STATUS", 11, 1 },
|
|
{ "RXCREFRESH_STATUS", 10, 1 },
|
|
{ "RXDQUIET_STATUS", 9, 1 },
|
|
{ "RXDREFRESH_STATUS", 8, 1 },
|
|
{ "TXAQUIET_STATUS", 7, 1 },
|
|
{ "TXAREFRESH_STATUS", 6, 1 },
|
|
{ "TXBQUIET_STATUS", 5, 1 },
|
|
{ "TXBREFRESH_STATUS", 4, 1 },
|
|
{ "TXCQUIET_STATUS", 3, 1 },
|
|
{ "TXCREFRESH_STATUS", 2, 1 },
|
|
{ "TXDQUIET_STATUS", 1, 1 },
|
|
{ "TXDREFRESH_STATUS", 0, 1 },
|
|
{ "MAC_PORT_HSS_SIGDET_STATUS", 0x3c90c, 0 },
|
|
{ "MAC_PORT_HSS_PL_CTL", 0x3c910, 0 },
|
|
{ "TOV", 16, 8 },
|
|
{ "TSU", 8, 8 },
|
|
{ "IPW", 0, 8 },
|
|
{ "MAC_PORT_RUNT_FRAME", 0x3c914, 0 },
|
|
{ "runtclear", 16, 1 },
|
|
{ "runt", 0, 16 },
|
|
{ "MAC_PORT_EEE_STATUS", 0x3c918, 0 },
|
|
{ "eee_tx_10g_state", 10, 2 },
|
|
{ "eee_rx_10g_state", 8, 2 },
|
|
{ "eee_tx_1g_state", 6, 2 },
|
|
{ "eee_rx_1g_state", 4, 2 },
|
|
{ "pma_rx_refresh", 3, 1 },
|
|
{ "pma_rx_quiet", 2, 1 },
|
|
{ "pma_tx_refresh", 1, 1 },
|
|
{ "pma_tx_quiet", 0, 1 },
|
|
{ "MAC_PORT_CGEN", 0x3c91c, 0 },
|
|
{ "CGEN", 8, 1 },
|
|
{ "sd7_CGEN", 7, 1 },
|
|
{ "sd6_CGEN", 6, 1 },
|
|
{ "sd5_CGEN", 5, 1 },
|
|
{ "sd4_CGEN", 4, 1 },
|
|
{ "sd3_CGEN", 3, 1 },
|
|
{ "sd2_CGEN", 2, 1 },
|
|
{ "sd1_CGEN", 1, 1 },
|
|
{ "sd0_CGEN", 0, 1 },
|
|
{ "MAC_PORT_CGEN_MTIP", 0x3c920, 0 },
|
|
{ "MACSEG5_CGEN", 11, 1 },
|
|
{ "PCSSEG5_CGEN", 10, 1 },
|
|
{ "MACSEG4_CGEN", 9, 1 },
|
|
{ "PCSSEG4_CGEN", 8, 1 },
|
|
{ "MACSEG3_CGEN", 7, 1 },
|
|
{ "PCSSEG3_CGEN", 6, 1 },
|
|
{ "MACSEG2_CGEN", 5, 1 },
|
|
{ "PCSSEG2_CGEN", 4, 1 },
|
|
{ "MACSEG1_CGEN", 3, 1 },
|
|
{ "PCSSEG1_CGEN", 2, 1 },
|
|
{ "MACSEG0_CGEN", 1, 1 },
|
|
{ "PCSSEG0_CGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_TS_ID", 0x3c924, 0 },
|
|
{ "MAC_PORT_TX_TS_VAL_LO", 0x3c928, 0 },
|
|
{ "MAC_PORT_TX_TS_VAL_HI", 0x3c92c, 0 },
|
|
{ "MAC_PORT_EEE_CTL", 0x3c930, 0 },
|
|
{ "EEE_CTRL", 2, 30 },
|
|
{ "TICK_START", 1, 1 },
|
|
{ "En", 0, 1 },
|
|
{ "MAC_PORT_EEE_TX_CTL", 0x3c934, 0 },
|
|
{ "WAKE_TIMER", 16, 16 },
|
|
{ "HSS_TIMER", 5, 4 },
|
|
{ "HSS_CTL", 4, 1 },
|
|
{ "LPI_ACTIVE", 3, 1 },
|
|
{ "LPI_TXHOLD", 2, 1 },
|
|
{ "LPI_REQ", 1, 1 },
|
|
{ "EEE_TX_RESET", 0, 1 },
|
|
{ "MAC_PORT_EEE_RX_CTL", 0x3c938, 0 },
|
|
{ "WAKE_TIMER", 16, 16 },
|
|
{ "HSS_TIMER", 5, 4 },
|
|
{ "HSS_CTL", 4, 1 },
|
|
{ "LPI_IND", 1, 1 },
|
|
{ "EEE_RX_RESET", 0, 1 },
|
|
{ "MAC_PORT_EEE_TX_10G_SLEEP_TIMER", 0x3c93c, 0 },
|
|
{ "MAC_PORT_EEE_TX_10G_QUIET_TIMER", 0x3c940, 0 },
|
|
{ "MAC_PORT_EEE_TX_10G_WAKE_TIMER", 0x3c944, 0 },
|
|
{ "MAC_PORT_EEE_TX_1G_SLEEP_TIMER", 0x3c948, 0 },
|
|
{ "MAC_PORT_EEE_TX_1G_QUIET_TIMER", 0x3c94c, 0 },
|
|
{ "MAC_PORT_EEE_TX_1G_REFRESH_TIMER", 0x3c950, 0 },
|
|
{ "MAC_PORT_EEE_RX_10G_QUIET_TIMER", 0x3c954, 0 },
|
|
{ "MAC_PORT_EEE_RX_10G_WAKE_TIMER", 0x3c958, 0 },
|
|
{ "MAC_PORT_EEE_RX_10G_WF_TIMER", 0x3c95c, 0 },
|
|
{ "MAC_PORT_EEE_RX_1G_QUIET_TIMER", 0x3c960, 0 },
|
|
{ "MAC_PORT_EEE_RX_1G_WAKE_TIMER", 0x3c964, 0 },
|
|
{ "MAC_PORT_EEE_WF_COUNT", 0x3c968, 0 },
|
|
{ "wake_cnt_clr", 16, 1 },
|
|
{ "wake_cnt", 0, 16 },
|
|
{ "MAC_PORT_PTP_TIMER_RD0_LO", 0x3c96c, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_RD0_HI", 0x3c970, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_RD1_LO", 0x3c974, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_RD1_HI", 0x3c978, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_WR_LO", 0x3c97c, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_WR_HI", 0x3c980, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_OFFSET_0", 0x3c984, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_OFFSET_1", 0x3c988, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_OFFSET_2", 0x3c98c, 0 },
|
|
{ "MAC_PORT_PTP_SUM_LO", 0x3c990, 0 },
|
|
{ "MAC_PORT_PTP_SUM_HI", 0x3c994, 0 },
|
|
{ "MAC_PORT_PTP_TIMER_INCR0", 0x3c998, 0 },
|
|
{ "Y", 16, 16 },
|
|
{ "X", 0, 16 },
|
|
{ "MAC_PORT_PTP_TIMER_INCR1", 0x3c99c, 0 },
|
|
{ "Y_TICK", 16, 16 },
|
|
{ "X_TICK", 0, 16 },
|
|
{ "MAC_PORT_PTP_DRIFT_ADJUST_COUNT", 0x3c9a0, 0 },
|
|
{ "MAC_PORT_PTP_OFFSET_ADJUST_FINE", 0x3c9a4, 0 },
|
|
{ "B", 16, 16 },
|
|
{ "A", 0, 16 },
|
|
{ "MAC_PORT_PTP_OFFSET_ADJUST_TOTAL", 0x3c9a8, 0 },
|
|
{ "MAC_PORT_PTP_CFG", 0x3c9ac, 0 },
|
|
{ "FRZ", 18, 1 },
|
|
{ "OFFSER_ADJUST_SIGN", 17, 1 },
|
|
{ "ADD_OFFSET", 16, 1 },
|
|
{ "CYCLE1", 8, 8 },
|
|
{ "Q", 0, 8 },
|
|
{ "MAC_PORT_MTIP_REVISION", 0x3ca00, 0 },
|
|
{ "CUSTREV", 16, 16 },
|
|
{ "VER", 8, 8 },
|
|
{ "REV", 0, 8 },
|
|
{ "MAC_PORT_MTIP_SCRATCH", 0x3ca04, 0 },
|
|
{ "MAC_PORT_MTIP_COMMAND_CONFIG", 0x3ca08, 0 },
|
|
{ "TX_FLUSH", 22, 1 },
|
|
{ "RX_SFD_ANY", 21, 1 },
|
|
{ "PAUSE_PFC_COMP", 20, 1 },
|
|
{ "PFC_MODE", 19, 1 },
|
|
{ "RS_COL_CNT_EXT", 18, 1 },
|
|
{ "NO_LGTH_CHECK", 17, 1 },
|
|
{ "SEND_IDLE", 16, 1 },
|
|
{ "PHY_TXENA", 15, 1 },
|
|
{ "RX_ERR_DISC", 14, 1 },
|
|
{ "CMD_FRAME_ENA", 13, 1 },
|
|
{ "SW_RESET", 12, 1 },
|
|
{ "TX_PAD_EN", 11, 1 },
|
|
{ "LOOPBACK_EN", 10, 1 },
|
|
{ "TX_ADDR_INS", 9, 1 },
|
|
{ "PAUSE_IGNORE", 8, 1 },
|
|
{ "PAUSE_FWD", 7, 1 },
|
|
{ "CRC_FWD", 6, 1 },
|
|
{ "PAD_EN", 5, 1 },
|
|
{ "PROMIS_EN", 4, 1 },
|
|
{ "WAN_MODE", 3, 1 },
|
|
{ "RX_ENA", 1, 1 },
|
|
{ "TX_ENA", 0, 1 },
|
|
{ "MAC_PORT_MTIP_MAC_ADDR_0", 0x3ca0c, 0 },
|
|
{ "MAC_PORT_MTIP_MAC_ADDR_1", 0x3ca10, 0 },
|
|
{ "MAC_PORT_MTIP_FRM_LENGTH", 0x3ca14, 0 },
|
|
{ "MAC_PORT_MTIP_RX_FIFO_SECTIONS", 0x3ca1c, 0 },
|
|
{ "AVAIL", 16, 16 },
|
|
{ "EMPTY", 0, 16 },
|
|
{ "MAC_PORT_MTIP_TX_FIFO_SECTIONS", 0x3ca20, 0 },
|
|
{ "AVAIL", 16, 16 },
|
|
{ "EMPTY", 0, 16 },
|
|
{ "MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E", 0x3ca24, 0 },
|
|
{ "AlmstFull", 16, 16 },
|
|
{ "AlmstEmpty", 0, 16 },
|
|
{ "MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E", 0x3ca28, 0 },
|
|
{ "AlmstFull", 16, 16 },
|
|
{ "AlmstEmpty", 0, 16 },
|
|
{ "MAC_PORT_MTIP_HASHTABLE_LOAD", 0x3ca2c, 0 },
|
|
{ "ENABLE", 8, 1 },
|
|
{ "ADDR", 0, 6 },
|
|
{ "MAC_PORT_MTIP_MAC_STATUS", 0x3ca40, 0 },
|
|
{ "TS_AVAIL", 3, 1 },
|
|
{ "PHY_LOS", 2, 1 },
|
|
{ "RX_REM_FAULT", 1, 1 },
|
|
{ "RX_LOC_FAULT", 0, 1 },
|
|
{ "MAC_PORT_MTIP_TX_IPG_LENGTH", 0x3ca44, 0 },
|
|
{ "MAC_PORT_MTIP_MAC_CREDIT_TRIGGER", 0x3ca48, 0 },
|
|
{ "MAC_PORT_MTIP_INIT_CREDIT", 0x3ca4c, 0 },
|
|
{ "MAC_PORT_MTIP_CURRENT_CREDIT", 0x3ca50, 0 },
|
|
{ "MAC_PORT_RX_PAUSE_STATUS", 0x3ca74, 0 },
|
|
{ "MAC_PORT_MTIP_TS_TIMESTAMP", 0x3ca7c, 0 },
|
|
{ "MAC_PORT_AFRAMESTRANSMITTEDOK", 0x3ca80, 0 },
|
|
{ "MAC_PORT_AFRAMESTRANSMITTEDOKHI", 0x3ca84, 0 },
|
|
{ "MAC_PORT_AFRAMESRECEIVEDOK", 0x3ca88, 0 },
|
|
{ "MAC_PORT_AFRAMESRECEIVEDOKHI", 0x3ca8c, 0 },
|
|
{ "MAC_PORT_AFRAMECHECKSEQUENCEERRORS", 0x3ca90, 0 },
|
|
{ "MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI", 0x3ca94, 0 },
|
|
{ "MAC_PORT_AALIGNMENTERRORS", 0x3ca98, 0 },
|
|
{ "MAC_PORT_AALIGNMENTERRORSHI", 0x3ca9c, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED", 0x3caa0, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI", 0x3caa4, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED", 0x3caa8, 0 },
|
|
{ "MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI", 0x3caac, 0 },
|
|
{ "MAC_PORT_AFRAMETOOLONGERRORS", 0x3cab0, 0 },
|
|
{ "MAC_PORT_AFRAMETOOLONGERRORSHI", 0x3cab4, 0 },
|
|
{ "MAC_PORT_AINRANGELENGTHERRORS", 0x3cab8, 0 },
|
|
{ "MAC_PORT_AINRANGELENGTHERRORSHI", 0x3cabc, 0 },
|
|
{ "MAC_PORT_VLANTRANSMITTEDOK", 0x3cac0, 0 },
|
|
{ "MAC_PORT_VLANTRANSMITTEDOKHI", 0x3cac4, 0 },
|
|
{ "MAC_PORT_VLANRECEIVEDOK", 0x3cac8, 0 },
|
|
{ "MAC_PORT_VLANRECEIVEDOKHI", 0x3cacc, 0 },
|
|
{ "MAC_PORT_AOCTETSTRANSMITTEDOK", 0x3cad0, 0 },
|
|
{ "MAC_PORT_AOCTETSTRANSMITTEDOKHI", 0x3cad4, 0 },
|
|
{ "MAC_PORT_AOCTETSRECEIVEDOK", 0x3cad8, 0 },
|
|
{ "MAC_PORT_AOCTETSRECEIVEDOKHI", 0x3cadc, 0 },
|
|
{ "MAC_PORT_IFINUCASTPKTS", 0x3cae0, 0 },
|
|
{ "MAC_PORT_IFINUCASTPKTSHI", 0x3cae4, 0 },
|
|
{ "MAC_PORT_IFINMULTICASTPKTS", 0x3cae8, 0 },
|
|
{ "MAC_PORT_IFINMULTICASTPKTSHI", 0x3caec, 0 },
|
|
{ "MAC_PORT_IFINBROADCASTPKTS", 0x3caf0, 0 },
|
|
{ "MAC_PORT_IFINBROADCASTPKTSHI", 0x3caf4, 0 },
|
|
{ "MAC_PORT_IFOUTERRORS", 0x3caf8, 0 },
|
|
{ "MAC_PORT_IFOUTERRORSHI", 0x3cafc, 0 },
|
|
{ "MAC_PORT_IFOUTUCASTPKTS", 0x3cb08, 0 },
|
|
{ "MAC_PORT_IFOUTUCASTPKTSHI", 0x3cb0c, 0 },
|
|
{ "MAC_PORT_IFOUTMULTICASTPKTS", 0x3cb10, 0 },
|
|
{ "MAC_PORT_IFOUTMULTICASTPKTSHI", 0x3cb14, 0 },
|
|
{ "MAC_PORT_IFOUTBROADCASTPKTS", 0x3cb18, 0 },
|
|
{ "MAC_PORT_IFOUTBROADCASTPKTSHI", 0x3cb1c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSDROPEVENTS", 0x3cb20, 0 },
|
|
{ "MAC_PORT_ETHERSTATSDROPEVENTSHI", 0x3cb24, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOCTETS", 0x3cb28, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOCTETSHI", 0x3cb2c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS", 0x3cb30, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTSHI", 0x3cb34, 0 },
|
|
{ "MAC_PORT_ETHERSTATSUNDERSIZEPKTS", 0x3cb38, 0 },
|
|
{ "MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI", 0x3cb3c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS64OCTETS", 0x3cb40, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS64OCTETSHI", 0x3cb44, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS65TO127OCTETS", 0x3cb48, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI", 0x3cb4c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS128TO255OCTETS", 0x3cb50, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI", 0x3cb54, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS256TO511OCTETS", 0x3cb58, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI", 0x3cb5c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS", 0x3cb60, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI", 0x3cb64, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS", 0x3cb68, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI", 0x3cb6c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS", 0x3cb70, 0 },
|
|
{ "MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI", 0x3cb74, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOVERSIZEPKTS", 0x3cb78, 0 },
|
|
{ "MAC_PORT_ETHERSTATSOVERSIZEPKTSHI", 0x3cb7c, 0 },
|
|
{ "MAC_PORT_ETHERSTATSJABBERS", 0x3cb80, 0 },
|
|
{ "MAC_PORT_ETHERSTATSJABBERSHI", 0x3cb84, 0 },
|
|
{ "MAC_PORT_ETHERSTATSFRAGMENTS", 0x3cb88, 0 },
|
|
{ "MAC_PORT_ETHERSTATSFRAGMENTSHI", 0x3cb8c, 0 },
|
|
{ "MAC_PORT_IFINERRORS", 0x3cb90, 0 },
|
|
{ "MAC_PORT_IFINERRORSHI", 0x3cb94, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0", 0x3cb98, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI", 0x3cb9c, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1", 0x3cba0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI", 0x3cba4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2", 0x3cba8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI", 0x3cbac, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3", 0x3cbb0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI", 0x3cbb4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4", 0x3cbb8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI", 0x3cbbc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5", 0x3cbc0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI", 0x3cbc4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6", 0x3cbc8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI", 0x3cbcc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7", 0x3cbd0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI", 0x3cbd4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0", 0x3cbd8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI", 0x3cbdc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1", 0x3cbe0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI", 0x3cbe4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2", 0x3cbe8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI", 0x3cbec, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3", 0x3cbf0, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI", 0x3cbf4, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4", 0x3cbf8, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI", 0x3cbfc, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5", 0x3cc00, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI", 0x3cc04, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6", 0x3cc08, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI", 0x3cc0c, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7", 0x3cc10, 0 },
|
|
{ "MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI", 0x3cc14, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESTRANSMITTED", 0x3cc18, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI", 0x3cc1c, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESRECEIVED", 0x3cc20, 0 },
|
|
{ "MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI", 0x3cc24, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_CONTROL", 0x3cd00, 0 },
|
|
{ "Reset", 15, 1 },
|
|
{ "Loopback", 14, 1 },
|
|
{ "sppedsel1", 13, 1 },
|
|
{ "AN_EN", 12, 1 },
|
|
{ "PWRDWN", 11, 1 },
|
|
{ "Isolate", 10, 1 },
|
|
{ "AN_RESTART", 9, 1 },
|
|
{ "DPLX", 8, 1 },
|
|
{ "CollisionTest", 7, 1 },
|
|
{ "SpeedSel0", 6, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_STATUS", 0x3cd04, 0 },
|
|
{ "100BaseT4", 15, 1 },
|
|
{ "100BaseXFullDplx", 14, 1 },
|
|
{ "100BaseXHalfDplx", 13, 1 },
|
|
{ "10MbpsFullDplx", 12, 1 },
|
|
{ "10MbpsHalfDplx", 11, 1 },
|
|
{ "100BaseT2FullDplx", 10, 1 },
|
|
{ "100BaseT2HalfDplx", 9, 1 },
|
|
{ "ExtdStatus", 8, 1 },
|
|
{ "AN_Complete", 5, 1 },
|
|
{ "SGMII_REM_FAULT", 4, 1 },
|
|
{ "AN_Ability", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "JabberDetect", 1, 1 },
|
|
{ "ExtdCapability", 0, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0", 0x3cd08, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1", 0x3cd0c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_DEV_ABILITY", 0x3cd10, 0 },
|
|
{ "NP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "RF2", 13, 1 },
|
|
{ "RF1", 12, 1 },
|
|
{ "PS2", 8, 1 },
|
|
{ "PS1", 7, 1 },
|
|
{ "HD", 6, 1 },
|
|
{ "FD", 5, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_PARTNER_ABILITY", 0x3cd14, 0 },
|
|
{ "CuLinkStatus", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "CuDplxStatus", 12, 1 },
|
|
{ "CuSpeed", 10, 2 },
|
|
{ "MAC_PORT_MTIP_SGMII_AN_EXPANSION", 0x3cd18, 0 },
|
|
{ "PgRcvd", 1, 1 },
|
|
{ "RealTimePgRcvd", 0, 1 },
|
|
{ "MAC_PORT_MTIP_SGMII_DEVICE_NP", 0x3cd1c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_PARTNER_NP", 0x3cd20, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_EXTENDED_STATUS", 0x3cd3c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_LINK_TIMER_LO", 0x3cd48, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_LINK_TIMER_HI", 0x3cd4c, 0 },
|
|
{ "MAC_PORT_MTIP_SGMII_IF_MODE", 0x3cd50, 0 },
|
|
{ "SGMII_PCS_ENABLE", 5, 1 },
|
|
{ "SGMII_HDUPLEX", 4, 1 },
|
|
{ "SGMII_SPEED", 2, 2 },
|
|
{ "USE_SGMII_AN", 1, 1 },
|
|
{ "SGMII_ENA", 0, 1 },
|
|
{ "MAC_PORT_MTIP_ACT_CTL_SEG", 0x3d200, 0 },
|
|
{ "MAC_PORT_MTIP_MODE_CTL_SEG", 0x3d204, 0 },
|
|
{ "MAC_PORT_MTIP_TXCLK_CTL_SEG", 0x3d208, 0 },
|
|
{ "MAC_PORT_MTIP_TX_PRMBL_CTL_SEG", 0x3d20c, 0 },
|
|
{ "MAC_PORT_MTIP_WAN_RS_COL_CNT", 0x3d220, 0 },
|
|
{ "MAC_PORT_MTIP_VL_INTVL", 0x3d240, 0 },
|
|
{ "VL_INTVL", 1, 1 },
|
|
{ "MAC_PORT_MTIP_MDIO_CFG_STATUS", 0x3d600, 0 },
|
|
{ "CLK_DIV", 7, 9 },
|
|
{ "CL45_EN", 6, 1 },
|
|
{ "disable_preamble", 5, 1 },
|
|
{ "mdio_hold_time", 2, 3 },
|
|
{ "mdio_read_err", 1, 1 },
|
|
{ "mdio_busy", 0, 1 },
|
|
{ "MAC_PORT_MTIP_MDIO_COMMAND", 0x3d604, 0 },
|
|
{ "read", 15, 1 },
|
|
{ "read_incr", 14, 1 },
|
|
{ "port_addr", 5, 5 },
|
|
{ "dev_addr", 0, 5 },
|
|
{ "MAC_PORT_MTIP_MDIO_DATA", 0x3d608, 0 },
|
|
{ "readbusy", 31, 1 },
|
|
{ "data_word", 0, 16 },
|
|
{ "MAC_PORT_MTIP_MDIO_REGADDR", 0x3d60c, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_0", 0x3da00, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_1", 0x3da04, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_2", 0x3da08, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_3", 0x3da0c, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_4", 0x3da10, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_5", 0x3da14, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_6", 0x3da18, 0 },
|
|
{ "MAC_PORT_MTIP_VLAN_TPID_7", 0x3da1c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_CTL", 0x3de00, 0 },
|
|
{ "RESET", 15, 1 },
|
|
{ "LPBK", 14, 1 },
|
|
{ "SPEED_SEL1", 13, 1 },
|
|
{ "LP_MODE", 11, 1 },
|
|
{ "SPEED_SEL0", 6, 1 },
|
|
{ "SPEED", 2, 4 },
|
|
{ "MAC_PORT_MTIP_PCS_STATUS1", 0x3de04, 0 },
|
|
{ "FaultDet", 7, 1 },
|
|
{ "rx_link_status", 2, 1 },
|
|
{ "LoPwrAbl", 1, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_DEVICE_ID0", 0x3de08, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_DEVICE_ID1", 0x3de0c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_SPEED_ABILITY", 0x3de10, 0 },
|
|
{ "100G", 8, 1 },
|
|
{ "40G", 7, 1 },
|
|
{ "10BASE_TL", 1, 1 },
|
|
{ "10G", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_DEVICE_PKG1", 0x3de14, 0 },
|
|
{ "TC", 6, 1 },
|
|
{ "DTEXS", 5, 1 },
|
|
{ "PHYXS", 4, 1 },
|
|
{ "PCS", 3, 1 },
|
|
{ "WIS", 2, 1 },
|
|
{ "PMD_PMA", 1, 1 },
|
|
{ "CL22", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_DEVICE_PKG2", 0x3de18, 0 },
|
|
{ "VendDev2", 15, 1 },
|
|
{ "VendDev1", 14, 1 },
|
|
{ "CL22EXT", 13, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_CTL2", 0x3de1c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_STATUS2", 0x3de20, 0 },
|
|
{ "Device", 15, 1 },
|
|
{ "TxFault", 7, 1 },
|
|
{ "RxFault", 6, 1 },
|
|
{ "100BASE_R", 5, 1 },
|
|
{ "40GBASE_R", 4, 1 },
|
|
{ "10GBASE_T", 3, 1 },
|
|
{ "10GBASE_W", 2, 1 },
|
|
{ "10GBASE_X", 1, 1 },
|
|
{ "10GBASE_R", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_PKG_ID0", 0x3de38, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_PKG_ID1", 0x3de3c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BASER_STATUS1", 0x3de80, 0 },
|
|
{ "RxLinkStatus", 12, 1 },
|
|
{ "RESEREVED", 4, 8 },
|
|
{ "10GPRBS9", 3, 1 },
|
|
{ "10GPRBS31", 2, 1 },
|
|
{ "HiBER", 1, 1 },
|
|
{ "blocklock", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_BASER_STATUS2", 0x3de84, 0 },
|
|
{ "blocklockLL", 15, 1 },
|
|
{ "HiBERLH", 14, 1 },
|
|
{ "HiBERCount", 8, 6 },
|
|
{ "ErrBlkCnt", 0, 8 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_A", 0x3de88, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_A1", 0x3de8c, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_A2", 0x3de90, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_A3", 0x3de94, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_B", 0x3de98, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_B1", 0x3de9c, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_B2", 0x3dea0, 0 },
|
|
{ "MAC_PORT_MTIP_10GBASER_SEED_B3", 0x3dea4, 0 },
|
|
{ "MAC_PORT_MTIP_BASER_TEST_CTRL", 0x3dea8, 0 },
|
|
{ "TXPRBS9", 6, 1 },
|
|
{ "RXPRBS31", 5, 1 },
|
|
{ "TXPRBS31", 4, 1 },
|
|
{ "TxTestPatEn", 3, 1 },
|
|
{ "RxTestPatEn", 2, 1 },
|
|
{ "TestPatSel", 1, 1 },
|
|
{ "DataPatSel", 0, 1 },
|
|
{ "MAC_PORT_MTIP_BASER_TEST_ERR_CNT", 0x3deac, 0 },
|
|
{ "MAC_PORT_MTIP_BER_HIGH_ORDER_CNT", 0x3deb0, 0 },
|
|
{ "MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT", 0x3deb4, 0 },
|
|
{ "HiCountPrsnt", 15, 1 },
|
|
{ "BLOCK_CNT_HI", 0, 14 },
|
|
{ "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1", 0x3dec8, 0 },
|
|
{ "alignstatus", 12, 1 },
|
|
{ "Lane7", 7, 1 },
|
|
{ "Lane6", 6, 1 },
|
|
{ "Lane5", 5, 1 },
|
|
{ "Lane4", 4, 1 },
|
|
{ "Lane3", 3, 1 },
|
|
{ "Lane2", 2, 1 },
|
|
{ "Lane1", 1, 1 },
|
|
{ "Lane0", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2", 0x3decc, 0 },
|
|
{ "Lane19", 11, 1 },
|
|
{ "Lane18", 10, 1 },
|
|
{ "Lane17", 9, 1 },
|
|
{ "Lane16", 8, 1 },
|
|
{ "Lane15", 7, 1 },
|
|
{ "Lane14", 6, 1 },
|
|
{ "Lane13", 5, 1 },
|
|
{ "Lane12", 4, 1 },
|
|
{ "Lane11", 3, 1 },
|
|
{ "Lane10", 2, 1 },
|
|
{ "Lane9", 1, 1 },
|
|
{ "Lane8", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3", 0x3ded0, 0 },
|
|
{ "AMLOCK7", 7, 1 },
|
|
{ "AMLOCK6", 6, 1 },
|
|
{ "AMLOCK5", 5, 1 },
|
|
{ "AMLOCK4", 4, 1 },
|
|
{ "AMLOCK3", 3, 1 },
|
|
{ "AMLOCK2", 2, 1 },
|
|
{ "AMLOCK1", 1, 1 },
|
|
{ "AMLOCK0", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4", 0x3ded4, 0 },
|
|
{ "AMLOCK19", 11, 1 },
|
|
{ "AMLOCK18", 10, 1 },
|
|
{ "AMLOCK17", 9, 1 },
|
|
{ "AMLOCK16", 8, 1 },
|
|
{ "AMLOCK15", 7, 1 },
|
|
{ "AMLOCK14", 6, 1 },
|
|
{ "AMLOCK13", 5, 1 },
|
|
{ "AMLOCK12", 4, 1 },
|
|
{ "AMLOCK11", 3, 1 },
|
|
{ "AMLOCK10", 2, 1 },
|
|
{ "AMLOCK9", 1, 1 },
|
|
{ "AMLOCK8", 0, 1 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0", 0x3df68, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1", 0x3df6c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2", 0x3df70, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3", 0x3df74, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4", 0x3df78, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5", 0x3df7c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6", 0x3df80, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7", 0x3df84, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8", 0x3df88, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9", 0x3df8c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10", 0x3df90, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11", 0x3df94, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12", 0x3df98, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13", 0x3df9c, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14", 0x3dfa0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15", 0x3dfa4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16", 0x3dfa8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17", 0x3dfac, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18", 0x3dfb0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19", 0x3dfb4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_0", 0x3dfb8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_1", 0x3dfbc, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_2", 0x3dfc0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_3", 0x3dfc4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_4", 0x3dfc8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_5", 0x3dfcc, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_6", 0x3dfd0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_7", 0x3dfd4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_8", 0x3dfd8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_9", 0x3dfdc, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_10", 0x3dfe0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_11", 0x3dfe4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_12", 0x3dfe8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_13", 0x3dfec, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_14", 0x3dff0, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_15", 0x3dff4, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_16", 0x3dff8, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_17", 0x3dffc, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_18", 0x3e000, 0 },
|
|
{ "MAC_PORT_MTIP_PCS_LANE_MAP_19", 0x3e004, 0 },
|
|
{ "MAC_PORT_BEAN_CTL", 0x3e200, 0 },
|
|
{ "AN_RESET", 15, 1 },
|
|
{ "EXT_NXP_CTRL", 13, 1 },
|
|
{ "BEAN_EN", 12, 1 },
|
|
{ "RESTART_BEAN", 9, 1 },
|
|
{ "MAC_PORT_BEAN_STATUS", 0x3e204, 0 },
|
|
{ "PDF", 9, 1 },
|
|
{ "EXT_NXP_STATUS", 7, 1 },
|
|
{ "PAGE_RCVD", 6, 1 },
|
|
{ "BEAN_COMPLETE", 5, 1 },
|
|
{ "REM_FAULT_STATUS", 4, 1 },
|
|
{ "BEAN_ABILITY", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "LP_BEAN_ABILITY", 0, 1 },
|
|
{ "MAC_PORT_BEAN_ABILITY_0", 0x3e208, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_1", 0x3e20c, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_2", 0x3e210, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_0", 0x3e214, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_1", 0x3e218, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_2", 0x3e21c, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_MS_COUNT", 0x3e220, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_0", 0x3e224, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_BEAN_XNP_1", 0x3e228, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_2", 0x3e22c, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_0", 0x3e230, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_1", 0x3e234, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_2", 0x3e238, 0 },
|
|
{ "MAC_PORT_BEAN_ETH_STATUS", 0x3e23c, 0 },
|
|
{ "100GCR10", 8, 1 },
|
|
{ "40GCR4", 6, 1 },
|
|
{ "40GKR4", 5, 1 },
|
|
{ "FEC", 4, 1 },
|
|
{ "10GKR", 3, 1 },
|
|
{ "10GKX4", 2, 1 },
|
|
{ "1GKX", 1, 1 },
|
|
{ "MAC_PORT_BEAN_CTL_LANE1", 0x3e240, 0 },
|
|
{ "AN_RESET", 15, 1 },
|
|
{ "EXT_NXP_CTRL", 13, 1 },
|
|
{ "BEAN_EN", 12, 1 },
|
|
{ "RESTART_BEAN", 9, 1 },
|
|
{ "MAC_PORT_BEAN_STATUS_LANE1", 0x3e244, 0 },
|
|
{ "PDF", 9, 1 },
|
|
{ "EXT_NXP_STATUS", 7, 1 },
|
|
{ "PAGE_RCVD", 6, 1 },
|
|
{ "BEAN_COMPLETE", 5, 1 },
|
|
{ "REM_FAULT_STATUS", 4, 1 },
|
|
{ "BEAN_ABILITY", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "LP_BEAN_ABILITY", 0, 1 },
|
|
{ "MAC_PORT_BEAN_ABILITY_0_LANE1", 0x3e248, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_1_LANE1", 0x3e24c, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_2_LANE1", 0x3e250, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_0_LANE1", 0x3e254, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_1_LANE1", 0x3e258, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_2_LANE1", 0x3e25c, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_MS_COUNT_LANE1", 0x3e260, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_0_LANE1", 0x3e264, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_BEAN_XNP_1_LANE1", 0x3e268, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_2_LANE1", 0x3e26c, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_0_LANE1", 0x3e270, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_1_LANE1", 0x3e274, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_2_LANE1", 0x3e278, 0 },
|
|
{ "MAC_PORT_BEAN_ETH_STATUS_LANE1", 0x3e27c, 0 },
|
|
{ "100GCR10", 8, 1 },
|
|
{ "40GCR4", 6, 1 },
|
|
{ "40GKR4", 5, 1 },
|
|
{ "FEC", 4, 1 },
|
|
{ "10GKR", 3, 1 },
|
|
{ "10GKX4", 2, 1 },
|
|
{ "1GKX", 1, 1 },
|
|
{ "MAC_PORT_BEAN_CTL_LANE2", 0x3e280, 0 },
|
|
{ "AN_RESET", 15, 1 },
|
|
{ "EXT_NXP_CTRL", 13, 1 },
|
|
{ "BEAN_EN", 12, 1 },
|
|
{ "RESTART_BEAN", 9, 1 },
|
|
{ "MAC_PORT_BEAN_STATUS_LANE2", 0x3e284, 0 },
|
|
{ "PDF", 9, 1 },
|
|
{ "EXT_NXP_STATUS", 7, 1 },
|
|
{ "PAGE_RCVD", 6, 1 },
|
|
{ "BEAN_COMPLETE", 5, 1 },
|
|
{ "REM_FAULT_STATUS", 4, 1 },
|
|
{ "BEAN_ABILITY", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "LP_BEAN_ABILITY", 0, 1 },
|
|
{ "MAC_PORT_BEAN_ABILITY_0_LANE2", 0x3e288, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_1_LANE2", 0x3e28c, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_2_LANE2", 0x3e290, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_0_LANE2", 0x3e294, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_1_LANE2", 0x3e298, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_2_LANE2", 0x3e29c, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_MS_COUNT_LANE2", 0x3e2a0, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_0_LANE2", 0x3e2a4, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_BEAN_XNP_1_LANE2", 0x3e2a8, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_2_LANE2", 0x3e2ac, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_0_LANE2", 0x3e2b0, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_1_LANE2", 0x3e2b4, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_2_LANE2", 0x3e2b8, 0 },
|
|
{ "MAC_PORT_BEAN_ETH_STATUS_LANE2", 0x3e2bc, 0 },
|
|
{ "100GCR10", 8, 1 },
|
|
{ "40GCR4", 6, 1 },
|
|
{ "40GKR4", 5, 1 },
|
|
{ "FEC", 4, 1 },
|
|
{ "10GKR", 3, 1 },
|
|
{ "10GKX4", 2, 1 },
|
|
{ "1GKX", 1, 1 },
|
|
{ "MAC_PORT_BEAN_CTL_LANE3", 0x3e2c0, 0 },
|
|
{ "AN_RESET", 15, 1 },
|
|
{ "EXT_NXP_CTRL", 13, 1 },
|
|
{ "BEAN_EN", 12, 1 },
|
|
{ "RESTART_BEAN", 9, 1 },
|
|
{ "MAC_PORT_BEAN_STATUS_LANE3", 0x3e2c4, 0 },
|
|
{ "PDF", 9, 1 },
|
|
{ "EXT_NXP_STATUS", 7, 1 },
|
|
{ "PAGE_RCVD", 6, 1 },
|
|
{ "BEAN_COMPLETE", 5, 1 },
|
|
{ "REM_FAULT_STATUS", 4, 1 },
|
|
{ "BEAN_ABILITY", 3, 1 },
|
|
{ "LINK_STATUS", 2, 1 },
|
|
{ "LP_BEAN_ABILITY", 0, 1 },
|
|
{ "MAC_PORT_BEAN_ABILITY_0_LANE3", 0x3e2c8, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_1_LANE3", 0x3e2cc, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_ABILITY_2_LANE3", 0x3e2d0, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_0_LANE3", 0x3e2d4, 0 },
|
|
{ "NXP", 15, 1 },
|
|
{ "ACK", 14, 1 },
|
|
{ "REM_FAULT", 13, 1 },
|
|
{ "PAUSE_ABILITY", 10, 3 },
|
|
{ "ECHO_NONCE", 5, 5 },
|
|
{ "SELECTOR", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_1_LANE3", 0x3e2d8, 0 },
|
|
{ "TECH_ABILITY_1", 5, 11 },
|
|
{ "TX_NONCE", 0, 5 },
|
|
{ "MAC_PORT_BEAN_REM_ABILITY_2_LANE3", 0x3e2dc, 0 },
|
|
{ "T5_FEC_ABILITY", 14, 2 },
|
|
{ "TECH_ABILITY_2", 0, 14 },
|
|
{ "MAC_PORT_BEAN_MS_COUNT_LANE3", 0x3e2e0, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_0_LANE3", 0x3e2e4, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_BEAN_XNP_1_LANE3", 0x3e2e8, 0 },
|
|
{ "MAC_PORT_BEAN_XNP_2_LANE3", 0x3e2ec, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_0_LANE3", 0x3e2f0, 0 },
|
|
{ "XNP", 15, 1 },
|
|
{ "ACKNOWLEDGE", 14, 1 },
|
|
{ "MP", 13, 1 },
|
|
{ "ACK2", 12, 1 },
|
|
{ "TOGGLE", 11, 1 },
|
|
{ "MU", 0, 11 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_1_LANE3", 0x3e2f4, 0 },
|
|
{ "MAC_PORT_LP_BEAN_XNP_2_LANE3", 0x3e2f8, 0 },
|
|
{ "MAC_PORT_BEAN_ETH_STATUS_LANE3", 0x3e2fc, 0 },
|
|
{ "100GCR10", 8, 1 },
|
|
{ "40GCR4", 6, 1 },
|
|
{ "40GKR4", 5, 1 },
|
|
{ "FEC", 4, 1 },
|
|
{ "10GKR", 3, 1 },
|
|
{ "10GKX4", 2, 1 },
|
|
{ "1GKX", 1, 1 },
|
|
{ "MAC_PORT_FEC_KR_CONTROL", 0x3e600, 0 },
|
|
{ "enable_tr", 1, 1 },
|
|
{ "restart_tr", 0, 1 },
|
|
{ "MAC_PORT_FEC_KR_STATUS", 0x3e604, 0 },
|
|
{ "fecKRsigdet", 15, 1 },
|
|
{ "train_fail", 3, 1 },
|
|
{ "startup_status", 2, 1 },
|
|
{ "frame_lock", 1, 1 },
|
|
{ "rx_status", 0, 1 },
|
|
{ "MAC_PORT_FEC_KR_LP_COEFF", 0x3e608, 0 },
|
|
{ "Preset", 13, 1 },
|
|
{ "Initialize", 12, 1 },
|
|
{ "CP1_UPD", 4, 2 },
|
|
{ "C0_UPD", 2, 2 },
|
|
{ "CN1_UPD", 0, 2 },
|
|
{ "MAC_PORT_FEC_KR_LP_STAT", 0x3e60c, 0 },
|
|
{ "rx_ready", 15, 1 },
|
|
{ "CP1_STAT", 4, 2 },
|
|
{ "C0_STAT", 2, 2 },
|
|
{ "CN1_STAT", 0, 2 },
|
|
{ "MAC_PORT_FEC_KR_LD_COEFF", 0x3e610, 0 },
|
|
{ "Preset", 13, 1 },
|
|
{ "Initialize", 12, 1 },
|
|
{ "CP1_UPD", 4, 2 },
|
|
{ "C0_UPD", 2, 2 },
|
|
{ "CN1_UPD", 0, 2 },
|
|
{ "MAC_PORT_FEC_KR_LD_STAT", 0x3e614, 0 },
|
|
{ "rx_ready", 15, 1 },
|
|
{ "CP1_STAT", 4, 2 },
|
|
{ "C0_STAT", 2, 2 },
|
|
{ "CN1_STAT", 0, 2 },
|
|
{ "MAC_PORT_FEC_ABILITY", 0x3e618, 0 },
|
|
{ "fec_ind_ability", 1, 1 },
|
|
{ "ability", 0, 1 },
|
|
{ "MAC_PORT_FEC_CONTROL", 0x3e61c, 0 },
|
|
{ "fec_en_err_ind", 1, 1 },
|
|
{ "fec_en", 0, 1 },
|
|
{ "MAC_PORT_FEC_STATUS", 0x3e620, 0 },
|
|
{ "FEC_LOCKED_100", 1, 1 },
|
|
{ "FEC_LOCKED", 0, 1 },
|
|
{ "MAC_PORT_FEC_CERR_CNT_0", 0x3e624, 0 },
|
|
{ "MAC_PORT_FEC_CERR_CNT_1", 0x3e628, 0 },
|
|
{ "MAC_PORT_FEC_NCERR_CNT_0", 0x3e62c, 0 },
|
|
{ "MAC_PORT_FEC_NCERR_CNT_1", 0x3e630, 0 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ", 0x3ea00, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT", 0x3ea04, 0 },
|
|
{ "T5_AE0_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE0_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE0_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE0_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ", 0x3ea08, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT", 0x3ea0c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE", 0x3ea10, 0 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL", 0x3ea14, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL", 0x3ea18, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE", 0x3ea1c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ_1", 0x3ea20, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT_1", 0x3ea24, 0 },
|
|
{ "T5_AE1_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE1_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE1_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE1_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ_1", 0x3ea28, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT_1", 0x3ea2c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE_1", 0x3ea30, 0 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL_1", 0x3ea34, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL_1", 0x3ea38, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE_1", 0x3ea3c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ_2", 0x3ea40, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT_2", 0x3ea44, 0 },
|
|
{ "T5_AE2_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE2_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE2_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE2_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ_2", 0x3ea48, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT_2", 0x3ea4c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE_2", 0x3ea50, 0 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL_2", 0x3ea54, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL_2", 0x3ea58, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE_2", 0x3ea5c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_RX_COEF_REQ_3", 0x3ea60, 0 },
|
|
{ "RXREQ_CPRE", 13, 1 },
|
|
{ "RXREQ_CINIT", 12, 1 },
|
|
{ "T5_RXREQ_C2", 4, 2 },
|
|
{ "T5_RXREQ_C1", 2, 2 },
|
|
{ "T5_RXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_RX_COEF_STAT_3", 0x3ea64, 0 },
|
|
{ "T5_AE3_RXSTAT_RDY", 15, 1 },
|
|
{ "T5_AE3_RXSTAT_C2", 4, 2 },
|
|
{ "T5_AE3_RXSTAT_C1", 2, 2 },
|
|
{ "T5_AE3_RXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_REQ_3", 0x3ea68, 0 },
|
|
{ "TXREQ_CPRE", 13, 1 },
|
|
{ "TXREQ_CINIT", 12, 1 },
|
|
{ "T5_TXREQ_C2", 4, 2 },
|
|
{ "T5_TXREQ_C1", 2, 2 },
|
|
{ "T5_TXREQ_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_TX_COEF_STAT_3", 0x3ea6c, 0 },
|
|
{ "TXSTAT_RDY", 15, 1 },
|
|
{ "T5_TXSTAT_C2", 4, 2 },
|
|
{ "T5_TXSTAT_C1", 2, 2 },
|
|
{ "T5_TXSTAT_C0", 0, 2 },
|
|
{ "MAC_PORT_AE_REG_MODE_3", 0x3ea70, 0 },
|
|
{ "AET_RSVD", 7, 1 },
|
|
{ "AET_ENABLE", 6, 1 },
|
|
{ "MAN_DEC", 4, 2 },
|
|
{ "MANUAL_RDY", 3, 1 },
|
|
{ "MWT_DISABLE", 2, 1 },
|
|
{ "MDIO_OVR", 1, 1 },
|
|
{ "STICKY_MODE", 0, 1 },
|
|
{ "MAC_PORT_AE_PRBS_CTL_3", 0x3ea74, 0 },
|
|
{ "PRBS_CHK_ERRCNT", 8, 8 },
|
|
{ "PRBS_SYNCCNT", 5, 3 },
|
|
{ "PRBS_CHK_SYNC", 4, 1 },
|
|
{ "PRBS_CHK_RST", 3, 1 },
|
|
{ "PRBS_CHK_OFF", 2, 1 },
|
|
{ "PRBS_GEN_FRCERR", 1, 1 },
|
|
{ "PRBS_GEN_OFF", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_CTL_3", 0x3ea78, 0 },
|
|
{ "CIN_ENABLE", 15, 1 },
|
|
{ "FSM_TR_LCL", 14, 1 },
|
|
{ "FSM_GDMRK", 11, 3 },
|
|
{ "FSM_BADMRK", 8, 3 },
|
|
{ "FSM_TR_FAIL", 7, 1 },
|
|
{ "FSM_TR_ACT", 6, 1 },
|
|
{ "FSM_FRM_LCK", 5, 1 },
|
|
{ "FSM_TR_COMP", 4, 1 },
|
|
{ "MC_RX_RDY", 3, 1 },
|
|
{ "FSM_CU_DIS", 2, 1 },
|
|
{ "FSM_TR_RST", 1, 1 },
|
|
{ "FSM_TR_EN", 0, 1 },
|
|
{ "MAC_PORT_AE_FSM_STATE_3", 0x3ea7c, 0 },
|
|
{ "CC2FSM_STATE", 13, 3 },
|
|
{ "CC1FSM_STATE", 10, 3 },
|
|
{ "CC0FSM_STATE", 7, 3 },
|
|
{ "FLFSM_STATE", 4, 3 },
|
|
{ "TFSM_STATE", 0, 3 },
|
|
{ "MAC_PORT_AE_TX_DIS", 0x3ea80, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL", 0x3ea84, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET", 0x3ea88, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS", 0x3ea8c, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AE_TX_DIS_1", 0x3ea90, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL_1", 0x3ea94, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET_1", 0x3ea98, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS_1", 0x3ea9c, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AE_TX_DIS_2", 0x3eaa0, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL_2", 0x3eaa4, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET_2", 0x3eaa8, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS_2", 0x3eaac, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AE_TX_DIS_3", 0x3eab0, 0 },
|
|
{ "MAC_PORT_AE_KR_CTRL_3", 0x3eab4, 0 },
|
|
{ "Training_Enable", 1, 1 },
|
|
{ "Restart_Training", 0, 1 },
|
|
{ "MAC_PORT_AE_RX_SIGDET_3", 0x3eab8, 0 },
|
|
{ "MAC_PORT_AE_KR_STATUS_3", 0x3eabc, 0 },
|
|
{ "Training_Failure", 3, 1 },
|
|
{ "Training", 2, 1 },
|
|
{ "Frame_Lock", 1, 1 },
|
|
{ "RX_Trained", 0, 1 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_0", 0x3eb00, 0 },
|
|
{ "EN_HOLD_FAIL", 14, 1 },
|
|
{ "INIT_METH", 12, 2 },
|
|
{ "CE_DECS", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_C1", 5, 1 },
|
|
{ "EN_MAX_ST", 4, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0", 0x3eb04, 0 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_0", 0x3eb08, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0", 0x3eb0c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT6", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_0", 0x3eb10, 0 },
|
|
{ "AET_STAT", 9, 4 },
|
|
{ "NEU_STATE", 5, 4 },
|
|
{ "CTRL_STATE", 0, 5 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_1", 0x3eb20, 0 },
|
|
{ "EN_HOLD_FAIL", 14, 1 },
|
|
{ "INIT_METH", 12, 2 },
|
|
{ "CE_DECS", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_C1", 5, 1 },
|
|
{ "EN_MAX_ST", 4, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1", 0x3eb24, 0 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_1", 0x3eb28, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1", 0x3eb2c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT6", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_1", 0x3eb30, 0 },
|
|
{ "AET_STAT", 9, 4 },
|
|
{ "NEU_STATE", 5, 4 },
|
|
{ "CTRL_STATE", 0, 5 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_2", 0x3eb40, 0 },
|
|
{ "EN_HOLD_FAIL", 14, 1 },
|
|
{ "INIT_METH", 12, 2 },
|
|
{ "CE_DECS", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_C1", 5, 1 },
|
|
{ "EN_MAX_ST", 4, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2", 0x3eb44, 0 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_2", 0x3eb48, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2", 0x3eb4c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT6", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_2", 0x3eb50, 0 },
|
|
{ "AET_STAT", 9, 4 },
|
|
{ "NEU_STATE", 5, 4 },
|
|
{ "CTRL_STATE", 0, 5 },
|
|
{ "MAC_PORT_AET_STAGE_CONFIGURATION_3", 0x3eb60, 0 },
|
|
{ "EN_HOLD_FAIL", 14, 1 },
|
|
{ "INIT_METH", 12, 2 },
|
|
{ "CE_DECS", 8, 4 },
|
|
{ "EN_ZFE", 7, 1 },
|
|
{ "EN_GAIN_TOG", 6, 1 },
|
|
{ "EN_AI_C1", 5, 1 },
|
|
{ "EN_MAX_ST", 4, 1 },
|
|
{ "EN_H1T_EQ", 3, 1 },
|
|
{ "H1TEQ_GOAL", 0, 3 },
|
|
{ "MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3", 0x3eb64, 0 },
|
|
{ "GAIN_TH", 6, 5 },
|
|
{ "EN_SD_TH", 5, 1 },
|
|
{ "EN_AMIN_TH", 4, 1 },
|
|
{ "AMIN_TH", 0, 4 },
|
|
{ "MAC_PORT_AET_ZFE_LIMITS_3", 0x3eb68, 0 },
|
|
{ "ACC_LIM", 8, 4 },
|
|
{ "CNV_LIM", 4, 4 },
|
|
{ "TOG_LIM", 0, 4 },
|
|
{ "MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3", 0x3eb6c, 0 },
|
|
{ "BOOT_LUT7", 12, 4 },
|
|
{ "BOOT_LUT6", 8, 4 },
|
|
{ "BOOT_LUT45", 4, 4 },
|
|
{ "BOOT_LUT0123", 2, 2 },
|
|
{ "BOOT_DEC_C0", 1, 1 },
|
|
{ "MAC_PORT_AET_STATUS_3", 0x3eb70, 0 },
|
|
{ "AET_STAT", 9, 4 },
|
|
{ "NEU_STATE", 5, 4 },
|
|
{ "CTRL_STATE", 0, 5 },
|
|
{ "MAC_PORT_ANALOG_TEST_MUX", 0x3f814, 0 },
|
|
{ "MAC_PORT_BANDGAP_CONTROL", 0x3f82c, 0 },
|
|
{ "MAC_PORT_RESISTOR_CALIBRATION_CONTROL", 0x3f880, 0 },
|
|
{ "RCCTL1", 5, 1 },
|
|
{ "RCCTL0", 4, 1 },
|
|
{ "RCAMP1", 3, 1 },
|
|
{ "RCAMP0", 2, 1 },
|
|
{ "RCAMPEN", 1, 1 },
|
|
{ "RCRST", 0, 1 },
|
|
{ "MAC_PORT_RESISTOR_CALIBRATION_STATUS_1", 0x3f884, 0 },
|
|
{ "RCERR", 1, 1 },
|
|
{ "RCCOMP", 0, 1 },
|
|
{ "MAC_PORT_RESISTOR_CALIBRATION_STATUS_2", 0x3f888, 0 },
|
|
{ "MAC_PORT_RESISTOR_CALIBRATION_STATUS_3", 0x3f88c, 0 },
|
|
{ "MAC_PORT_MACRO_TEST_CONTROL_6", 0x3f8e8, 0 },
|
|
{ "LBIST", 7, 1 },
|
|
{ "LOGICTEST", 6, 1 },
|
|
{ "MAVDHI", 5, 1 },
|
|
{ "AUXEN", 4, 1 },
|
|
{ "JTAGMD", 3, 1 },
|
|
{ "RXACMODE", 2, 1 },
|
|
{ "HSSACJPC", 1, 1 },
|
|
{ "HSSACJAC", 0, 1 },
|
|
{ "MAC_PORT_MACRO_TEST_CONTROL_5", 0x3f8ec, 0 },
|
|
{ "REFVALIDD", 6, 1 },
|
|
{ "REFVALIDC", 5, 1 },
|
|
{ "REFVALIDB", 4, 1 },
|
|
{ "REFVALIDA", 3, 1 },
|
|
{ "REFSELRESET", 2, 1 },
|
|
{ "SOFTRESET", 1, 1 },
|
|
{ "MACROTEST", 0, 1 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0", 0x3fb00, 0 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1", 0x3fb04, 0 },
|
|
{ "LDET", 4, 1 },
|
|
{ "CCERR", 3, 1 },
|
|
{ "CCCMP", 2, 1 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2", 0x3fb08, 0 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3", 0x3fb0c, 0 },
|
|
{ "FMIN", 3, 1 },
|
|
{ "FMAX", 2, 1 },
|
|
{ "CVHOLD", 1, 1 },
|
|
{ "MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4", 0x3fb10, 0 },
|
|
{ "CMETH", 2, 1 },
|
|
{ "RECAL", 1, 1 },
|
|
{ "CCLD", 0, 1 },
|
|
{ "MAC_PORT_PLLA_CHARGE_PUMP_CONTROL", 0x3fb28, 0 },
|
|
{ "MAC_PORT_PLLA_PCLK_CONTROL", 0x3fb3c, 0 },
|
|
{ "SPEDIV", 3, 5 },
|
|
{ "PCKSEL", 0, 3 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL", 0x3fb40, 0 },
|
|
{ "EMIL", 2, 1 },
|
|
{ "EMID", 1, 1 },
|
|
{ "EMIS", 0, 1 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1", 0x3fb44, 0 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2", 0x3fb48, 0 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3", 0x3fb4c, 0 },
|
|
{ "MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4", 0x3fb50, 0 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_4", 0x3fbf0, 0 },
|
|
{ "VBST", 1, 3 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_3", 0x3fbf4, 0 },
|
|
{ "RESYNC", 6, 1 },
|
|
{ "RXCLKSEL", 5, 1 },
|
|
{ "FRCBAND", 4, 1 },
|
|
{ "PLLBYP", 3, 1 },
|
|
{ "PDWNP", 2, 1 },
|
|
{ "VCOSEL", 1, 1 },
|
|
{ "DIVSEL8", 0, 1 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_2", 0x3fbf8, 0 },
|
|
{ "MAC_PORT_PLLA_MACRO_TEST_CONTROL_1", 0x3fbfc, 0 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0", 0x3fc00, 0 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1", 0x3fc04, 0 },
|
|
{ "LDET", 4, 1 },
|
|
{ "CCERR", 3, 1 },
|
|
{ "CCCMP", 2, 1 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2", 0x3fc08, 0 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3", 0x3fc0c, 0 },
|
|
{ "FMIN", 3, 1 },
|
|
{ "FMAX", 2, 1 },
|
|
{ "CVHOLD", 1, 1 },
|
|
{ "MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4", 0x3fc10, 0 },
|
|
{ "CMETH", 2, 1 },
|
|
{ "RECAL", 1, 1 },
|
|
{ "CCLD", 0, 1 },
|
|
{ "MAC_PORT_PLLB_CHARGE_PUMP_CONTROL", 0x3fc28, 0 },
|
|
{ "MAC_PORT_PLLB_PCLK_CONTROL", 0x3fc3c, 0 },
|
|
{ "SPEDIV", 3, 5 },
|
|
{ "PCKSEL", 0, 3 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL", 0x3fc40, 0 },
|
|
{ "EMIL", 2, 1 },
|
|
{ "EMID", 1, 1 },
|
|
{ "EMIS", 0, 1 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1", 0x3fc44, 0 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2", 0x3fc48, 0 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3", 0x3fc4c, 0 },
|
|
{ "MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4", 0x3fc50, 0 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_4", 0x3fcf0, 0 },
|
|
{ "VBST", 1, 3 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_3", 0x3fcf4, 0 },
|
|
{ "RESYNC", 6, 1 },
|
|
{ "RXCLKSEL", 5, 1 },
|
|
{ "FRCBAND", 4, 1 },
|
|
{ "PLLBYP", 3, 1 },
|
|
{ "PDWNP", 2, 1 },
|
|
{ "VCOSEL", 1, 1 },
|
|
{ "DIVSEL8", 0, 1 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_2", 0x3fcf8, 0 },
|
|
{ "MAC_PORT_PLLB_MACRO_TEST_CONTROL_1", 0x3fcfc, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE", 0x3f000, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL", 0x3f004, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL", 0x3f008, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL", 0x3f00c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3f010, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3f014, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3f018, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3f01c, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT", 0x3f020, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT", 0x3f024, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT", 0x3f028, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE", 0x3f030, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_POLARITY", 0x3f034, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3f038, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3f03c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3f040, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3f044, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3f048, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3f060, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3f064, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3f068, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3f070, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3f074, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3f078, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3f07c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3f080, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3f084, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3f088, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL", 0x3f08c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE", 0x3f090, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED", 0x3f094, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT", 0x3f098, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL", 0x3f09c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3f0f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3f0f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3f0f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3f0fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x3c000, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x3c008, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x3c010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x3c018, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x3c020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x3c028, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x3c030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x3c038, 0 },
|
|
{ "MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x3c040, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE", 0x3f100, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL", 0x3f104, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL", 0x3f108, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL", 0x3f10c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3f110, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3f114, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3f118, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3f11c, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT", 0x3f120, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT", 0x3f124, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT", 0x3f128, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE", 0x3f130, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_POLARITY", 0x3f134, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3f138, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3f13c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3f140, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3f144, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3f148, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3f160, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3f164, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3f168, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3f170, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3f174, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3f178, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3f17c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3f180, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3f184, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3f188, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL", 0x3f18c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE", 0x3f190, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED", 0x3f194, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT", 0x3f198, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL", 0x3f19c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3f1f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3f1f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3f1f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3f1fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x3c000, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x3c008, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x3c010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x3c018, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x3c020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x3c028, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x3c030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x3c038, 0 },
|
|
{ "MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x3c040, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE", 0x3f400, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL", 0x3f404, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL", 0x3f408, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL", 0x3f40c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3f410, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3f414, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3f418, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3f41c, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT", 0x3f420, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT", 0x3f424, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT", 0x3f428, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE", 0x3f430, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_POLARITY", 0x3f434, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3f438, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3f43c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3f440, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3f444, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3f448, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3f460, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3f464, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3f468, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3f470, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3f474, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3f478, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3f47c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3f480, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3f484, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3f488, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL", 0x3f48c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE", 0x3f490, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED", 0x3f494, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT", 0x3f498, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL", 0x3f49c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3f4f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3f4f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3f4f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3f4fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x3c000, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x3c008, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x3c010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x3c018, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x3c020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x3c028, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x3c030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x3c038, 0 },
|
|
{ "MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x3c040, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE", 0x3f500, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL", 0x3f504, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL", 0x3f508, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL", 0x3f50c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3f510, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3f514, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3f518, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3f51c, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT", 0x3f520, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT", 0x3f524, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT", 0x3f528, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE", 0x3f530, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_POLARITY", 0x3f534, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3f538, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3f53c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3f540, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3f544, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3f548, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3f560, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3f564, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3f568, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3f570, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3f574, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3f578, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3f57c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3f580, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3f584, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3f588, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL", 0x3f58c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE", 0x3f590, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED", 0x3f594, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT", 0x3f598, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL", 0x3f59c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3f5f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3f5f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3f5f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3f5fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x3c000, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x3c008, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x3c010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x3c018, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x3c020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x3c028, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x3c030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x3c038, 0 },
|
|
{ "MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x3c040, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE", 0x3f900, 0 },
|
|
{ "T5_TX_LINKEN", 15, 1 },
|
|
{ "T5_TX_LINKRST", 14, 1 },
|
|
{ "T5_TX_CFGWRT", 13, 1 },
|
|
{ "T5_TX_CFGPTR", 11, 2 },
|
|
{ "T5_TX_CFGEXT", 10, 1 },
|
|
{ "T5_TX_CFGACT", 9, 1 },
|
|
{ "T5_TX_RSYNCC", 8, 1 },
|
|
{ "T5_TX_PLLSEL", 6, 2 },
|
|
{ "T5_TX_EXTC16", 5, 1 },
|
|
{ "T5_TX_DCKSEL", 4, 1 },
|
|
{ "T5_TX_RXLOOP", 3, 1 },
|
|
{ "T5_TX_BWSEL", 2, 1 },
|
|
{ "T5_TX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL", 0x3f904, 0 },
|
|
{ "SPSEL", 11, 3 },
|
|
{ "AFDWEN", 7, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "TPGMD", 3, 1 },
|
|
{ "TPSEL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL", 0x3f908, 0 },
|
|
{ "ZCALOVRD", 8, 1 },
|
|
{ "AMMODE", 7, 1 },
|
|
{ "AEPOL", 6, 1 },
|
|
{ "AESRC", 5, 1 },
|
|
{ "EQMODE", 4, 1 },
|
|
{ "OCOEF", 3, 1 },
|
|
{ "COEFRST", 2, 1 },
|
|
{ "ALOAD", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL", 0x3f90c, 0 },
|
|
{ "T5DRVHIZ", 5, 1 },
|
|
{ "T5SASIMP", 4, 1 },
|
|
{ "T5SLEW", 2, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL", 0x3f910, 0 },
|
|
{ "T5C2BUFDCEN", 5, 1 },
|
|
{ "T5DCCEN", 4, 1 },
|
|
{ "T5REGBYP", 3, 1 },
|
|
{ "T5REGAEN", 2, 1 },
|
|
{ "T5REGAMP", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE", 0x3f914, 0 },
|
|
{ "RSTEP", 15, 1 },
|
|
{ "RLOCK", 14, 1 },
|
|
{ "RPOS", 8, 6 },
|
|
{ "DCLKSAM", 7, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE", 0x3f918, 0 },
|
|
{ "CALSSTN", 3, 3 },
|
|
{ "CALSSTP", 0, 3 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE", 0x3f91c, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT", 0x3f920, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT", 0x3f924, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT", 0x3f928, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE", 0x3f930, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY", 0x3f934, 0 },
|
|
{ "TXPOL", 4, 3 },
|
|
{ "NXTPOL", 0, 3 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND", 0x3f938, 0 },
|
|
{ "CPREST", 13, 1 },
|
|
{ "CINIT", 12, 1 },
|
|
{ "C2UPDT", 4, 2 },
|
|
{ "C1UPDT", 2, 2 },
|
|
{ "C0UPDT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS", 0x3f93c, 0 },
|
|
{ "C2STAT", 4, 2 },
|
|
{ "C1STAT", 2, 2 },
|
|
{ "C0STAT", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE", 0x3f940, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE", 0x3f944, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE", 0x3f948, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED", 0x3f960, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED", 0x3f964, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED", 0x3f968, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1", 0x3f970, 0 },
|
|
{ "MAINSC", 6, 6 },
|
|
{ "POSTSC", 0, 6 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2", 0x3f974, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA", 0x3f978, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR", 0x3f97c, 0 },
|
|
{ "T5XADDR", 1, 5 },
|
|
{ "T5XWR", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0", 0x3f980, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2", 0x3f984, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4", 0x3f988, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL", 0x3f98c, 0 },
|
|
{ "DCCTIMEDOUT", 15, 1 },
|
|
{ "DCCTIMEEN", 14, 1 },
|
|
{ "DCCLOCK", 13, 1 },
|
|
{ "DCCOFFSET", 8, 5 },
|
|
{ "DCCSTEP", 6, 2 },
|
|
{ "DCCASTEP", 1, 5 },
|
|
{ "DCCAEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE", 0x3f990, 0 },
|
|
{ "DCCOUT", 12, 1 },
|
|
{ "DCCCLK", 11, 1 },
|
|
{ "DCCHOLD", 10, 1 },
|
|
{ "DCCSIGN", 8, 2 },
|
|
{ "DCCAMP", 1, 7 },
|
|
{ "DCCOEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED", 0x3f994, 0 },
|
|
{ "DCCASIGN", 7, 2 },
|
|
{ "DCCAAMP", 0, 7 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT", 0x3f998, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL", 0x3f99c, 0 },
|
|
{ "LPIDCLK", 4, 1 },
|
|
{ "LPITERM", 2, 2 },
|
|
{ "LPIPRCD", 0, 2 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4", 0x3f9f0, 0 },
|
|
{ "SDOVRDEN", 8, 1 },
|
|
{ "SDOVRD", 0, 8 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3", 0x3f9f4, 0 },
|
|
{ "SLEWCODE", 1, 2 },
|
|
{ "ASEGEN", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2", 0x3f9f8, 0 },
|
|
{ "AECMDVAL", 14, 1 },
|
|
{ "AECMD1312", 12, 2 },
|
|
{ "AECMD70", 0, 8 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1", 0x3f9fc, 0 },
|
|
{ "C48DIVCTL", 12, 3 },
|
|
{ "RATEDIVCTL", 9, 3 },
|
|
{ "ANLGFLSH", 8, 1 },
|
|
{ "DCCTSTOUT", 7, 1 },
|
|
{ "BSOUT", 6, 1 },
|
|
{ "BSIN", 5, 1 },
|
|
{ "JTAGAMPL", 3, 2 },
|
|
{ "JTAGTS", 2, 1 },
|
|
{ "TS", 1, 1 },
|
|
{ "OBS", 0, 1 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED", 0x3c000, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED", 0x3c008, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED", 0x3c010, 0 },
|
|
{ "C0MAX", 8, 5 },
|
|
{ "C0MIN", 0, 5 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED", 0x3c018, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED", 0x3c020, 0 },
|
|
{ "C1MAX", 8, 7 },
|
|
{ "C1MIN", 0, 7 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED", 0x3c028, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED", 0x3c030, 0 },
|
|
{ "C2MAX", 8, 6 },
|
|
{ "C2MIN", 0, 6 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED", 0x3c038, 0 },
|
|
{ "MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED", 0x3c040, 0 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE", 0x3f200, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL", 0x3f204, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL", 0x3f208, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL", 0x3f20c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1", 0x3f210, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2", 0x3f214, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3f218, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3f21c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_CONTROL", 0x3f220, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1", 0x3f224, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2", 0x3f228, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1", 0x3f22c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2", 0x3f230, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3", 0x3f234, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1", 0x3f238, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3", 0x3f240, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN", 0x3f248, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ", 0x3f24c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL", 0x3f250, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3f25c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3f260, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3f264, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3f270, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC", 0x3f274, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS", 0x3f278, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1", 0x3f27c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2", 0x3f280, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2", 0x3f284, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2", 0x3f288, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4", 0x3f28c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4", 0x3f290, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET", 0x3f294, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL", 0x3f298, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL", 0x3f29c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3f2a0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET", 0x3f2a4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL", 0x3f2a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS", 0x3f2ac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3f2b0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3f2b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3f2b8, 0 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_TAP_ENABLE", 0x3f2c0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H1", 0x3f2c4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H2", 0x3f2c8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H3", 0x3f2cc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H4", 0x3f2d0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H5", 0x3f2d4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H6_AND_H7", 0x3f2d8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H8_AND_H9", 0x3f2dc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H10_AND_H11", 0x3f2e0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_DFE_H12", 0x3f2e4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2", 0x3f2f8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1", 0x3f2fc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE", 0x3f300, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL", 0x3f304, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL", 0x3f308, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL", 0x3f30c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1", 0x3f310, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2", 0x3f314, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3f318, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3f31c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_CONTROL", 0x3f320, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1", 0x3f324, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2", 0x3f328, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1", 0x3f32c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2", 0x3f330, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3", 0x3f334, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1", 0x3f338, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3", 0x3f340, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN", 0x3f348, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ", 0x3f34c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL", 0x3f350, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3f35c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3f360, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3f364, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3f370, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC", 0x3f374, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS", 0x3f378, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1", 0x3f37c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2", 0x3f380, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2", 0x3f384, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2", 0x3f388, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4", 0x3f38c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4", 0x3f390, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET", 0x3f394, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL", 0x3f398, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL", 0x3f39c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3f3a0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET", 0x3f3a4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL", 0x3f3a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS", 0x3f3ac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3f3b0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3f3b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3f3b8, 0 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_TAP_ENABLE", 0x3f3c0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H1", 0x3f3c4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H2", 0x3f3c8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H3", 0x3f3cc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H4", 0x3f3d0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H5", 0x3f3d4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H6_AND_H7", 0x3f3d8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H8_AND_H9", 0x3f3dc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H10_AND_H11", 0x3f3e0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_DFE_H12", 0x3f3e4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2", 0x3f3f8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1", 0x3f3fc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE", 0x3f600, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL", 0x3f604, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL", 0x3f608, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL", 0x3f60c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1", 0x3f610, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2", 0x3f614, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3f618, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3f61c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_CONTROL", 0x3f620, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1", 0x3f624, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2", 0x3f628, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1", 0x3f62c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2", 0x3f630, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3", 0x3f634, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1", 0x3f638, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3", 0x3f640, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN", 0x3f648, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ", 0x3f64c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL", 0x3f650, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3f65c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3f660, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3f664, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3f670, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC", 0x3f674, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS", 0x3f678, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1", 0x3f67c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2", 0x3f680, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2", 0x3f684, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2", 0x3f688, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4", 0x3f68c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4", 0x3f690, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET", 0x3f694, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL", 0x3f698, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL", 0x3f69c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3f6a0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET", 0x3f6a4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL", 0x3f6a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS", 0x3f6ac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3f6b0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3f6b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3f6b8, 0 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_TAP_ENABLE", 0x3f6c0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H1", 0x3f6c4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H2", 0x3f6c8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H3", 0x3f6cc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H4", 0x3f6d0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H5", 0x3f6d4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H6_AND_H7", 0x3f6d8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H8_AND_H9", 0x3f6dc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H10_AND_H11", 0x3f6e0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_DFE_H12", 0x3f6e4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2", 0x3f6f8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1", 0x3f6fc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE", 0x3f700, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL", 0x3f704, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL", 0x3f708, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL", 0x3f70c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1", 0x3f710, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2", 0x3f714, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3f718, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3f71c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_CONTROL", 0x3f720, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1", 0x3f724, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2", 0x3f728, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1", 0x3f72c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2", 0x3f730, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3", 0x3f734, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1", 0x3f738, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3", 0x3f740, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN", 0x3f748, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ", 0x3f74c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL", 0x3f750, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3f75c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3f760, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3f764, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3f770, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC", 0x3f774, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS", 0x3f778, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1", 0x3f77c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2", 0x3f780, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2", 0x3f784, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2", 0x3f788, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4", 0x3f78c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4", 0x3f790, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET", 0x3f794, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL", 0x3f798, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL", 0x3f79c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3f7a0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET", 0x3f7a4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL", 0x3f7a8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS", 0x3f7ac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3f7b0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3f7b4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3f7b8, 0 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_TAP_ENABLE", 0x3f7c0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H1", 0x3f7c4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H2", 0x3f7c8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H3", 0x3f7cc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H4", 0x3f7d0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H5", 0x3f7d4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H6_AND_H7", 0x3f7d8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H8_AND_H9", 0x3f7dc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H10_AND_H11", 0x3f7e0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_DFE_H12", 0x3f7e4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2", 0x3f7f8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1", 0x3f7fc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE", 0x3fa00, 0 },
|
|
{ "T5_RX_LINKEN", 15, 1 },
|
|
{ "T5_RX_LINKRST", 14, 1 },
|
|
{ "T5_RX_CFGWRT", 13, 1 },
|
|
{ "T5_RX_CFGPTR", 11, 2 },
|
|
{ "T5_RX_CFGEXT", 10, 1 },
|
|
{ "T5_RX_CFGACT", 9, 1 },
|
|
{ "T5_RX_AUXCLK", 8, 1 },
|
|
{ "T5_RX_PLLSEL", 6, 2 },
|
|
{ "T5_RX_DMSEL", 4, 2 },
|
|
{ "T5_RX_BWSEL", 2, 2 },
|
|
{ "T5_RX_RTSEL", 0, 2 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL", 0x3fa04, 0 },
|
|
{ "RCLKEN", 15, 1 },
|
|
{ "RRATE", 13, 2 },
|
|
{ "FERRST", 10, 1 },
|
|
{ "ERRST", 9, 1 },
|
|
{ "SYNCST", 8, 1 },
|
|
{ "WRPSM", 7, 1 },
|
|
{ "WPLPEN", 6, 1 },
|
|
{ "WRPMD", 5, 1 },
|
|
{ "PRST", 4, 1 },
|
|
{ "PCHKEN", 3, 1 },
|
|
{ "PATSEL", 0, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL", 0x3fa08, 0 },
|
|
{ "FTHROT", 12, 4 },
|
|
{ "RTHROT", 11, 1 },
|
|
{ "FILTCTL", 7, 4 },
|
|
{ "RSRVO", 5, 2 },
|
|
{ "EXTEL", 4, 1 },
|
|
{ "RSTUCK", 3, 1 },
|
|
{ "FRZFW", 2, 1 },
|
|
{ "RSTFW", 1, 1 },
|
|
{ "SSCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL", 0x3fa0c, 0 },
|
|
{ "RSNP", 11, 1 },
|
|
{ "TSOEN", 10, 1 },
|
|
{ "OFFEN", 9, 1 },
|
|
{ "TMSCAL", 7, 2 },
|
|
{ "APADJ", 6, 1 },
|
|
{ "RSEL", 5, 1 },
|
|
{ "PHOFFS", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1", 0x3fa10, 0 },
|
|
{ "ROT0A", 8, 6 },
|
|
{ "ROT00", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2", 0x3fa14, 0 },
|
|
{ "FREQFW", 8, 8 },
|
|
{ "FWSNAP", 7, 1 },
|
|
{ "ROT90", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1", 0x3fa18, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RAOOFF", 10, 5 },
|
|
{ "RAEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2", 0x3fa1c, 0 },
|
|
{ "RCALER", 15, 1 },
|
|
{ "RBOOFF", 10, 5 },
|
|
{ "RBEOFF", 5, 5 },
|
|
{ "RDOFF", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_CONTROL", 0x3fa20, 0 },
|
|
{ "REQCMP", 15, 1 },
|
|
{ "DFEREQ", 14, 1 },
|
|
{ "SPCEN", 13, 1 },
|
|
{ "GATEEN", 12, 1 },
|
|
{ "SPIFMT", 9, 3 },
|
|
{ "DFEPWR", 6, 3 },
|
|
{ "STNDBY", 5, 1 },
|
|
{ "FRCH", 4, 1 },
|
|
{ "NONRND", 3, 1 },
|
|
{ "NONRNF", 2, 1 },
|
|
{ "FSTLCK", 1, 1 },
|
|
{ "DFERST", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1", 0x3fa24, 0 },
|
|
{ "T5BYTE1", 8, 8 },
|
|
{ "T5BYTE0", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2", 0x3fa28, 0 },
|
|
{ "T5_RX_SMODE", 8, 3 },
|
|
{ "T5_RX_ADCORR", 7, 1 },
|
|
{ "T5_RX_TRAINEN", 6, 1 },
|
|
{ "T5_RX_ASAMPQ", 3, 3 },
|
|
{ "T5_RX_ASAMP", 0, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1", 0x3fa2c, 0 },
|
|
{ "POLE", 12, 2 },
|
|
{ "PEAK", 8, 3 },
|
|
{ "VOFFSN", 6, 2 },
|
|
{ "VOFFA", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2", 0x3fa30, 0 },
|
|
{ "T5SHORTV", 10, 1 },
|
|
{ "T5VGAIN", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3", 0x3fa34, 0 },
|
|
{ "HBND1", 10, 1 },
|
|
{ "HBND0", 9, 1 },
|
|
{ "VLCKD", 8, 1 },
|
|
{ "VLCKDF", 7, 1 },
|
|
{ "AMAXT", 0, 7 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1", 0x3fa38, 0 },
|
|
{ "IQSEP", 10, 5 },
|
|
{ "DUTYQ", 5, 5 },
|
|
{ "DUTYI", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3", 0x3fa40, 0 },
|
|
{ "DTHR", 8, 6 },
|
|
{ "SNUL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN", 0x3fa48, 0 },
|
|
{ "DACAN", 8, 8 },
|
|
{ "DACAP", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ", 0x3fa4c, 0 },
|
|
{ "DACAZ", 8, 8 },
|
|
{ "DACAM", 0, 8 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL", 0x3fa50, 0 },
|
|
{ "ADSN_ReadWrite", 8, 1 },
|
|
{ "ADSN_ReadOnly", 7, 1 },
|
|
{ "ADMAG", 0, 7 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2", 0x3fa5c, 0 },
|
|
{ "H1O2", 8, 6 },
|
|
{ "H1E2", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3", 0x3fa60, 0 },
|
|
{ "H1O3", 8, 6 },
|
|
{ "H1E3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4", 0x3fa64, 0 },
|
|
{ "H1O4", 8, 6 },
|
|
{ "H1E4", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC", 0x3fa70, 0 },
|
|
{ "DPCMD", 14, 1 },
|
|
{ "DPCCVG", 13, 1 },
|
|
{ "DACCVG", 12, 1 },
|
|
{ "DPCTGT", 9, 3 },
|
|
{ "BLKH1T", 8, 1 },
|
|
{ "BLKOAE", 7, 1 },
|
|
{ "H1TGT", 4, 3 },
|
|
{ "OAE", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC", 0x3fa74, 0 },
|
|
{ "OLS", 11, 5 },
|
|
{ "OES", 6, 5 },
|
|
{ "BLKODEC", 5, 1 },
|
|
{ "ODEC", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS", 0x3fa78, 0 },
|
|
{ "T5BER6VAL", 15, 1 },
|
|
{ "T5BER6", 14, 1 },
|
|
{ "T5BER3VAL", 13, 1 },
|
|
{ "T5TOOFAST", 12, 1 },
|
|
{ "T5DPCCMP", 9, 1 },
|
|
{ "T5DACCMP", 8, 1 },
|
|
{ "T5DDCCMP", 7, 1 },
|
|
{ "T5AERRFLG", 6, 1 },
|
|
{ "T5WERRFLG", 5, 1 },
|
|
{ "T5TRCMP", 4, 1 },
|
|
{ "T5VLCKF", 3, 1 },
|
|
{ "T5ROCCMP", 2, 1 },
|
|
{ "T5DQCCCMP", 1, 1 },
|
|
{ "T5OCCMP", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1", 0x3fa7c, 0 },
|
|
{ "FDPC", 15, 1 },
|
|
{ "FDAC", 14, 1 },
|
|
{ "FDDC", 13, 1 },
|
|
{ "FNRND", 12, 1 },
|
|
{ "FVGAIN", 11, 1 },
|
|
{ "FVOFF", 10, 1 },
|
|
{ "FSDET", 9, 1 },
|
|
{ "FBER6", 8, 1 },
|
|
{ "FROTO", 7, 1 },
|
|
{ "FH4H5", 6, 1 },
|
|
{ "FH2H3", 5, 1 },
|
|
{ "FH1", 4, 1 },
|
|
{ "FH1SN", 3, 1 },
|
|
{ "FNRDF", 2, 1 },
|
|
{ "FLOFF", 1, 1 },
|
|
{ "FADAC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2", 0x3fa80, 0 },
|
|
{ "H25SPC", 15, 1 },
|
|
{ "FTOOFAST", 8, 1 },
|
|
{ "FINTTRIM", 7, 1 },
|
|
{ "FDINV", 6, 1 },
|
|
{ "FHGS", 5, 1 },
|
|
{ "FH6H12", 4, 1 },
|
|
{ "FH1CAL", 3, 1 },
|
|
{ "FINTCAL", 2, 1 },
|
|
{ "FDCA", 1, 1 },
|
|
{ "FDQCC", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2", 0x3fa84, 0 },
|
|
{ "LOFE2S_ReadWrite", 16, 1 },
|
|
{ "LOFE2S_ReadOnly", 14, 2 },
|
|
{ "LOFE2", 8, 6 },
|
|
{ "LOFE1S_ReadWrite", 7, 1 },
|
|
{ "LOFE1S_ReadOnly", 6, 1 },
|
|
{ "LOFE1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2", 0x3fa88, 0 },
|
|
{ "LOFO2S_ReadWrite", 15, 1 },
|
|
{ "LOFO2S_ReadOnly", 14, 1 },
|
|
{ "LOFO2", 8, 6 },
|
|
{ "LOFO1S_ReadWrite", 7, 1 },
|
|
{ "LOFO1S_ReadOnly", 6, 1 },
|
|
{ "LOFO1", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4", 0x3fa8c, 0 },
|
|
{ "LOFE4S_ReadWrite", 15, 1 },
|
|
{ "LOFE4S_ReadOnly", 14, 1 },
|
|
{ "LOFE", 8, 6 },
|
|
{ "LOFE3S_ReadWrite", 7, 1 },
|
|
{ "LOFE3S_ReadOnly", 6, 1 },
|
|
{ "LOFE3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4", 0x3fa90, 0 },
|
|
{ "LOFO4S_ReadWrite", 15, 1 },
|
|
{ "LOFO4S_ReadOnly", 14, 1 },
|
|
{ "LOFO4", 8, 6 },
|
|
{ "LOFO3S_ReadWrite", 7, 1 },
|
|
{ "LOFO3S_ReadOnly", 6, 1 },
|
|
{ "LOFO3", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET", 0x3fa94, 0 },
|
|
{ "T5E1SN_ReadWrite", 15, 1 },
|
|
{ "T5E1SN_ReadOnly", 14, 1 },
|
|
{ "T5E1AMP", 8, 6 },
|
|
{ "T5E0SN_ReadWrite", 7, 1 },
|
|
{ "T5E0SN_ReadOnly", 6, 1 },
|
|
{ "T5E0AMP", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL", 0x3fa98, 0 },
|
|
{ "T5LFREG", 12, 1 },
|
|
{ "T5LFRC", 11, 1 },
|
|
{ "T5LFSEL", 8, 3 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL", 0x3fa9c, 0 },
|
|
{ "OFFSN_ReadWrite", 14, 1 },
|
|
{ "OFFSN_ReadOnly", 13, 1 },
|
|
{ "OFFAMP", 8, 5 },
|
|
{ "SDACDC", 7, 1 },
|
|
{ "SDPDN", 6, 1 },
|
|
{ "SIGDET", 5, 1 },
|
|
{ "SDLVL", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH", 0x3faa0, 0 },
|
|
{ "T5_RX_SETHDIS", 7, 1 },
|
|
{ "T5_RX_PDTERM", 6, 1 },
|
|
{ "T5_RX_BYPASS", 5, 1 },
|
|
{ "T5_RX_LPFEN", 4, 1 },
|
|
{ "T5_RX_VGABOD", 3, 1 },
|
|
{ "T5_RX_VTBYP", 2, 1 },
|
|
{ "T5_RX_VTERM", 0, 2 },
|
|
{ "MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET", 0x3faa4, 0 },
|
|
{ "ISTRIMS", 14, 2 },
|
|
{ "ISTRIM", 8, 6 },
|
|
{ "HALF1", 7, 1 },
|
|
{ "HALF2", 6, 1 },
|
|
{ "INTDAC", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL", 0x3faa8, 0 },
|
|
{ "BLKAZ", 15, 1 },
|
|
{ "WIDTH", 10, 5 },
|
|
{ "MINWDTH", 5, 5 },
|
|
{ "MINAMP", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS", 0x3faac, 0 },
|
|
{ "T5SMQM", 13, 3 },
|
|
{ "T5SMQ", 5, 8 },
|
|
{ "T5EMMD", 3, 2 },
|
|
{ "T5EMBRDY", 2, 1 },
|
|
{ "T5EMBUMP", 1, 1 },
|
|
{ "T5EMEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT", 0x3fab0, 0 },
|
|
{ "EMF8", 15, 1 },
|
|
{ "EMCNT", 4, 8 },
|
|
{ "EMOFLO", 2, 1 },
|
|
{ "EMCRST", 1, 1 },
|
|
{ "EMCEN", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT", 0x3fab4, 0 },
|
|
{ "SM2RDY", 15, 1 },
|
|
{ "SM2RST", 14, 1 },
|
|
{ "APDF", 0, 12 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH", 0x3fab8, 0 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE", 0x3fac0, 0 },
|
|
{ "H_EN", 1, 12 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H1", 0x3fac4, 0 },
|
|
{ "H1OSN", 14, 2 },
|
|
{ "H1OMAG", 8, 6 },
|
|
{ "H1ESN", 6, 2 },
|
|
{ "H1EMAG", 0, 6 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H2", 0x3fac8, 0 },
|
|
{ "H2OSN_ReadWrite", 14, 1 },
|
|
{ "H2OSN_ReadOnly", 13, 1 },
|
|
{ "H2OMAG", 8, 5 },
|
|
{ "H2ESN_ReadWrite", 6, 1 },
|
|
{ "H2ESN_ReadOnly", 5, 1 },
|
|
{ "H2EMAG", 0, 5 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H3", 0x3facc, 0 },
|
|
{ "H3OSN_ReadWrite", 13, 1 },
|
|
{ "H3OSN_ReadOnly", 12, 1 },
|
|
{ "H3OMAG", 8, 4 },
|
|
{ "H3ESN_ReadWrite", 5, 1 },
|
|
{ "H3ESN_ReadOnly", 4, 1 },
|
|
{ "H3EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H4", 0x3fad0, 0 },
|
|
{ "H4OGS", 14, 2 },
|
|
{ "H4OSN_ReadWrite", 13, 1 },
|
|
{ "H4OSN_ReadOnly", 12, 1 },
|
|
{ "H4OMAG", 8, 4 },
|
|
{ "H4EGS", 6, 2 },
|
|
{ "H4ESN_ReadWrite", 5, 1 },
|
|
{ "H4ESN_ReadOnly", 4, 1 },
|
|
{ "H4EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H5", 0x3fad4, 0 },
|
|
{ "H5OGS", 14, 2 },
|
|
{ "H5OSN_ReadWrite", 13, 1 },
|
|
{ "H5OSN_ReadOnly", 12, 1 },
|
|
{ "H5OMAG", 8, 4 },
|
|
{ "H5EGS", 6, 2 },
|
|
{ "H5ESN_ReadWrite", 5, 1 },
|
|
{ "H5ESN_ReadOnly", 4, 1 },
|
|
{ "H5EMAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7", 0x3fad8, 0 },
|
|
{ "H7GS", 14, 2 },
|
|
{ "H7SN_ReadWrite", 13, 1 },
|
|
{ "H7SN_ReadOnly", 12, 1 },
|
|
{ "H7MAG", 8, 4 },
|
|
{ "H6GS", 6, 2 },
|
|
{ "H6SN_ReadWrite", 5, 1 },
|
|
{ "H6SN_ReadOnly", 4, 1 },
|
|
{ "H6MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9", 0x3fadc, 0 },
|
|
{ "H9GS", 14, 2 },
|
|
{ "H9SN_ReadWrite", 13, 1 },
|
|
{ "H9SN_ReadOnly", 12, 1 },
|
|
{ "H9MAG", 8, 4 },
|
|
{ "H8GS", 6, 2 },
|
|
{ "H8SN_ReadWrite", 5, 1 },
|
|
{ "H8SN_ReadOnly", 4, 1 },
|
|
{ "H8MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11", 0x3fae0, 0 },
|
|
{ "H11GS", 14, 2 },
|
|
{ "H11SN_ReadWrite", 13, 1 },
|
|
{ "H11SN_ReadOnly", 12, 1 },
|
|
{ "H11MAG", 8, 4 },
|
|
{ "H10GS", 6, 2 },
|
|
{ "H10SN_ReadWrite", 5, 1 },
|
|
{ "H10SN_ReadOnly", 4, 1 },
|
|
{ "H10MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_DFE_H12", 0x3fae4, 0 },
|
|
{ "H12GS", 6, 2 },
|
|
{ "H12SN_ReadWrite", 5, 1 },
|
|
{ "H12SN_ReadOnly", 4, 1 },
|
|
{ "H12MAG", 0, 4 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2", 0x3faf8, 0 },
|
|
{ "DFEDACLSSD", 6, 1 },
|
|
{ "SDLSSD", 5, 1 },
|
|
{ "DFEOBSBIAS", 4, 1 },
|
|
{ "GBOFSTLSSD", 3, 1 },
|
|
{ "RXDOBS", 2, 1 },
|
|
{ "ACJZPT", 1, 1 },
|
|
{ "ACJZNT", 0, 1 },
|
|
{ "MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1", 0x3fafc, 0 },
|
|
{ "PHSLOCK", 10, 1 },
|
|
{ "TESTMODE", 9, 1 },
|
|
{ "CALMODE", 8, 1 },
|
|
{ "AMPSEL", 7, 1 },
|
|
{ "WHICHNRZ", 6, 1 },
|
|
{ "BANKA", 5, 1 },
|
|
{ "BANKB", 4, 1 },
|
|
{ "ACJPDP", 3, 1 },
|
|
{ "ACJPDN", 2, 1 },
|
|
{ "LSSDT", 1, 1 },
|
|
{ "MTHOLD", 0, 1 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_mc_0_regs[] = {
|
|
{ "MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS", 0x47000, 0 },
|
|
{ "DP18_PLL_LOCK", 1, 15 },
|
|
{ "MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS", 0x47004, 0 },
|
|
{ "AD32S_PLL_LOCK", 14, 2 },
|
|
{ "MC_DDRPHY_PC_RANK_PAIR0", 0x47008, 0 },
|
|
{ "RANK_PAIR0_PRI", 13, 3 },
|
|
{ "RANK_PAIR0_PRI_V", 12, 1 },
|
|
{ "RANK_PAIR0_SEC", 9, 3 },
|
|
{ "RANK_PAIR0_SEC_V", 8, 1 },
|
|
{ "RANK_PAIR1_PRI", 5, 3 },
|
|
{ "RANK_PAIR1_PRI_V", 4, 1 },
|
|
{ "RANK_PAIR1_SEC", 1, 3 },
|
|
{ "RANK_PAIR1_SEC_V", 0, 1 },
|
|
{ "MC_DDRPHY_PC_RANK_PAIR1", 0x4700c, 0 },
|
|
{ "RANK_PAIR2_PRI", 13, 3 },
|
|
{ "RANK_PAIR2_PRI_V", 12, 1 },
|
|
{ "RANK_PAIR2_SEC", 9, 3 },
|
|
{ "RANK_PAIR2_SEC_V", 8, 1 },
|
|
{ "RANK_PAIR3_PRI", 5, 3 },
|
|
{ "RANK_PAIR3_PRI_V", 4, 1 },
|
|
{ "RANK_PAIR3_SEC", 1, 3 },
|
|
{ "RANK_PAIR3_SEC_V", 0, 1 },
|
|
{ "MC_DDRPHY_PC_BASE_CNTR0", 0x47010, 0 },
|
|
{ "MC_DDRPHY_PC_RELOAD_VALUE0", 0x47014, 0 },
|
|
{ "PERIODIC_CAL_REQ_EN", 15, 1 },
|
|
{ "PERIODIC_RELOAD_VALUE0", 0, 15 },
|
|
{ "MC_DDRPHY_PC_BASE_CNTR1", 0x47018, 0 },
|
|
{ "MC_DDRPHY_PC_CAL_TIMER", 0x4701c, 0 },
|
|
{ "MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE", 0x47020, 0 },
|
|
{ "MC_DDRPHY_PC_ZCAL_TIMER", 0x47024, 0 },
|
|
{ "MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE", 0x47028, 0 },
|
|
{ "MC_DDRPHY_PC_PER_CAL_CONFIG", 0x4702c, 0 },
|
|
{ "PER_ENA_RANK_PAIR", 12, 4 },
|
|
{ "PER_ENA_ZCAL", 11, 1 },
|
|
{ "PER_ENA_SYSCLK_ALIGN", 10, 1 },
|
|
{ "ENA_PER_READ_CTR", 9, 1 },
|
|
{ "ENA_PER_RDCLK_ALIGN", 8, 1 },
|
|
{ "ENA_PER_DQS_ALIGN", 7, 1 },
|
|
{ "PER_NEXT_RANK_PAIR", 5, 2 },
|
|
{ "FAST_SIM_PER_CNTR", 4, 1 },
|
|
{ "START_INIT_CAL", 3, 1 },
|
|
{ "START_PER_CAL", 2, 1 },
|
|
{ "ABORT_ON_ERR_EN", 1, 1 },
|
|
{ "MC_DDRPHY_PC_PER_ZCAL_CONFIG", 0x4703c, 0 },
|
|
{ "PER_ZCAL_ENA_RANK", 8, 8 },
|
|
{ "PER_ZCAL_NEXT_RANK", 5, 3 },
|
|
{ "START_PER_ZCAL", 4, 1 },
|
|
{ "MC_DDRPHY_PC_CONFIG0", 0x47030, 0 },
|
|
{ "PROTOCOL_DDR", 12, 4 },
|
|
{ "DATA_MUX4_1MODE", 11, 1 },
|
|
{ "DDR4_CMD_SIG_REDUCTION", 9, 1 },
|
|
{ "SYSCLK_2X_MEMINTCLKO", 8, 1 },
|
|
{ "RANK_OVERRIDE", 7, 1 },
|
|
{ "RANK_OVERRIDE_VALUE", 4, 3 },
|
|
{ "LOW_LATENCY", 3, 1 },
|
|
{ "DDR4_BANK_REFRESH", 2, 1 },
|
|
{ "DDR4_VLEVEL_BANK_GROUP", 1, 1 },
|
|
{ "MC_DDRPHY_PC_CONFIG1", 0x47034, 0 },
|
|
{ "WRITE_LATENCY_OFFSET", 12, 4 },
|
|
{ "READ_LATENCY_OFFSET", 8, 4 },
|
|
{ "MEMCTL_CIC_FAST", 7, 1 },
|
|
{ "MEMCTL_CTRN_IGNORE", 6, 1 },
|
|
{ "DISABLE_MEMCTL_CAL", 5, 1 },
|
|
{ "MC_DDRPHY_PC_RESETS", 0x47038, 0 },
|
|
{ "PLL_RESET", 15, 1 },
|
|
{ "SYSCLK_RESET", 14, 1 },
|
|
{ "MC_DDRPHY_PC_ERROR_STATUS0", 0x47048, 0 },
|
|
{ "RC_ERROR", 15, 1 },
|
|
{ "WC_ERROR", 14, 1 },
|
|
{ "SEQ_ERROR", 13, 1 },
|
|
{ "CC_ERROR", 12, 1 },
|
|
{ "APB_ERROR", 11, 1 },
|
|
{ "PC_ERROR", 10, 1 },
|
|
{ "MC_DDRPHY_PC_ERROR_MASK0", 0x4704c, 0 },
|
|
{ "RC_ERROR_MASK", 15, 1 },
|
|
{ "WC_ERROR_MASK", 14, 1 },
|
|
{ "SEQ_ERROR_MASK", 13, 1 },
|
|
{ "CC_ERROR_MASK", 12, 1 },
|
|
{ "APB_ERROR_MASK", 11, 1 },
|
|
{ "PC_ERROR_MASK", 10, 1 },
|
|
{ "MC_DDRPHY_PC_IO_PVT_FET_CONTROL", 0x47050, 0 },
|
|
{ "PVTP", 11, 5 },
|
|
{ "PVTN", 6, 5 },
|
|
{ "PVT_OVERRIDE", 5, 1 },
|
|
{ "ENABLE_ZCAL", 4, 1 },
|
|
{ "MC_DDRPHY_PC_VREF_DRV_CONTROL", 0x47054, 0 },
|
|
{ "VREFDQ0DSGN", 15, 1 },
|
|
{ "VREFDQ0D", 11, 4 },
|
|
{ "VREFDQ1DSGN", 10, 1 },
|
|
{ "VREFDQ1D", 6, 4 },
|
|
{ "MC_DDRPHY_PC_INIT_CAL_CONFIG0", 0x47058, 0 },
|
|
{ "ENA_WR_LEVEL", 15, 1 },
|
|
{ "ENA_INITIAL_PAT_WR", 14, 1 },
|
|
{ "ENA_DQS_ALIGN", 13, 1 },
|
|
{ "ENA_RDCLK_ALIGN", 12, 1 },
|
|
{ "ENA_READ_CTR", 11, 1 },
|
|
{ "ENA_WRITE_CTR", 10, 1 },
|
|
{ "ENA_INITIAL_COARSE_WR", 9, 1 },
|
|
{ "ENA_COARSE_RD", 8, 1 },
|
|
{ "ENA_CUSTOM_RD", 7, 1 },
|
|
{ "ENA_CUSTOM_WR", 6, 1 },
|
|
{ "ABORT_ON_CAL_ERROR", 5, 1 },
|
|
{ "ENA_DIGITAL_EYE", 4, 1 },
|
|
{ "ENA_RANK_PAIR", 0, 4 },
|
|
{ "MC_DDRPHY_PC_INIT_CAL_CONFIG1", 0x4705c, 0 },
|
|
{ "REFRESH_COUNT", 12, 4 },
|
|
{ "REFRESH_CONTROL", 10, 2 },
|
|
{ "REFRESH_ALL_RANKS", 9, 1 },
|
|
{ "REFRESH_INTERVAL", 0, 7 },
|
|
{ "MC_DDRPHY_PC_INIT_CAL_ERROR", 0x47060, 0 },
|
|
{ "ERROR_WR_LEVEL", 15, 1 },
|
|
{ "ERROR_INITIAL_PAT_WRITE", 14, 1 },
|
|
{ "ERROR_DQS_ALIGN", 13, 1 },
|
|
{ "ERROR_RDCLK_ALIGN", 12, 1 },
|
|
{ "ERROR_READ_CTR", 11, 1 },
|
|
{ "ERROR_WRITE_CTR", 10, 1 },
|
|
{ "ERROR_INITIAL_COARSE_WR", 9, 1 },
|
|
{ "ERROR_COARSE_RD", 8, 1 },
|
|
{ "ERROR_CUSTOM_RD", 7, 1 },
|
|
{ "ERROR_CUSTOM_WR", 6, 1 },
|
|
{ "ERROR_DIGITAL_EYE", 5, 1 },
|
|
{ "ERROR_RANK_PAIR", 0, 4 },
|
|
{ "MC_DDRPHY_PC_INIT_CAL_MASK", 0x47068, 0 },
|
|
{ "ERROR_WR_LEVEL_MASK", 15, 1 },
|
|
{ "ERROR_INITIAL_PAT_WRITE_MASK", 14, 1 },
|
|
{ "ERROR_DQS_ALIGN_MASK", 13, 1 },
|
|
{ "ERROR_RDCLK_ALIGN_MASK", 12, 1 },
|
|
{ "ERROR_READ_CTR_MASK", 11, 1 },
|
|
{ "ERROR_WRITE_CTR_MASK", 10, 1 },
|
|
{ "ERROR_INITIAL_COARSE_WR_MASK", 9, 1 },
|
|
{ "ERROR_COARSE_RD_MASK", 8, 1 },
|
|
{ "ERROR_CUSTOM_RD_MASK", 7, 1 },
|
|
{ "ERROR_CUSTOM_WR_MASK", 6, 1 },
|
|
{ "ERROR_DIGITAL_EYE_MASK", 5, 1 },
|
|
{ "MC_DDRPHY_PC_INIT_CAL_STATUS", 0x47064, 0 },
|
|
{ "INIT_CAL_COMPLETE", 12, 4 },
|
|
{ "MC_DDRPHY_PC_IO_PVT_FET_STATUS", 0x4706c, 0 },
|
|
{ "PVTP", 11, 5 },
|
|
{ "PVTN", 6, 5 },
|
|
{ "MC_DDRPHY_PC_MR0_PRI_RP", 0x47070, 0 },
|
|
{ "MC_DDRPHY_PC_MR1_PRI_RP", 0x47074, 0 },
|
|
{ "MC_DDRPHY_PC_MR2_PRI_RP", 0x47078, 0 },
|
|
{ "MC_DDRPHY_PC_MR3_PRI_RP", 0x4707c, 0 },
|
|
{ "MC_DDRPHY_PC_MR0_SEC_RP", 0x47080, 0 },
|
|
{ "MC_DDRPHY_PC_MR1_SEC_RP", 0x47084, 0 },
|
|
{ "MC_DDRPHY_PC_MR2_SEC_RP", 0x47088, 0 },
|
|
{ "MC_DDRPHY_PC_MR3_SEC_RP", 0x4708c, 0 },
|
|
{ "MC_DDRPHY_PC_RANK_GROUP", 0x47044, 0 },
|
|
{ "ADDR_MIRROR_RP0_PRI", 15, 1 },
|
|
{ "ADDR_MIRROR_RP0_SEC", 14, 1 },
|
|
{ "ADDR_MIRROR_RP1_PRI", 13, 1 },
|
|
{ "ADDR_MIRROR_RP1_SEC", 12, 1 },
|
|
{ "ADDR_MIRROR_RP2_PRI", 11, 1 },
|
|
{ "ADDR_MIRROR_RP2_SEC", 10, 1 },
|
|
{ "ADDR_MIRROR_RP3_PRI", 9, 1 },
|
|
{ "ADDR_MIRROR_RP3_SEC", 8, 1 },
|
|
{ "RANK_GROUPING", 6, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_BIT_ENABLE", 0x45000, 0 },
|
|
{ "BIT_ENABLE_0_11", 4, 12 },
|
|
{ "BIT_ENABLE_12_15", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE", 0x45004, 0 },
|
|
{ "DI_ADR0_ADR1", 15, 1 },
|
|
{ "DI_ADR2_ADR3", 14, 1 },
|
|
{ "DI_ADR4_ADR5", 13, 1 },
|
|
{ "DI_ADR6_ADR7", 12, 1 },
|
|
{ "DI_ADR8_ADR9", 11, 1 },
|
|
{ "DI_ADR10_ADR11", 10, 1 },
|
|
{ "DI_ADR12_ADR13", 9, 1 },
|
|
{ "DI_ADR14_ADR15", 8, 1 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY0", 0x45010, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY1", 0x45014, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY2", 0x45018, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY3", 0x4501c, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY4", 0x45020, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY5", 0x45024, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY6", 0x45028, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY7", 0x4502c, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL", 0x45030, 0 },
|
|
{ "ADR_TEST_LANE_PAIR_FAIL", 8, 8 },
|
|
{ "ADR_TEST_DATA_EN", 7, 1 },
|
|
{ "DADR_TEST_MODE", 5, 2 },
|
|
{ "ADR_TEST_4TO1_MODE", 4, 1 },
|
|
{ "ADR_TEST_RESET", 3, 1 },
|
|
{ "ADR_TEST_GEN_EN", 2, 1 },
|
|
{ "ADR_TEST_CLEAR_ERROR", 1, 1 },
|
|
{ "ADR_TEST_CHECK_EN", 0, 1 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0", 0x45040, 0 },
|
|
{ "EN_SLICE_N_WR_0", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1", 0x45044, 0 },
|
|
{ "EN_SLICE_N_WR_1", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2", 0x45048, 0 },
|
|
{ "EN_SLICE_N_WR_2", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3", 0x4504c, 0 },
|
|
{ "EN_SLICE_N_WR_3", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0", 0x45050, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1", 0x45054, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2", 0x45058, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3", 0x4505c, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0", 0x45080, 0 },
|
|
{ "SLICE_SEL_REG_BITS0_1", 14, 2 },
|
|
{ "SLICE_SEL_REG_BITS2_3", 12, 2 },
|
|
{ "SLICE_SEL_REG_BITS4_5", 10, 2 },
|
|
{ "SLICE_SEL_REG_BITS6_7", 8, 2 },
|
|
{ "SLICE_SEL_REG_BITS8_9", 6, 2 },
|
|
{ "SLICE_SEL_REG_BITS10_11", 4, 2 },
|
|
{ "SLICE_SEL_REG_BITS12_13", 2, 2 },
|
|
{ "SLICE_SEL_REG_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1", 0x45084, 0 },
|
|
{ "SLICE_SEL_REG_BITS0_1", 14, 2 },
|
|
{ "SLICE_SEL_REG_BITS2_3", 12, 2 },
|
|
{ "SLICE_SEL_REG_BITS4_5", 10, 2 },
|
|
{ "SLICE_SEL_REG_BITS6_7", 8, 2 },
|
|
{ "SLICE_SEL_REG_BITS8_9", 6, 2 },
|
|
{ "SLICE_SEL_REG_BITS10_11", 4, 2 },
|
|
{ "SLICE_SEL_REG_BITS12_13", 2, 2 },
|
|
{ "SLICE_SEL_REG_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE", 0x45060, 0 },
|
|
{ "POST_CURSOR0", 12, 4 },
|
|
{ "POST_CURSOR1", 8, 4 },
|
|
{ "POST_CURSOR2", 4, 4 },
|
|
{ "POST_CURSOR3", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0", 0x450a0, 0 },
|
|
{ "POST_CUR_SEL_BITS0_1", 14, 2 },
|
|
{ "POST_CUR_SEL_BITS2_3", 12, 2 },
|
|
{ "POST_CUR_SEL_BITS4_5", 10, 2 },
|
|
{ "POST_CUR_SEL_BITS6_7", 8, 2 },
|
|
{ "POST_CUR_SEL_BITS8_9", 6, 2 },
|
|
{ "POST_CUR_SEL_BITS10_11", 4, 2 },
|
|
{ "POST_CUR_SEL_BITS12_13", 2, 2 },
|
|
{ "POST_CUR_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1", 0x450a4, 0 },
|
|
{ "POST_CUR_SEL_BITS0_1", 14, 2 },
|
|
{ "POST_CUR_SEL_BITS2_3", 12, 2 },
|
|
{ "POST_CUR_SEL_BITS4_5", 10, 2 },
|
|
{ "POST_CUR_SEL_BITS6_7", 8, 2 },
|
|
{ "POST_CUR_SEL_BITS8_9", 6, 2 },
|
|
{ "POST_CUR_SEL_BITS10_11", 4, 2 },
|
|
{ "POST_CUR_SEL_BITS12_13", 2, 2 },
|
|
{ "POST_CUR_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE", 0x45068, 0 },
|
|
{ "SLEW_CTL0", 12, 4 },
|
|
{ "SLEW_CTL1", 8, 4 },
|
|
{ "SLEW_CTL2", 4, 4 },
|
|
{ "SLEW_CTL3", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0", 0x450a8, 0 },
|
|
{ "SLEW_CTL_SEL_BITS0_1", 14, 2 },
|
|
{ "SLEW_CTL_SEL_BITS2_3", 12, 2 },
|
|
{ "SLEW_CTL_SEL_BITS4_5", 10, 2 },
|
|
{ "SLEW_CTL_SEL_BITS6_7", 8, 2 },
|
|
{ "SLEW_CTL_SEL_BITS8_9", 6, 2 },
|
|
{ "SLEW_CTL_SEL_BITS10_11", 4, 2 },
|
|
{ "SLEW_CTL_SEL_BITS12_13", 2, 2 },
|
|
{ "SLEW_CTL_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1", 0x450ac, 0 },
|
|
{ "SLEW_CTL_SEL_BITS0_1", 14, 2 },
|
|
{ "SLEW_CTL_SEL_BITS2_3", 12, 2 },
|
|
{ "SLEW_CTL_SEL_BITS4_5", 10, 2 },
|
|
{ "SLEW_CTL_SEL_BITS6_7", 8, 2 },
|
|
{ "SLEW_CTL_SEL_BITS8_9", 6, 2 },
|
|
{ "SLEW_CTL_SEL_BITS10_11", 4, 2 },
|
|
{ "SLEW_CTL_SEL_BITS12_13", 2, 2 },
|
|
{ "SLEW_CTL_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_POWERDOWN_2", 0x450b0, 0 },
|
|
{ "ADR_LANE_0_11_PD", 4, 12 },
|
|
{ "ADR_LANE_12_15_PD", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_BIT_ENABLE", 0x45200, 0 },
|
|
{ "BIT_ENABLE_0_11", 4, 12 },
|
|
{ "BIT_ENABLE_12_15", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE", 0x45204, 0 },
|
|
{ "DI_ADR0_ADR1", 15, 1 },
|
|
{ "DI_ADR2_ADR3", 14, 1 },
|
|
{ "DI_ADR4_ADR5", 13, 1 },
|
|
{ "DI_ADR6_ADR7", 12, 1 },
|
|
{ "DI_ADR8_ADR9", 11, 1 },
|
|
{ "DI_ADR10_ADR11", 10, 1 },
|
|
{ "DI_ADR12_ADR13", 9, 1 },
|
|
{ "DI_ADR14_ADR15", 8, 1 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY0", 0x45210, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY1", 0x45214, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY2", 0x45218, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY3", 0x4521c, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY4", 0x45220, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY5", 0x45224, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY6", 0x45228, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY7", 0x4522c, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL", 0x45230, 0 },
|
|
{ "ADR_TEST_LANE_PAIR_FAIL", 8, 8 },
|
|
{ "ADR_TEST_DATA_EN", 7, 1 },
|
|
{ "DADR_TEST_MODE", 5, 2 },
|
|
{ "ADR_TEST_4TO1_MODE", 4, 1 },
|
|
{ "ADR_TEST_RESET", 3, 1 },
|
|
{ "ADR_TEST_GEN_EN", 2, 1 },
|
|
{ "ADR_TEST_CLEAR_ERROR", 1, 1 },
|
|
{ "ADR_TEST_CHECK_EN", 0, 1 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0", 0x45240, 0 },
|
|
{ "EN_SLICE_N_WR_0", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1", 0x45244, 0 },
|
|
{ "EN_SLICE_N_WR_1", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2", 0x45248, 0 },
|
|
{ "EN_SLICE_N_WR_2", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3", 0x4524c, 0 },
|
|
{ "EN_SLICE_N_WR_3", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0", 0x45250, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1", 0x45254, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2", 0x45258, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3", 0x4525c, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0", 0x45280, 0 },
|
|
{ "SLICE_SEL_REG_BITS0_1", 14, 2 },
|
|
{ "SLICE_SEL_REG_BITS2_3", 12, 2 },
|
|
{ "SLICE_SEL_REG_BITS4_5", 10, 2 },
|
|
{ "SLICE_SEL_REG_BITS6_7", 8, 2 },
|
|
{ "SLICE_SEL_REG_BITS8_9", 6, 2 },
|
|
{ "SLICE_SEL_REG_BITS10_11", 4, 2 },
|
|
{ "SLICE_SEL_REG_BITS12_13", 2, 2 },
|
|
{ "SLICE_SEL_REG_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1", 0x45284, 0 },
|
|
{ "SLICE_SEL_REG_BITS0_1", 14, 2 },
|
|
{ "SLICE_SEL_REG_BITS2_3", 12, 2 },
|
|
{ "SLICE_SEL_REG_BITS4_5", 10, 2 },
|
|
{ "SLICE_SEL_REG_BITS6_7", 8, 2 },
|
|
{ "SLICE_SEL_REG_BITS8_9", 6, 2 },
|
|
{ "SLICE_SEL_REG_BITS10_11", 4, 2 },
|
|
{ "SLICE_SEL_REG_BITS12_13", 2, 2 },
|
|
{ "SLICE_SEL_REG_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE", 0x45260, 0 },
|
|
{ "POST_CURSOR0", 12, 4 },
|
|
{ "POST_CURSOR1", 8, 4 },
|
|
{ "POST_CURSOR2", 4, 4 },
|
|
{ "POST_CURSOR3", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0", 0x452a0, 0 },
|
|
{ "POST_CUR_SEL_BITS0_1", 14, 2 },
|
|
{ "POST_CUR_SEL_BITS2_3", 12, 2 },
|
|
{ "POST_CUR_SEL_BITS4_5", 10, 2 },
|
|
{ "POST_CUR_SEL_BITS6_7", 8, 2 },
|
|
{ "POST_CUR_SEL_BITS8_9", 6, 2 },
|
|
{ "POST_CUR_SEL_BITS10_11", 4, 2 },
|
|
{ "POST_CUR_SEL_BITS12_13", 2, 2 },
|
|
{ "POST_CUR_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1", 0x452a4, 0 },
|
|
{ "POST_CUR_SEL_BITS0_1", 14, 2 },
|
|
{ "POST_CUR_SEL_BITS2_3", 12, 2 },
|
|
{ "POST_CUR_SEL_BITS4_5", 10, 2 },
|
|
{ "POST_CUR_SEL_BITS6_7", 8, 2 },
|
|
{ "POST_CUR_SEL_BITS8_9", 6, 2 },
|
|
{ "POST_CUR_SEL_BITS10_11", 4, 2 },
|
|
{ "POST_CUR_SEL_BITS12_13", 2, 2 },
|
|
{ "POST_CUR_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE", 0x45268, 0 },
|
|
{ "SLEW_CTL0", 12, 4 },
|
|
{ "SLEW_CTL1", 8, 4 },
|
|
{ "SLEW_CTL2", 4, 4 },
|
|
{ "SLEW_CTL3", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0", 0x452a8, 0 },
|
|
{ "SLEW_CTL_SEL_BITS0_1", 14, 2 },
|
|
{ "SLEW_CTL_SEL_BITS2_3", 12, 2 },
|
|
{ "SLEW_CTL_SEL_BITS4_5", 10, 2 },
|
|
{ "SLEW_CTL_SEL_BITS6_7", 8, 2 },
|
|
{ "SLEW_CTL_SEL_BITS8_9", 6, 2 },
|
|
{ "SLEW_CTL_SEL_BITS10_11", 4, 2 },
|
|
{ "SLEW_CTL_SEL_BITS12_13", 2, 2 },
|
|
{ "SLEW_CTL_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1", 0x452ac, 0 },
|
|
{ "SLEW_CTL_SEL_BITS0_1", 14, 2 },
|
|
{ "SLEW_CTL_SEL_BITS2_3", 12, 2 },
|
|
{ "SLEW_CTL_SEL_BITS4_5", 10, 2 },
|
|
{ "SLEW_CTL_SEL_BITS6_7", 8, 2 },
|
|
{ "SLEW_CTL_SEL_BITS8_9", 6, 2 },
|
|
{ "SLEW_CTL_SEL_BITS10_11", 4, 2 },
|
|
{ "SLEW_CTL_SEL_BITS12_13", 2, 2 },
|
|
{ "SLEW_CTL_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_POWERDOWN_2", 0x452b0, 0 },
|
|
{ "ADR_LANE_0_11_PD", 4, 12 },
|
|
{ "ADR_LANE_12_15_PD", 0, 4 },
|
|
{ "MC_DDRPHY_ADR_PLL_VREG_CONFIG_0", 0x460c0, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_ADR_PLL_VREG_CONFIG_1", 0x460c4, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "VREG_VREGSPARE", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "INTERP_SIG_SLEW_0_3", 1, 4 },
|
|
{ "ANALOG_WRAPON", 0, 1 },
|
|
{ "MC_DDRPHY_ADR_SYSCLK_CNTL_PR", 0x460c8, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESE", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "CE0DLTVCC", 0, 2 },
|
|
{ "MC_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET", 0x460cc, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_ADR_SYSCLK_PR_VALUE_RO", 0x460d0, 0 },
|
|
{ "SLEW_LATE_SAMPLE", 15, 1 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "BB_LOCK", 7, 1 },
|
|
{ "SLEW_EARLY_SAMPLE", 6, 1 },
|
|
{ "SLEW_DONE_STATUS", 4, 2 },
|
|
{ "SLEW_CNTL", 0, 4 },
|
|
{ "MC_DDRPHY_ADR_GMTEST_ATEST_CNTL", 0x460d4, 0 },
|
|
{ "FLUSH", 15, 1 },
|
|
{ "GIANT_MUX_TEST_EN", 14, 1 },
|
|
{ "GIANT_MUX_TEST_VAL", 13, 1 },
|
|
{ "HS_PROBE_A_SEL_", 8, 4 },
|
|
{ "HS_PROBE_B_SEL_", 4, 4 },
|
|
{ "ATEST1CTL0", 3, 1 },
|
|
{ "ATEST1CTL1", 2, 1 },
|
|
{ "ATEST1CTL2", 1, 1 },
|
|
{ "ATEST1CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A0", 0x460d8, 0 },
|
|
{ "MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A1", 0x460dc, 0 },
|
|
{ "MC_DDRPHY_ADR_POWERDOWN_1", 0x460e0, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "ADR_RX_PD", 4, 1 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "DVCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_ADR_SLEW_CAL_CNTL", 0x460e4, 0 },
|
|
{ "SLEW_CAL_ENABLE", 15, 1 },
|
|
{ "SLEW_CAL_START", 14, 1 },
|
|
{ "SLEW_CAL_OVERRIDE_EN", 12, 1 },
|
|
{ "SLEW_CAL_OVERRIDE", 8, 4 },
|
|
{ "SLEW_TARGET_PR_OFFSET", 0, 5 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44000, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44004, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "WRAPSEL", 5, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x441f0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x441f4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44008, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4400c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44010, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44014, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x441f8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44018, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4401c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x441cc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x441d0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x440c0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x440c4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44024, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44170, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44174, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x440e0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x440e4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x440e8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x440ec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x440f0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x440f4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x440f8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x440fc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44100, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44104, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44108, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4410c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44110, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44114, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44118, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4411c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44120, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44124, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44128, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4412c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44130, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44134, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44138, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4413c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44140, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44144, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44148, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4414c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44150, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44154, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44158, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4415c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44160, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44164, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44168, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4416c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44030, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44034, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x441c0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x441c4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x441c8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44180, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44184, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44188, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4418c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44190, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44194, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44198, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4419c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x441a0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x441a4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x441a8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x441ac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44028, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44038, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4403c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44040, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44044, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4404c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44050, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44054, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4405c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44060, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "DDONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44064, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44068, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4406c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44070, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x441d8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x441dc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x441e0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x441e8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x441e4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x441ec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x441d4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44074, 0 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44020, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x440c8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x440cc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x440d0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44078, 0 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x440d4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x440d8, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x441b4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x441b8, 0 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x440dc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4402c, 0 },
|
|
{ "HS_PROBE_A_SEL", 11, 5 },
|
|
{ "HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x441fc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "ADR_RX_PD", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "DVCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44048, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DYN_MCTERM_CNTL_EN", 14, 1 },
|
|
{ "DYN_RX_GATE_CNTL_EN", 13, 1 },
|
|
{ "CALGATE_ON", 12, 1 },
|
|
{ "PER_RDCLK_UPDATE_DIS", 11, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44200, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44204, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "WRAPSEL", 5, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x443f0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x443f4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44208, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4420c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44210, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44214, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x443f8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44218, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4421c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x443cc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x443d0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x442c0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x442c4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44224, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44370, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44374, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x442e0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x442e4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x442e8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x442ec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x442f0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x442f4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x442f8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x442fc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44300, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44304, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44308, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4430c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44310, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44314, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44318, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4431c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44320, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44324, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44328, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4432c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44330, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44334, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44338, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4433c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44340, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44344, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44348, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4434c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44350, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44354, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44358, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4435c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44360, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44364, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44368, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4436c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44230, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44234, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x443c0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x443c4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x443c8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44380, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44384, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44388, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4438c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44390, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44394, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44398, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4439c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x443a0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x443a4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x443a8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x443ac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44228, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44238, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4423c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44240, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44244, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4424c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44250, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44254, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4425c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44260, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "DDONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44264, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44268, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4426c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44270, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x443d8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x443dc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x443e0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x443e8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x443e4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x443ec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x443d4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44274, 0 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44220, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x442c8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x442cc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x442d0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44278, 0 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x442d4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x442d8, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x443b4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x443b8, 0 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x442dc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4422c, 0 },
|
|
{ "HS_PROBE_A_SEL", 11, 5 },
|
|
{ "HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x443fc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "ADR_RX_PD", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "DVCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44248, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DYN_MCTERM_CNTL_EN", 14, 1 },
|
|
{ "DYN_RX_GATE_CNTL_EN", 13, 1 },
|
|
{ "CALGATE_ON", 12, 1 },
|
|
{ "PER_RDCLK_UPDATE_DIS", 11, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44400, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44404, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "WRAPSEL", 5, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x445f0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x445f4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44408, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4440c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44410, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44414, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x445f8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44418, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4441c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x445cc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x445d0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x444c0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x444c4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44424, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44570, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44574, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x444e0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x444e4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x444e8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x444ec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x444f0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x444f4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x444f8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x444fc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44500, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44504, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44508, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4450c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44510, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44514, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44518, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4451c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44520, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44524, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44528, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4452c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44530, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44534, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44538, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4453c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44540, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44544, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44548, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4454c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44550, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44554, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44558, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4455c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44560, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44564, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44568, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4456c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44430, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44434, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x445c0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x445c4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x445c8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44580, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44584, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44588, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4458c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44590, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44594, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44598, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4459c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x445a0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x445a4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x445a8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x445ac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44428, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44438, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4443c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44440, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44444, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4444c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44450, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44454, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4445c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44460, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "DDONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44464, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44468, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4446c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44470, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x445d8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x445dc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x445e0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x445e8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x445e4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x445ec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x445d4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44474, 0 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44420, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x444c8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x444cc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x444d0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44478, 0 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x444d4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x444d8, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x445b4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x445b8, 0 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x444dc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4442c, 0 },
|
|
{ "HS_PROBE_A_SEL", 11, 5 },
|
|
{ "HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x445fc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "ADR_RX_PD", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "DVCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44448, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DYN_MCTERM_CNTL_EN", 14, 1 },
|
|
{ "DYN_RX_GATE_CNTL_EN", 13, 1 },
|
|
{ "CALGATE_ON", 12, 1 },
|
|
{ "PER_RDCLK_UPDATE_DIS", 11, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44600, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44604, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "WRAPSEL", 5, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x447f0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x447f4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44608, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4460c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44610, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44614, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x447f8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44618, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4461c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x447cc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x447d0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x446c0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x446c4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44624, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44770, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44774, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x446e0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x446e4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x446e8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x446ec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x446f0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x446f4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x446f8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x446fc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44700, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44704, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44708, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4470c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44710, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44714, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44718, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4471c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44720, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44724, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44728, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4472c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44730, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44734, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44738, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4473c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44740, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44744, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44748, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4474c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44750, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44754, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44758, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4475c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44760, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44764, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44768, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4476c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44630, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44634, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x447c0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x447c4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x447c8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44780, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44784, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44788, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4478c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44790, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44794, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44798, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4479c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x447a0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x447a4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x447a8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x447ac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44628, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44638, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4463c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44640, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44644, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4464c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44650, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44654, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4465c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44660, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "DDONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44664, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44668, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4466c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44670, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x447d8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x447dc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x447e0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x447e8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x447e4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x447ec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x447d4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44674, 0 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44620, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x446c8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x446cc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x446d0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44678, 0 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x446d4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x446d8, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x447b4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x447b8, 0 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x446dc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4462c, 0 },
|
|
{ "HS_PROBE_A_SEL", 11, 5 },
|
|
{ "HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x447fc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "ADR_RX_PD", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "DVCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44648, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DYN_MCTERM_CNTL_EN", 14, 1 },
|
|
{ "DYN_RX_GATE_CNTL_EN", 13, 1 },
|
|
{ "CALGATE_ON", 12, 1 },
|
|
{ "PER_RDCLK_UPDATE_DIS", 11, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x44800, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x44804, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "WRAPSEL", 5, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x449f0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x449f4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x44808, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4480c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x44810, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x44814, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x449f8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x44818, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4481c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x449cc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x449d0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x448c0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x448c4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x44824, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x44970, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x44974, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x448e0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x448e4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x448e8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x448ec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x448f0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x448f4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x448f8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x448fc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x44900, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x44904, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x44908, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4490c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x44910, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x44914, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x44918, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4491c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x44920, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x44924, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x44928, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4492c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x44930, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x44934, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x44938, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4493c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x44940, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x44944, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x44948, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4494c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x44950, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x44954, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x44958, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4495c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x44960, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x44964, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x44968, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4496c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x44830, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x44834, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x449c0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x449c4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x449c8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x44980, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x44984, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x44988, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4498c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x44990, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x44994, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x44998, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4499c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x449a0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x449a4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x449a8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x449ac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x44828, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x44838, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4483c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x44840, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x44844, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4484c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x44850, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x44854, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4485c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x44860, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "DDONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x44864, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x44868, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4486c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x44870, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x449d8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x449dc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x449e0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x449e8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x449e4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x449ec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x449d4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x44874, 0 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x44820, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x448c8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x448cc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x448d0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x44878, 0 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x448d4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x448d8, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x449b4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x449b8, 0 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x448dc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4482c, 0 },
|
|
{ "HS_PROBE_A_SEL", 11, 5 },
|
|
{ "HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x449fc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "ADR_RX_PD", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "DVCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x44848, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DYN_MCTERM_CNTL_EN", 14, 1 },
|
|
{ "DYN_RX_GATE_CNTL_EN", 13, 1 },
|
|
{ "CALGATE_ON", 12, 1 },
|
|
{ "PER_RDCLK_UPDATE_DIS", 11, 1 },
|
|
{ "MC_DDRPHY_SEQ_RD_WR_DATA0", 0x47200, 0 },
|
|
{ "MC_DDRPHY_SEQ_RD_WR_DATA1", 0x47204, 0 },
|
|
{ "MC_DDRPHY_SEQ_CONFIG0", 0x47208, 0 },
|
|
{ "MPR_PATTERN_BIT", 15, 1 },
|
|
{ "TWO_CYCLE_ADDR_EN", 14, 1 },
|
|
{ "MR_MASK_EN", 10, 4 },
|
|
{ "MC_DDRPHY_SEQ_RESERVED_ADDR0", 0x4720c, 0 },
|
|
{ "MC_DDRPHY_SEQ_RESERVED_ADDR1", 0x47210, 0 },
|
|
{ "MC_DDRPHY_SEQ_RESERVED_ADDR2", 0x47214, 0 },
|
|
{ "MC_DDRPHY_SEQ_RESERVED_ADDR3", 0x47218, 0 },
|
|
{ "MC_DDRPHY_SEQ_RESERVED_ADDR4", 0x4721c, 0 },
|
|
{ "MC_DDRPHY_SEQ_ERROR_STATUS0", 0x47220, 0 },
|
|
{ "MULTIPLE_REQ_ERROR", 15, 1 },
|
|
{ "INVALID_REQTYPE_ERRO", 14, 1 },
|
|
{ "EARLY_REQ_ERROR", 13, 1 },
|
|
{ "MULTIPLE_REQ_SOURCE", 10, 3 },
|
|
{ "INVALID_REQTYPE", 6, 4 },
|
|
{ "INVALID_REQ_SOURCE", 3, 3 },
|
|
{ "EARLY_REQ_SOURCE", 0, 3 },
|
|
{ "MC_DDRPHY_SEQ_ERROR_MASK0", 0x47224, 0 },
|
|
{ "MULT_REQ_ERR_MASK", 15, 1 },
|
|
{ "INVALID_REQTYPE_ERR_MASK", 14, 1 },
|
|
{ "EARLY_REQ_ERR_MASK", 13, 1 },
|
|
{ "MC_DDRPHY_SEQ_ODT_WR_CONFIG0", 0x47228, 0 },
|
|
{ "ODT_WR_VALUES_BITS0_7", 8, 8 },
|
|
{ "ODT_WR_VALUES_BITS8_15", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_WR_CONFIG1", 0x4722c, 0 },
|
|
{ "ODT_WR_VALUES_BITS0_7", 8, 8 },
|
|
{ "ODT_WR_VALUES_BITS8_15", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_WR_CONFIG2", 0x47230, 0 },
|
|
{ "ODT_WR_VALUES_BITS0_7", 8, 8 },
|
|
{ "ODT_WR_VALUES_BITS8_15", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_WR_CONFIG3", 0x47234, 0 },
|
|
{ "ODT_WR_VALUES_BITS0_7", 8, 8 },
|
|
{ "ODT_WR_VALUES_BITS8_15", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_RD_CONFIG0", 0x47238, 0 },
|
|
{ "ODT_RD_VALUES_x2", 8, 8 },
|
|
{ "ODT_RD_VALUES_x2plus1", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_RD_CONFIG1", 0x4723c, 0 },
|
|
{ "ODT_RD_VALUES_x2", 8, 8 },
|
|
{ "ODT_RD_VALUES_x2plus1", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_RD_CONFIG2", 0x47240, 0 },
|
|
{ "ODT_RD_VALUES_x2", 8, 8 },
|
|
{ "ODT_RD_VALUES_x2plus1", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_RD_CONFIG3", 0x47244, 0 },
|
|
{ "ODT_RD_VALUES_x2", 8, 8 },
|
|
{ "ODT_RD_VALUES_x2plus1", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_MEM_TIMING_PARAM0", 0x47248, 0 },
|
|
{ "TMOD_CYCLES", 12, 4 },
|
|
{ "TRCD_CYCLES", 8, 4 },
|
|
{ "TRP_CYCLES", 4, 4 },
|
|
{ "TRFC_CYCLES", 0, 4 },
|
|
{ "MC_DDRPHY_SEQ_MEM_TIMING_PARAM1", 0x4724c, 0 },
|
|
{ "TZQINIT_CYCLES", 12, 4 },
|
|
{ "TZQCS_CYCLES", 8, 4 },
|
|
{ "TWLDQSEN_CYCLES", 4, 4 },
|
|
{ "TWRMRD_CYCLES", 0, 4 },
|
|
{ "MC_DDRPHY_SEQ_MEM_TIMING_PARAM2", 0x47250, 0 },
|
|
{ "TODTLON_OFF_CYCLES", 12, 4 },
|
|
{ "TRC_CYCLES", 8, 4 },
|
|
{ "TMRSC_CYCLES", 4, 4 },
|
|
{ "MC_DDRPHY_WC_CONFIG0", 0x47600, 0 },
|
|
{ "TWLO_TWLOE", 8, 8 },
|
|
{ "WL_ONE_DQS_PULSE", 7, 1 },
|
|
{ "FW_WR_RD", 1, 6 },
|
|
{ "CUSTOM_INIT_WRITE", 0, 1 },
|
|
{ "MC_DDRPHY_WC_CONFIG1", 0x47604, 0 },
|
|
{ "BIG_STEP", 12, 4 },
|
|
{ "SMALL_STEP", 9, 3 },
|
|
{ "WR_PRE_DLY", 3, 6 },
|
|
{ "MC_DDRPHY_WC_CONFIG2", 0x47608, 0 },
|
|
{ "NUM_VALID_SAMPLES", 12, 4 },
|
|
{ "FW_RD_WR", 6, 6 },
|
|
{ "EN_RESET_WR_DELAY_WL", 0, 1 },
|
|
{ "MC_DDRPHY_WC_CONFIG3", 0x47614, 0 },
|
|
{ "DDR4_MRS_CMD_DQ_EN", 15, 1 },
|
|
{ "MRS_CMD_DQ_ON", 9, 6 },
|
|
{ "MRS_CMD_DQ_OFF", 3, 6 },
|
|
{ "MC_DDRPHY_WC_WRCLK_CNTL", 0x47618, 0 },
|
|
{ "WRCLK_CAL_START", 15, 1 },
|
|
{ "WRCLK_CAL_DONE", 14, 1 },
|
|
{ "MC_DDRPHY_WC_ERROR_STATUS0", 0x4760c, 0 },
|
|
{ "WR_CNTL_ERROR", 15, 1 },
|
|
{ "MC_DDRPHY_WC_ERROR_MASK0", 0x47610, 0 },
|
|
{ "WR_CNTL_ERROR_MASK", 15, 1 },
|
|
{ "MC_DDRPHY_RC_CONFIG0", 0x47400, 0 },
|
|
{ "GLOBAL_PHY_OFFSET", 12, 4 },
|
|
{ "ADVANCE_RD_VALID", 11, 1 },
|
|
{ "SINGLE_BIT_MPR_RP0", 6, 1 },
|
|
{ "SINGLE_BIT_MPR_RP1", 5, 1 },
|
|
{ "SINGLE_BIT_MPR_RP2", 4, 1 },
|
|
{ "SINGLE_BIT_MPR_RP3", 3, 1 },
|
|
{ "ALIGN_ON_EVEN_CYCLES", 2, 1 },
|
|
{ "PERFORM_RDCLK_ALIGN", 1, 1 },
|
|
{ "STAGGERED_PATTERN", 0, 1 },
|
|
{ "MC_DDRPHY_RC_CONFIG1", 0x47404, 0 },
|
|
{ "OUTER_LOOP_CNT", 2, 14 },
|
|
{ "MC_DDRPHY_RC_CONFIG2", 0x47408, 0 },
|
|
{ "CONSEQ_PASS", 11, 5 },
|
|
{ "BURST_WINDOW", 5, 2 },
|
|
{ "ALLOW_RD_FIFO_AUTO_R_ESET", 4, 1 },
|
|
{ "MC_DDRPHY_RC_CONFIG3", 0x4741c, 0 },
|
|
{ "FINE_CAL_STEP_SIZE", 13, 3 },
|
|
{ "COARSE_CAL_STEP_SIZE", 9, 4 },
|
|
{ "DQ_SEL_QUAD", 7, 2 },
|
|
{ "DQ_SEL_LANE", 4, 3 },
|
|
{ "MC_DDRPHY_RC_PERIODIC", 0x47420, 0 },
|
|
{ "MC_DDRPHY_RC_ERROR_STATUS0", 0x47414, 0 },
|
|
{ "RD_CNTL_ERROR", 15, 1 },
|
|
{ "MC_DDRPHY_RC_ERROR_MASK0", 0x47418, 0 },
|
|
{ "RD_CNTL_ERROR_MASK", 15, 1 },
|
|
{ "MC_DDRPHY_APB_CONFIG0", 0x47800, 0 },
|
|
{ "DISABLE_PARITY_CHECKER", 15, 1 },
|
|
{ "GENERATE_EVEN_PARITY", 14, 1 },
|
|
{ "FORCE_ON_CLK_GATE", 13, 1 },
|
|
{ "DEBUG_BUS_SEL_LO", 12, 1 },
|
|
{ "DEBUG_BUS_SEL_HI", 8, 4 },
|
|
{ "MC_DDRPHY_APB_ERROR_STATUS0", 0x47804, 0 },
|
|
{ "INVALID_ADDRESS", 15, 1 },
|
|
{ "WR_PAR_ERR", 14, 1 },
|
|
{ "MC_DDRPHY_APB_ERROR_MASK0", 0x47808, 0 },
|
|
{ "INVALID_ADDRESS_MASK", 15, 1 },
|
|
{ "WR_PAR_ERR_MASK", 14, 1 },
|
|
{ "MC_DDRPHY_APB_DP18_POPULATION", 0x4780c, 0 },
|
|
{ "DP18_0_Populated", 15, 1 },
|
|
{ "DP18_1_Populated", 14, 1 },
|
|
{ "DP18_2_Populated", 13, 1 },
|
|
{ "DP18_3_Populated", 12, 1 },
|
|
{ "DP18_4_Populated", 11, 1 },
|
|
{ "DP18_5_Populated", 10, 1 },
|
|
{ "DP18_6_Populated", 9, 1 },
|
|
{ "DP18_7_Populated", 8, 1 },
|
|
{ "DP18_8_Populated", 7, 1 },
|
|
{ "DP18_9_Populated", 6, 1 },
|
|
{ "DP18_10_Populated", 5, 1 },
|
|
{ "DP18_11_Populated", 4, 1 },
|
|
{ "DP18_12_Populated", 3, 1 },
|
|
{ "DP18_13_Populated", 2, 1 },
|
|
{ "DP18_14_Populated", 1, 1 },
|
|
{ "MC_DDRPHY_APB_ADR_POPULATION", 0x47810, 0 },
|
|
{ "ADR16_0_Populated", 15, 1 },
|
|
{ "ADR16_1_Populated", 14, 1 },
|
|
{ "ADR16_2_Populated", 13, 1 },
|
|
{ "ADR16_3_Populated", 12, 1 },
|
|
{ "ADR12_0_Populated", 7, 1 },
|
|
{ "ADR12_1_Populated", 6, 1 },
|
|
{ "ADR12_2_Populated", 5, 1 },
|
|
{ "ADR12_3_Populated", 4, 1 },
|
|
{ "MC_DDRPHY_APB_ATEST_MUX_SEL", 0x47814, 0 },
|
|
{ "ATEST_CNTL", 10, 6 },
|
|
{ "MC_UPCTL_SCFG", 0x40000, 0 },
|
|
{ "bbflags_timing", 8, 4 },
|
|
{ "nfifo_nif1_dis", 6, 1 },
|
|
{ "hw_low_power_en", 0, 1 },
|
|
{ "MC_UPCTL_SCTL", 0x40004, 0 },
|
|
{ "MC_UPCTL_STAT", 0x40008, 0 },
|
|
{ "lp_trig", 4, 3 },
|
|
{ "ctl_stat", 0, 3 },
|
|
{ "MC_UPCTL_INTRSTAT", 0x4000c, 0 },
|
|
{ "parity_intr", 1, 1 },
|
|
{ "ecc_intr", 0, 1 },
|
|
{ "MC_UPCTL_MCMD", 0x40040, 0 },
|
|
{ "start_cmd", 31, 1 },
|
|
{ "cmd_add_del", 24, 4 },
|
|
{ "rank_sel", 20, 4 },
|
|
{ "bank_addr", 17, 3 },
|
|
{ "cmd_addr", 4, 13 },
|
|
{ "cmd_opcode0", 0, 4 },
|
|
{ "MC_UPCTL_POWCTL", 0x40044, 0 },
|
|
{ "MC_UPCTL_POWSTAT", 0x40048, 0 },
|
|
{ "MC_UPCTL_CMDTSTAT", 0x4004c, 0 },
|
|
{ "MC_UPCTL_CMDTSTATEN", 0x40050, 0 },
|
|
{ "MC_UPCTL_MRRCFG0", 0x40060, 0 },
|
|
{ "MC_UPCTL_MRRSTAT0", 0x40064, 0 },
|
|
{ "mrrstat_beat3", 24, 8 },
|
|
{ "mrrstat_beat2", 16, 8 },
|
|
{ "mrrstat_beat1", 8, 8 },
|
|
{ "mrrstat_beat0", 0, 8 },
|
|
{ "MC_UPCTL_MRRSTAT1", 0x40068, 0 },
|
|
{ "mrrstat_beat7", 24, 8 },
|
|
{ "mrrstat_beat6", 16, 8 },
|
|
{ "mrrstat_beat5", 8, 8 },
|
|
{ "mrrstat_beat4", 0, 8 },
|
|
{ "MC_UPCTL_MCFG1", 0x4007c, 0 },
|
|
{ "hw_exit_idle_en", 31, 1 },
|
|
{ "hw_idle", 16, 8 },
|
|
{ "sr_idle", 0, 8 },
|
|
{ "MC_UPCTL_MCFG", 0x40080, 0 },
|
|
{ "mddr_lpddr2_clk_stop_idle", 24, 8 },
|
|
{ "mddr_lpddr2_en", 22, 2 },
|
|
{ "mddr_lpddr2_bl", 20, 2 },
|
|
{ "tfaw_cfg", 18, 2 },
|
|
{ "pd_exit_mode", 17, 1 },
|
|
{ "pd_type", 16, 1 },
|
|
{ "pd_idle", 8, 8 },
|
|
{ "lpddr2_s4", 6, 1 },
|
|
{ "ddr3_en", 5, 1 },
|
|
{ "stagger_cs", 4, 1 },
|
|
{ "two_t_en", 3, 1 },
|
|
{ "bl8int_en", 2, 1 },
|
|
{ "cke_or_en", 1, 1 },
|
|
{ "mem_bl", 0, 1 },
|
|
{ "MC_UPCTL_PPCFG", 0x40084, 0 },
|
|
{ "rpmem_dis", 1, 8 },
|
|
{ "ppmem_en", 0, 1 },
|
|
{ "MC_UPCTL_MSTAT", 0x40088, 0 },
|
|
{ "self_refresh", 2, 1 },
|
|
{ "clock_stop", 1, 1 },
|
|
{ "power_down", 0, 1 },
|
|
{ "MC_UPCTL_LPDDR2ZQCFG", 0x4008c, 0 },
|
|
{ "zqcl_op", 24, 8 },
|
|
{ "zqcl_ma", 16, 8 },
|
|
{ "zqcs_op", 8, 8 },
|
|
{ "zqcs_ma", 0, 8 },
|
|
{ "MC_UPCTL_DTUPDES", 0x40094, 0 },
|
|
{ "dtu_rd_missing", 13, 1 },
|
|
{ "dtu_eaffl", 9, 4 },
|
|
{ "dtu_random_error", 8, 1 },
|
|
{ "dtu_err_b7", 7, 1 },
|
|
{ "dtu_err_b6", 6, 1 },
|
|
{ "dtu_err_b5", 5, 1 },
|
|
{ "dtu_err_b4", 4, 1 },
|
|
{ "dtu_err_b3", 3, 1 },
|
|
{ "dtu_err_b2", 2, 1 },
|
|
{ "dtu_err_b1", 1, 1 },
|
|
{ "dtu_err_b0", 0, 1 },
|
|
{ "MC_UPCTL_DTUNA", 0x40098, 0 },
|
|
{ "MC_UPCTL_DTUNE", 0x4009c, 0 },
|
|
{ "MC_UPCTL_DTUPRD0", 0x400a0, 0 },
|
|
{ "dtu_allbits_1", 16, 16 },
|
|
{ "dtu_allbits_0", 0, 16 },
|
|
{ "MC_UPCTL_DTUPRD1", 0x400a4, 0 },
|
|
{ "dtu_allbits_3", 16, 16 },
|
|
{ "dtu_allbits_2", 0, 16 },
|
|
{ "MC_UPCTL_DTUPRD2", 0x400a8, 0 },
|
|
{ "dtu_allbits_5", 16, 16 },
|
|
{ "dtu_allbits_4", 0, 16 },
|
|
{ "MC_UPCTL_DTUPRD3", 0x400ac, 0 },
|
|
{ "dtu_allbits_7", 16, 16 },
|
|
{ "dtu_allbits_6", 0, 16 },
|
|
{ "MC_UPCTL_DTUAWDT", 0x400b0, 0 },
|
|
{ "number_ranks", 9, 2 },
|
|
{ "row_addr_width", 6, 2 },
|
|
{ "bank_addr_width", 3, 2 },
|
|
{ "column_addr_width", 0, 2 },
|
|
{ "MC_UPCTL_TOGCNT1U", 0x400c0, 0 },
|
|
{ "MC_UPCTL_TINIT", 0x400c4, 0 },
|
|
{ "MC_UPCTL_TRSTH", 0x400c8, 0 },
|
|
{ "MC_UPCTL_TOGCNT100N", 0x400cc, 0 },
|
|
{ "MC_UPCTL_TREFI", 0x400d0, 0 },
|
|
{ "MC_UPCTL_TMRD", 0x400d4, 0 },
|
|
{ "MC_UPCTL_TRFC", 0x400d8, 0 },
|
|
{ "MC_UPCTL_TRP", 0x400dc, 0 },
|
|
{ "prea_extra", 16, 2 },
|
|
{ "t_rp", 0, 4 },
|
|
{ "MC_UPCTL_TRTW", 0x400e0, 0 },
|
|
{ "MC_UPCTL_TAL", 0x400e4, 0 },
|
|
{ "MC_UPCTL_TCL", 0x400e8, 0 },
|
|
{ "MC_UPCTL_TCWL", 0x400ec, 0 },
|
|
{ "MC_UPCTL_TRAS", 0x400f0, 0 },
|
|
{ "MC_UPCTL_TRC", 0x400f4, 0 },
|
|
{ "MC_UPCTL_TRCD", 0x400f8, 0 },
|
|
{ "MC_UPCTL_TRRD", 0x400fc, 0 },
|
|
{ "MC_UPCTL_TRTP", 0x40100, 0 },
|
|
{ "MC_UPCTL_TWR", 0x40104, 0 },
|
|
{ "MC_UPCTL_TWTR", 0x40108, 0 },
|
|
{ "MC_UPCTL_TEXSR", 0x4010c, 0 },
|
|
{ "MC_UPCTL_TXP", 0x40110, 0 },
|
|
{ "MC_UPCTL_TXPDLL", 0x40114, 0 },
|
|
{ "MC_UPCTL_TZQCS", 0x40118, 0 },
|
|
{ "MC_UPCTL_TZQCSI", 0x4011c, 0 },
|
|
{ "MC_UPCTL_TDQS", 0x40120, 0 },
|
|
{ "MC_UPCTL_TCKSRE", 0x40124, 0 },
|
|
{ "MC_UPCTL_TCKSRX", 0x40128, 0 },
|
|
{ "MC_UPCTL_TCKE", 0x4012c, 0 },
|
|
{ "MC_UPCTL_TMOD", 0x40130, 0 },
|
|
{ "MC_UPCTL_TRSTL", 0x40134, 0 },
|
|
{ "MC_UPCTL_TZQCL", 0x40138, 0 },
|
|
{ "MC_UPCTL_TMRR", 0x4013c, 0 },
|
|
{ "MC_UPCTL_TCKESR", 0x40140, 0 },
|
|
{ "MC_UPCTL_TDPD", 0x40144, 0 },
|
|
{ "MC_UPCTL_ECCCFG", 0x40180, 0 },
|
|
{ "inline_syn_en", 4, 1 },
|
|
{ "ecc_en", 3, 1 },
|
|
{ "ecc_intr_en", 2, 1 },
|
|
{ "MC_UPCTL_ECCTST", 0x40184, 0 },
|
|
{ "MC_UPCTL_ECCCLR", 0x40188, 0 },
|
|
{ "clr_ecc_log", 1, 1 },
|
|
{ "clr_ecc_intr", 0, 1 },
|
|
{ "MC_UPCTL_ECCLOG", 0x4018c, 0 },
|
|
{ "MC_UPCTL_DTUWACTL", 0x40200, 0 },
|
|
{ "dtu_wr_rank", 30, 2 },
|
|
{ "dtu_wr_row0", 13, 16 },
|
|
{ "dtu_wr_bank", 10, 3 },
|
|
{ "dtu_wr_col", 0, 10 },
|
|
{ "MC_UPCTL_DTURACTL", 0x40204, 0 },
|
|
{ "dtu_rd_rank", 30, 2 },
|
|
{ "dtu_rd_row0", 13, 16 },
|
|
{ "dtu_rd_bank", 10, 3 },
|
|
{ "dtu_rd_col", 0, 10 },
|
|
{ "MC_UPCTL_DTUCFG", 0x40208, 0 },
|
|
{ "dtu_row_increments", 16, 7 },
|
|
{ "dtu_wr_multi_rd", 15, 1 },
|
|
{ "dtu_data_mask_en", 14, 1 },
|
|
{ "dtu_target_lane", 10, 4 },
|
|
{ "dtu_generate_random", 9, 1 },
|
|
{ "dtu_incr_banks", 8, 1 },
|
|
{ "dtu_incr_cols", 7, 1 },
|
|
{ "dtu_nalen", 1, 6 },
|
|
{ "dtu_enable", 0, 1 },
|
|
{ "MC_UPCTL_DTUECTL", 0x4020c, 0 },
|
|
{ "wr_multi_rd_rst", 2, 1 },
|
|
{ "run_error_reports", 1, 1 },
|
|
{ "run_dtu", 0, 1 },
|
|
{ "MC_UPCTL_DTUWD0", 0x40210, 0 },
|
|
{ "dtu_wr_byte3", 24, 8 },
|
|
{ "dtu_wr_byte2", 16, 8 },
|
|
{ "dtu_wr_byte1", 8, 8 },
|
|
{ "dtu_wr_byte0", 0, 8 },
|
|
{ "MC_UPCTL_DTUWD1", 0x40214, 0 },
|
|
{ "dtu_wr_byte7", 24, 8 },
|
|
{ "dtu_wr_byte6", 16, 8 },
|
|
{ "dtu_wr_byte5", 8, 8 },
|
|
{ "dtu_wr_byte4", 0, 8 },
|
|
{ "MC_UPCTL_DTUWD2", 0x40218, 0 },
|
|
{ "dtu_wr_byte11", 24, 8 },
|
|
{ "dtu_wr_byte10", 16, 8 },
|
|
{ "dtu_wr_byte9", 8, 8 },
|
|
{ "dtu_wr_byte8", 0, 8 },
|
|
{ "MC_UPCTL_DTUWD3", 0x4021c, 0 },
|
|
{ "dtu_wr_byte15", 24, 8 },
|
|
{ "dtu_wr_byte14", 16, 8 },
|
|
{ "dtu_wr_byte13", 8, 8 },
|
|
{ "dtu_wr_byte12", 0, 8 },
|
|
{ "MC_UPCTL_DTUWDM", 0x40220, 0 },
|
|
{ "MC_UPCTL_DTURD0", 0x40224, 0 },
|
|
{ "dtu_rd_byte3", 24, 8 },
|
|
{ "dtu_rd_byte2", 16, 8 },
|
|
{ "dtu_rd_byte1", 8, 8 },
|
|
{ "dtu_rd_byte0", 0, 8 },
|
|
{ "MC_UPCTL_DTURD1", 0x40228, 0 },
|
|
{ "dtu_rd_byte7", 24, 8 },
|
|
{ "dtu_rd_byte6", 16, 8 },
|
|
{ "dtu_rd_byte5", 8, 8 },
|
|
{ "dtu_rd_byte4", 0, 8 },
|
|
{ "MC_UPCTL_DTURD2", 0x4022c, 0 },
|
|
{ "dtu_rd_byte11", 24, 8 },
|
|
{ "dtu_rd_byte10", 16, 8 },
|
|
{ "dtu_rd_byte9", 8, 8 },
|
|
{ "dtu_rd_byte8", 0, 8 },
|
|
{ "MC_UPCTL_DTURD3", 0x40230, 0 },
|
|
{ "dtu_rd_byte15", 24, 8 },
|
|
{ "dtu_rd_byte14", 16, 8 },
|
|
{ "dtu_rd_byte13", 8, 8 },
|
|
{ "dtu_rd_byte12", 0, 8 },
|
|
{ "MC_UPCTL_DTULFSRWD", 0x40234, 0 },
|
|
{ "MC_UPCTL_DTULFSRRD", 0x40238, 0 },
|
|
{ "MC_UPCTL_DTUEAF", 0x4023c, 0 },
|
|
{ "ea_rank", 30, 2 },
|
|
{ "ea_row0", 13, 16 },
|
|
{ "ea_bank", 10, 3 },
|
|
{ "ea_column", 0, 10 },
|
|
{ "MC_UPCTL_DFITCTRLDELAY", 0x40240, 0 },
|
|
{ "MC_UPCTL_DFIODTCFG", 0x40244, 0 },
|
|
{ "rank3_odt_default", 28, 1 },
|
|
{ "rank3_odt_write_sel", 27, 1 },
|
|
{ "rank3_odt_write_nsel", 26, 1 },
|
|
{ "rank3_odt_read_sel", 25, 1 },
|
|
{ "rank3_odt_read_nsel", 24, 1 },
|
|
{ "rank2_odt_default", 20, 1 },
|
|
{ "rank2_odt_write_sel", 19, 1 },
|
|
{ "rank2_odt_write_nsel", 18, 1 },
|
|
{ "rank2_odt_read_sel", 17, 1 },
|
|
{ "rank2_odt_read_nsel", 16, 1 },
|
|
{ "rank1_odt_default", 12, 1 },
|
|
{ "rank1_odt_write_sel", 11, 1 },
|
|
{ "rank1_odt_write_nsel", 10, 1 },
|
|
{ "rank1_odt_read_sel", 9, 1 },
|
|
{ "rank1_odt_read_nsel", 8, 1 },
|
|
{ "rank0_odt_default", 4, 1 },
|
|
{ "rank0_odt_write_sel", 3, 1 },
|
|
{ "rank0_odt_write_nsel", 2, 1 },
|
|
{ "rank0_odt_read_sel", 1, 1 },
|
|
{ "rank0_odt_read_nsel", 0, 1 },
|
|
{ "MC_UPCTL_DFIODTCFG1", 0x40248, 0 },
|
|
{ "odt_len_b8_r", 24, 3 },
|
|
{ "odt_len_bl8_w", 16, 3 },
|
|
{ "odt_lat_r", 8, 5 },
|
|
{ "odt_lat_w", 0, 5 },
|
|
{ "MC_UPCTL_DFIODTRANKMAP", 0x4024c, 0 },
|
|
{ "odt_rank_map3", 12, 4 },
|
|
{ "odt_rank_map2", 8, 4 },
|
|
{ "odt_rank_map1", 4, 4 },
|
|
{ "odt_rank_map0", 0, 4 },
|
|
{ "MC_UPCTL_DFITPHYWRDATA", 0x40250, 0 },
|
|
{ "MC_UPCTL_DFITPHYWRLAT", 0x40254, 0 },
|
|
{ "MC_UPCTL_DFITRDDATAEN", 0x40260, 0 },
|
|
{ "MC_UPCTL_DFITPHYRDLAT", 0x40264, 0 },
|
|
{ "MC_UPCTL_DFITPHYUPDTYPE0", 0x40270, 0 },
|
|
{ "MC_UPCTL_DFITPHYUPDTYPE1", 0x40274, 0 },
|
|
{ "MC_UPCTL_DFITPHYUPDTYPE2", 0x40278, 0 },
|
|
{ "MC_UPCTL_DFITPHYUPDTYPE3", 0x4027c, 0 },
|
|
{ "MC_UPCTL_DFITCTRLUPDMIN", 0x40280, 0 },
|
|
{ "MC_UPCTL_DFITCTRLUPDMAX", 0x40284, 0 },
|
|
{ "MC_UPCTL_DFITCTRLUPDDLY", 0x40288, 0 },
|
|
{ "MC_UPCTL_DFIUPDCFG", 0x40290, 0 },
|
|
{ "dfi_phyupd_en", 1, 1 },
|
|
{ "dfi_ctrlupd_en", 0, 1 },
|
|
{ "MC_UPCTL_DFITREFMSKI", 0x40294, 0 },
|
|
{ "MC_UPCTL_DFITCTRLUPDI", 0x40298, 0 },
|
|
{ "MC_UPCTL_DFITRCFG0", 0x402ac, 0 },
|
|
{ "dfi_wrlvl_rank_sel", 16, 4 },
|
|
{ "dfi_rdlvl_edge", 4, 9 },
|
|
{ "dfi_rdlvl_rank_sel", 0, 4 },
|
|
{ "MC_UPCTL_DFITRSTAT0", 0x402b0, 0 },
|
|
{ "dfi_wrlvl_mode", 16, 2 },
|
|
{ "dfi_rdlvl_gate_mode", 8, 2 },
|
|
{ "dfi_rdlvl_mode", 0, 2 },
|
|
{ "MC_UPCTL_DFITRWRLVLEN", 0x402b4, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLEN", 0x402b8, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLGATEEN", 0x402bc, 0 },
|
|
{ "MC_UPCTL_DFISTSTAT0", 0x402c0, 0 },
|
|
{ "dfi_data_byte_disable", 16, 9 },
|
|
{ "dfi_freq_ratio", 4, 2 },
|
|
{ "dfi_init_start0", 1, 1 },
|
|
{ "dfi_init_complete", 0, 1 },
|
|
{ "MC_UPCTL_DFISTCFG0", 0x402c4, 0 },
|
|
{ "dfi_data_byte_disable_en", 2, 1 },
|
|
{ "dfi_freq_ratio_en", 1, 1 },
|
|
{ "dfi_init_start", 0, 1 },
|
|
{ "MC_UPCTL_DFISTCFG1", 0x402c8, 0 },
|
|
{ "dfi_dram_clk_disable_en_dpd", 1, 1 },
|
|
{ "dfi_dram_clk_disable_en", 0, 1 },
|
|
{ "MC_UPCTL_DFITDRAMCLKEN", 0x402d0, 0 },
|
|
{ "MC_UPCTL_DFITDRAMCLKDIS", 0x402d4, 0 },
|
|
{ "MC_UPCTL_DFISTCFG2", 0x402d8, 0 },
|
|
{ "parity_en", 1, 1 },
|
|
{ "parity_intr_en", 0, 1 },
|
|
{ "MC_UPCTL_DFISTPARCLR", 0x402dc, 0 },
|
|
{ "parity_log_clr", 1, 1 },
|
|
{ "parity_intr_clr", 0, 1 },
|
|
{ "MC_UPCTL_DFISTPARLOG", 0x402e0, 0 },
|
|
{ "MC_UPCTL_DFILPCFG0", 0x402f0, 0 },
|
|
{ "dfi_lp_wakeup_dpd", 28, 4 },
|
|
{ "dfi_lp_en_dpd", 24, 1 },
|
|
{ "dfi_tlp_resp", 16, 4 },
|
|
{ "dfi_lp_en_sr", 8, 1 },
|
|
{ "dfi_lp_wakeup_pd", 4, 4 },
|
|
{ "dfi_lp_en_pd", 0, 1 },
|
|
{ "MC_UPCTL_DFITRWRLVLRESP0", 0x40300, 0 },
|
|
{ "MC_UPCTL_DFITRWRLVLRESP1", 0x40304, 0 },
|
|
{ "MC_UPCTL_DFITRWRLVLRESP2", 0x40308, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLRESP0", 0x4030c, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLRESP1", 0x40310, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLRESP2", 0x40314, 0 },
|
|
{ "MC_UPCTL_DFITRWRLVLDELAY0", 0x40318, 0 },
|
|
{ "MC_UPCTL_DFITRWRLVLDELAY1", 0x4031c, 0 },
|
|
{ "MC_UPCTL_DFITRWRLVLDELAY2", 0x40320, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLDELAY0", 0x40324, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLDELAY1", 0x40328, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLDELAY2", 0x4032c, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLGATEDELAY0", 0x40330, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLGATEDELAY1", 0x40334, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLGATEDELAY2", 0x40338, 0 },
|
|
{ "MC_UPCTL_DFITRCMD", 0x4033c, 0 },
|
|
{ "dfitrcmd_start", 31, 1 },
|
|
{ "dfitrcmd_en", 4, 9 },
|
|
{ "dfitrcmd_opcode", 0, 2 },
|
|
{ "MC_UPCTL_IPVR", 0x403f8, 0 },
|
|
{ "MC_UPCTL_IPTR", 0x403fc, 0 },
|
|
{ "MC_P_DDRPHY_RST_CTRL", 0x41300, 0 },
|
|
{ "PHY_DRAM_WL", 17, 5 },
|
|
{ "PHY_CALIB_DONE", 5, 1 },
|
|
{ "CTL_CAL_REQ", 4, 1 },
|
|
{ "CTL_CKE", 3, 1 },
|
|
{ "CTL_RST_N", 2, 1 },
|
|
{ "DDRIO_ENABLE", 1, 1 },
|
|
{ "PHY_RST_N", 0, 1 },
|
|
{ "MC_P_PERFORMANCE_CTRL", 0x41304, 0 },
|
|
{ "STALL_CHK_BIT", 2, 1 },
|
|
{ "DDR3_BRC_MODE", 1, 1 },
|
|
{ "RMW_PERF_CTRL", 0, 1 },
|
|
{ "MC_P_ECC_CTRL", 0x41308, 0 },
|
|
{ "ECC_BYPASS_BIST", 1, 1 },
|
|
{ "ECC_DISABLE", 0, 1 },
|
|
{ "MC_P_PAR_ENABLE", 0x4130c, 0 },
|
|
{ "ECC_UE_PAR_ENABLE", 3, 1 },
|
|
{ "ECC_CE_PAR_ENABLE", 2, 1 },
|
|
{ "PERR_REG_INT_ENABLE", 1, 1 },
|
|
{ "PERR_BLK_INT_ENABLE", 0, 1 },
|
|
{ "MC_P_PAR_CAUSE", 0x41310, 0 },
|
|
{ "ECC_UE_PAR_CAUSE", 3, 1 },
|
|
{ "ECC_CE_PAR_CAUSE", 2, 1 },
|
|
{ "FIFOR_PAR_CAUSE", 1, 1 },
|
|
{ "RDATA_FIFOR_PAR_CAUSE", 0, 1 },
|
|
{ "MC_P_INT_ENABLE", 0x41314, 0 },
|
|
{ "ECC_UE_INT_ENABLE", 2, 1 },
|
|
{ "ECC_CE_INT_ENABLE", 1, 1 },
|
|
{ "PERR_INT_ENABLE", 0, 1 },
|
|
{ "MC_P_INT_CAUSE", 0x41318, 0 },
|
|
{ "ECC_UE_INT_CAUSE", 2, 1 },
|
|
{ "ECC_CE_INT_CAUSE", 1, 1 },
|
|
{ "PERR_INT_CAUSE", 0, 1 },
|
|
{ "MC_P_ECC_STATUS", 0x4131c, 0 },
|
|
{ "ECC_CECNT", 16, 16 },
|
|
{ "ECC_UECNT", 0, 16 },
|
|
{ "MC_P_PHY_CTRL", 0x41320, 0 },
|
|
{ "MC_P_STATIC_CFG_STATUS", 0x41324, 0 },
|
|
{ "STATIC_AWEN", 23, 1 },
|
|
{ "STATIC_SWLAT", 18, 5 },
|
|
{ "STATIC_WLAT", 17, 1 },
|
|
{ "STATIC_ALIGN", 16, 1 },
|
|
{ "STATIC_SLAT", 11, 5 },
|
|
{ "STATIC_LAT", 10, 1 },
|
|
{ "STATIC_MODE", 9, 1 },
|
|
{ "STATIC_DEN", 6, 3 },
|
|
{ "STATIC_ORG", 5, 1 },
|
|
{ "STATIC_RKS", 4, 1 },
|
|
{ "STATIC_WIDTH", 1, 3 },
|
|
{ "STATIC_SLOW", 0, 1 },
|
|
{ "MC_P_CORE_PCTL_STAT", 0x41328, 0 },
|
|
{ "MC_P_DEBUG_CNT", 0x4132c, 0 },
|
|
{ "WDATA_OCNT", 8, 5 },
|
|
{ "RDATA_OCNT", 0, 5 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x41330, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x41334, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x41338, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x4133c, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x41340, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x41344, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x41348, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x4134c, 0 },
|
|
{ "MC_CE_COR_DATA_RDATA", 0x41350, 0 },
|
|
{ "MC_CE_COR_DATA_RDATA", 0x41354, 0 },
|
|
{ "MC_CE_COR_DATA_RDATA", 0x41358, 0 },
|
|
{ "MC_CE_COR_DATA_RDATA", 0x4135c, 0 },
|
|
{ "MC_CE_COR_DATA_RDATA", 0x41360, 0 },
|
|
{ "MC_CE_COR_DATA_RDATA", 0x41364, 0 },
|
|
{ "MC_CE_COR_DATA_RDATA", 0x41368, 0 },
|
|
{ "MC_CE_COR_DATA_RDATA", 0x4136c, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x41370, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x41374, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x41378, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x4137c, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x41380, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x41384, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x41388, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x4138c, 0 },
|
|
{ "MC_UE_COR_DATA_RDATA", 0x41390, 0 },
|
|
{ "MC_UE_COR_DATA_RDATA", 0x41394, 0 },
|
|
{ "MC_UE_COR_DATA_RDATA", 0x41398, 0 },
|
|
{ "MC_UE_COR_DATA_RDATA", 0x4139c, 0 },
|
|
{ "MC_UE_COR_DATA_RDATA", 0x413a0, 0 },
|
|
{ "MC_UE_COR_DATA_RDATA", 0x413a4, 0 },
|
|
{ "MC_UE_COR_DATA_RDATA", 0x413a8, 0 },
|
|
{ "MC_UE_COR_DATA_RDATA", 0x413ac, 0 },
|
|
{ "MC_CE_ADDR", 0x413b0, 0 },
|
|
{ "MC_UE_ADDR", 0x413b4, 0 },
|
|
{ "MC_P_DEEP_SLEEP", 0x413b8, 0 },
|
|
{ "SleepStatus", 1, 1 },
|
|
{ "SleepReq", 0, 1 },
|
|
{ "MC_P_FPGA_BONUS", 0x413bc, 0 },
|
|
{ "MC_P_DEBUG_CFG", 0x413c0, 0 },
|
|
{ "DEBUG_OR", 15, 1 },
|
|
{ "DEBUG_HI", 14, 1 },
|
|
{ "DEBUG_RPT", 13, 1 },
|
|
{ "DEBUGPAGE", 10, 3 },
|
|
{ "DEBUGSELH", 5, 5 },
|
|
{ "DEBUGSELL", 0, 5 },
|
|
{ "MC_P_DEBUG_RPT", 0x413c4, 0 },
|
|
{ "MC_P_BIST_CMD", 0x41400, 0 },
|
|
{ "START_BIST", 31, 1 },
|
|
{ "BURST_LEN", 16, 2 },
|
|
{ "BIST_CMD_GAP", 8, 8 },
|
|
{ "BIST_OPCODE", 0, 2 },
|
|
{ "MC_P_BIST_CMD_ADDR", 0x41404, 0 },
|
|
{ "MC_P_BIST_CMD_LEN", 0x41408, 0 },
|
|
{ "MC_P_BIST_DATA_PATTERN", 0x4140c, 0 },
|
|
{ "MC_P_BIST_USER_WDATA0", 0x41414, 0 },
|
|
{ "MC_P_BIST_USER_WDATA1", 0x41418, 0 },
|
|
{ "MC_P_BIST_USER_WDATA2", 0x4141c, 0 },
|
|
{ "USER_DATA_MASK", 8, 9 },
|
|
{ "USER_DATA2", 0, 8 },
|
|
{ "MC_P_BIST_NUM_ERR", 0x41480, 0 },
|
|
{ "MC_P_BIST_ERR_FIRST_ADDR", 0x41484, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x41488, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x4148c, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x41490, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x41494, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x41498, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x4149c, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414a0, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414a4, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414a8, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414ac, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414b0, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414b4, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414b8, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414bc, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414c0, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414c4, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414c8, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x414cc, 0 },
|
|
{ "MC_P_BIST_CRC_SEED", 0x414d0, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_mc_1_regs[] = {
|
|
{ "MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS", 0x4f000, 0 },
|
|
{ "DP18_PLL_LOCK", 1, 15 },
|
|
{ "MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS", 0x4f004, 0 },
|
|
{ "AD32S_PLL_LOCK", 14, 2 },
|
|
{ "MC_DDRPHY_PC_RANK_PAIR0", 0x4f008, 0 },
|
|
{ "RANK_PAIR0_PRI", 13, 3 },
|
|
{ "RANK_PAIR0_PRI_V", 12, 1 },
|
|
{ "RANK_PAIR0_SEC", 9, 3 },
|
|
{ "RANK_PAIR0_SEC_V", 8, 1 },
|
|
{ "RANK_PAIR1_PRI", 5, 3 },
|
|
{ "RANK_PAIR1_PRI_V", 4, 1 },
|
|
{ "RANK_PAIR1_SEC", 1, 3 },
|
|
{ "RANK_PAIR1_SEC_V", 0, 1 },
|
|
{ "MC_DDRPHY_PC_RANK_PAIR1", 0x4f00c, 0 },
|
|
{ "RANK_PAIR2_PRI", 13, 3 },
|
|
{ "RANK_PAIR2_PRI_V", 12, 1 },
|
|
{ "RANK_PAIR2_SEC", 9, 3 },
|
|
{ "RANK_PAIR2_SEC_V", 8, 1 },
|
|
{ "RANK_PAIR3_PRI", 5, 3 },
|
|
{ "RANK_PAIR3_PRI_V", 4, 1 },
|
|
{ "RANK_PAIR3_SEC", 1, 3 },
|
|
{ "RANK_PAIR3_SEC_V", 0, 1 },
|
|
{ "MC_DDRPHY_PC_BASE_CNTR0", 0x4f010, 0 },
|
|
{ "MC_DDRPHY_PC_RELOAD_VALUE0", 0x4f014, 0 },
|
|
{ "PERIODIC_CAL_REQ_EN", 15, 1 },
|
|
{ "PERIODIC_RELOAD_VALUE0", 0, 15 },
|
|
{ "MC_DDRPHY_PC_BASE_CNTR1", 0x4f018, 0 },
|
|
{ "MC_DDRPHY_PC_CAL_TIMER", 0x4f01c, 0 },
|
|
{ "MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE", 0x4f020, 0 },
|
|
{ "MC_DDRPHY_PC_ZCAL_TIMER", 0x4f024, 0 },
|
|
{ "MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE", 0x4f028, 0 },
|
|
{ "MC_DDRPHY_PC_PER_CAL_CONFIG", 0x4f02c, 0 },
|
|
{ "PER_ENA_RANK_PAIR", 12, 4 },
|
|
{ "PER_ENA_ZCAL", 11, 1 },
|
|
{ "PER_ENA_SYSCLK_ALIGN", 10, 1 },
|
|
{ "ENA_PER_READ_CTR", 9, 1 },
|
|
{ "ENA_PER_RDCLK_ALIGN", 8, 1 },
|
|
{ "ENA_PER_DQS_ALIGN", 7, 1 },
|
|
{ "PER_NEXT_RANK_PAIR", 5, 2 },
|
|
{ "FAST_SIM_PER_CNTR", 4, 1 },
|
|
{ "START_INIT_CAL", 3, 1 },
|
|
{ "START_PER_CAL", 2, 1 },
|
|
{ "ABORT_ON_ERR_EN", 1, 1 },
|
|
{ "MC_DDRPHY_PC_PER_ZCAL_CONFIG", 0x4f03c, 0 },
|
|
{ "PER_ZCAL_ENA_RANK", 8, 8 },
|
|
{ "PER_ZCAL_NEXT_RANK", 5, 3 },
|
|
{ "START_PER_ZCAL", 4, 1 },
|
|
{ "MC_DDRPHY_PC_CONFIG0", 0x4f030, 0 },
|
|
{ "PROTOCOL_DDR", 12, 4 },
|
|
{ "DATA_MUX4_1MODE", 11, 1 },
|
|
{ "DDR4_CMD_SIG_REDUCTION", 9, 1 },
|
|
{ "SYSCLK_2X_MEMINTCLKO", 8, 1 },
|
|
{ "RANK_OVERRIDE", 7, 1 },
|
|
{ "RANK_OVERRIDE_VALUE", 4, 3 },
|
|
{ "LOW_LATENCY", 3, 1 },
|
|
{ "DDR4_BANK_REFRESH", 2, 1 },
|
|
{ "DDR4_VLEVEL_BANK_GROUP", 1, 1 },
|
|
{ "MC_DDRPHY_PC_CONFIG1", 0x4f034, 0 },
|
|
{ "WRITE_LATENCY_OFFSET", 12, 4 },
|
|
{ "READ_LATENCY_OFFSET", 8, 4 },
|
|
{ "MEMCTL_CIC_FAST", 7, 1 },
|
|
{ "MEMCTL_CTRN_IGNORE", 6, 1 },
|
|
{ "DISABLE_MEMCTL_CAL", 5, 1 },
|
|
{ "MC_DDRPHY_PC_RESETS", 0x4f038, 0 },
|
|
{ "PLL_RESET", 15, 1 },
|
|
{ "SYSCLK_RESET", 14, 1 },
|
|
{ "MC_DDRPHY_PC_ERROR_STATUS0", 0x4f048, 0 },
|
|
{ "RC_ERROR", 15, 1 },
|
|
{ "WC_ERROR", 14, 1 },
|
|
{ "SEQ_ERROR", 13, 1 },
|
|
{ "CC_ERROR", 12, 1 },
|
|
{ "APB_ERROR", 11, 1 },
|
|
{ "PC_ERROR", 10, 1 },
|
|
{ "MC_DDRPHY_PC_ERROR_MASK0", 0x4f04c, 0 },
|
|
{ "RC_ERROR_MASK", 15, 1 },
|
|
{ "WC_ERROR_MASK", 14, 1 },
|
|
{ "SEQ_ERROR_MASK", 13, 1 },
|
|
{ "CC_ERROR_MASK", 12, 1 },
|
|
{ "APB_ERROR_MASK", 11, 1 },
|
|
{ "PC_ERROR_MASK", 10, 1 },
|
|
{ "MC_DDRPHY_PC_IO_PVT_FET_CONTROL", 0x4f050, 0 },
|
|
{ "PVTP", 11, 5 },
|
|
{ "PVTN", 6, 5 },
|
|
{ "PVT_OVERRIDE", 5, 1 },
|
|
{ "ENABLE_ZCAL", 4, 1 },
|
|
{ "MC_DDRPHY_PC_VREF_DRV_CONTROL", 0x4f054, 0 },
|
|
{ "VREFDQ0DSGN", 15, 1 },
|
|
{ "VREFDQ0D", 11, 4 },
|
|
{ "VREFDQ1DSGN", 10, 1 },
|
|
{ "VREFDQ1D", 6, 4 },
|
|
{ "MC_DDRPHY_PC_INIT_CAL_CONFIG0", 0x4f058, 0 },
|
|
{ "ENA_WR_LEVEL", 15, 1 },
|
|
{ "ENA_INITIAL_PAT_WR", 14, 1 },
|
|
{ "ENA_DQS_ALIGN", 13, 1 },
|
|
{ "ENA_RDCLK_ALIGN", 12, 1 },
|
|
{ "ENA_READ_CTR", 11, 1 },
|
|
{ "ENA_WRITE_CTR", 10, 1 },
|
|
{ "ENA_INITIAL_COARSE_WR", 9, 1 },
|
|
{ "ENA_COARSE_RD", 8, 1 },
|
|
{ "ENA_CUSTOM_RD", 7, 1 },
|
|
{ "ENA_CUSTOM_WR", 6, 1 },
|
|
{ "ABORT_ON_CAL_ERROR", 5, 1 },
|
|
{ "ENA_DIGITAL_EYE", 4, 1 },
|
|
{ "ENA_RANK_PAIR", 0, 4 },
|
|
{ "MC_DDRPHY_PC_INIT_CAL_CONFIG1", 0x4f05c, 0 },
|
|
{ "REFRESH_COUNT", 12, 4 },
|
|
{ "REFRESH_CONTROL", 10, 2 },
|
|
{ "REFRESH_ALL_RANKS", 9, 1 },
|
|
{ "REFRESH_INTERVAL", 0, 7 },
|
|
{ "MC_DDRPHY_PC_INIT_CAL_ERROR", 0x4f060, 0 },
|
|
{ "ERROR_WR_LEVEL", 15, 1 },
|
|
{ "ERROR_INITIAL_PAT_WRITE", 14, 1 },
|
|
{ "ERROR_DQS_ALIGN", 13, 1 },
|
|
{ "ERROR_RDCLK_ALIGN", 12, 1 },
|
|
{ "ERROR_READ_CTR", 11, 1 },
|
|
{ "ERROR_WRITE_CTR", 10, 1 },
|
|
{ "ERROR_INITIAL_COARSE_WR", 9, 1 },
|
|
{ "ERROR_COARSE_RD", 8, 1 },
|
|
{ "ERROR_CUSTOM_RD", 7, 1 },
|
|
{ "ERROR_CUSTOM_WR", 6, 1 },
|
|
{ "ERROR_DIGITAL_EYE", 5, 1 },
|
|
{ "ERROR_RANK_PAIR", 0, 4 },
|
|
{ "MC_DDRPHY_PC_INIT_CAL_MASK", 0x4f068, 0 },
|
|
{ "ERROR_WR_LEVEL_MASK", 15, 1 },
|
|
{ "ERROR_INITIAL_PAT_WRITE_MASK", 14, 1 },
|
|
{ "ERROR_DQS_ALIGN_MASK", 13, 1 },
|
|
{ "ERROR_RDCLK_ALIGN_MASK", 12, 1 },
|
|
{ "ERROR_READ_CTR_MASK", 11, 1 },
|
|
{ "ERROR_WRITE_CTR_MASK", 10, 1 },
|
|
{ "ERROR_INITIAL_COARSE_WR_MASK", 9, 1 },
|
|
{ "ERROR_COARSE_RD_MASK", 8, 1 },
|
|
{ "ERROR_CUSTOM_RD_MASK", 7, 1 },
|
|
{ "ERROR_CUSTOM_WR_MASK", 6, 1 },
|
|
{ "ERROR_DIGITAL_EYE_MASK", 5, 1 },
|
|
{ "MC_DDRPHY_PC_INIT_CAL_STATUS", 0x4f064, 0 },
|
|
{ "INIT_CAL_COMPLETE", 12, 4 },
|
|
{ "MC_DDRPHY_PC_IO_PVT_FET_STATUS", 0x4f06c, 0 },
|
|
{ "PVTP", 11, 5 },
|
|
{ "PVTN", 6, 5 },
|
|
{ "MC_DDRPHY_PC_MR0_PRI_RP", 0x4f070, 0 },
|
|
{ "MC_DDRPHY_PC_MR1_PRI_RP", 0x4f074, 0 },
|
|
{ "MC_DDRPHY_PC_MR2_PRI_RP", 0x4f078, 0 },
|
|
{ "MC_DDRPHY_PC_MR3_PRI_RP", 0x4f07c, 0 },
|
|
{ "MC_DDRPHY_PC_MR0_SEC_RP", 0x4f080, 0 },
|
|
{ "MC_DDRPHY_PC_MR1_SEC_RP", 0x4f084, 0 },
|
|
{ "MC_DDRPHY_PC_MR2_SEC_RP", 0x4f088, 0 },
|
|
{ "MC_DDRPHY_PC_MR3_SEC_RP", 0x4f08c, 0 },
|
|
{ "MC_DDRPHY_PC_RANK_GROUP", 0x4f044, 0 },
|
|
{ "ADDR_MIRROR_RP0_PRI", 15, 1 },
|
|
{ "ADDR_MIRROR_RP0_SEC", 14, 1 },
|
|
{ "ADDR_MIRROR_RP1_PRI", 13, 1 },
|
|
{ "ADDR_MIRROR_RP1_SEC", 12, 1 },
|
|
{ "ADDR_MIRROR_RP2_PRI", 11, 1 },
|
|
{ "ADDR_MIRROR_RP2_SEC", 10, 1 },
|
|
{ "ADDR_MIRROR_RP3_PRI", 9, 1 },
|
|
{ "ADDR_MIRROR_RP3_SEC", 8, 1 },
|
|
{ "RANK_GROUPING", 6, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_BIT_ENABLE", 0x4d000, 0 },
|
|
{ "BIT_ENABLE_0_11", 4, 12 },
|
|
{ "BIT_ENABLE_12_15", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE", 0x4d004, 0 },
|
|
{ "DI_ADR0_ADR1", 15, 1 },
|
|
{ "DI_ADR2_ADR3", 14, 1 },
|
|
{ "DI_ADR4_ADR5", 13, 1 },
|
|
{ "DI_ADR6_ADR7", 12, 1 },
|
|
{ "DI_ADR8_ADR9", 11, 1 },
|
|
{ "DI_ADR10_ADR11", 10, 1 },
|
|
{ "DI_ADR12_ADR13", 9, 1 },
|
|
{ "DI_ADR14_ADR15", 8, 1 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY0", 0x4d010, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY1", 0x4d014, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY2", 0x4d018, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY3", 0x4d01c, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY4", 0x4d020, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY5", 0x4d024, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY6", 0x4d028, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY7", 0x4d02c, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL", 0x4d030, 0 },
|
|
{ "ADR_TEST_LANE_PAIR_FAIL", 8, 8 },
|
|
{ "ADR_TEST_DATA_EN", 7, 1 },
|
|
{ "DADR_TEST_MODE", 5, 2 },
|
|
{ "ADR_TEST_4TO1_MODE", 4, 1 },
|
|
{ "ADR_TEST_RESET", 3, 1 },
|
|
{ "ADR_TEST_GEN_EN", 2, 1 },
|
|
{ "ADR_TEST_CLEAR_ERROR", 1, 1 },
|
|
{ "ADR_TEST_CHECK_EN", 0, 1 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0", 0x4d040, 0 },
|
|
{ "EN_SLICE_N_WR_0", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1", 0x4d044, 0 },
|
|
{ "EN_SLICE_N_WR_1", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2", 0x4d048, 0 },
|
|
{ "EN_SLICE_N_WR_2", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3", 0x4d04c, 0 },
|
|
{ "EN_SLICE_N_WR_3", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0", 0x4d050, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1", 0x4d054, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2", 0x4d058, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3", 0x4d05c, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0", 0x4d080, 0 },
|
|
{ "SLICE_SEL_REG_BITS0_1", 14, 2 },
|
|
{ "SLICE_SEL_REG_BITS2_3", 12, 2 },
|
|
{ "SLICE_SEL_REG_BITS4_5", 10, 2 },
|
|
{ "SLICE_SEL_REG_BITS6_7", 8, 2 },
|
|
{ "SLICE_SEL_REG_BITS8_9", 6, 2 },
|
|
{ "SLICE_SEL_REG_BITS10_11", 4, 2 },
|
|
{ "SLICE_SEL_REG_BITS12_13", 2, 2 },
|
|
{ "SLICE_SEL_REG_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1", 0x4d084, 0 },
|
|
{ "SLICE_SEL_REG_BITS0_1", 14, 2 },
|
|
{ "SLICE_SEL_REG_BITS2_3", 12, 2 },
|
|
{ "SLICE_SEL_REG_BITS4_5", 10, 2 },
|
|
{ "SLICE_SEL_REG_BITS6_7", 8, 2 },
|
|
{ "SLICE_SEL_REG_BITS8_9", 6, 2 },
|
|
{ "SLICE_SEL_REG_BITS10_11", 4, 2 },
|
|
{ "SLICE_SEL_REG_BITS12_13", 2, 2 },
|
|
{ "SLICE_SEL_REG_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE", 0x4d060, 0 },
|
|
{ "POST_CURSOR0", 12, 4 },
|
|
{ "POST_CURSOR1", 8, 4 },
|
|
{ "POST_CURSOR2", 4, 4 },
|
|
{ "POST_CURSOR3", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0", 0x4d0a0, 0 },
|
|
{ "POST_CUR_SEL_BITS0_1", 14, 2 },
|
|
{ "POST_CUR_SEL_BITS2_3", 12, 2 },
|
|
{ "POST_CUR_SEL_BITS4_5", 10, 2 },
|
|
{ "POST_CUR_SEL_BITS6_7", 8, 2 },
|
|
{ "POST_CUR_SEL_BITS8_9", 6, 2 },
|
|
{ "POST_CUR_SEL_BITS10_11", 4, 2 },
|
|
{ "POST_CUR_SEL_BITS12_13", 2, 2 },
|
|
{ "POST_CUR_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1", 0x4d0a4, 0 },
|
|
{ "POST_CUR_SEL_BITS0_1", 14, 2 },
|
|
{ "POST_CUR_SEL_BITS2_3", 12, 2 },
|
|
{ "POST_CUR_SEL_BITS4_5", 10, 2 },
|
|
{ "POST_CUR_SEL_BITS6_7", 8, 2 },
|
|
{ "POST_CUR_SEL_BITS8_9", 6, 2 },
|
|
{ "POST_CUR_SEL_BITS10_11", 4, 2 },
|
|
{ "POST_CUR_SEL_BITS12_13", 2, 2 },
|
|
{ "POST_CUR_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE", 0x4d068, 0 },
|
|
{ "SLEW_CTL0", 12, 4 },
|
|
{ "SLEW_CTL1", 8, 4 },
|
|
{ "SLEW_CTL2", 4, 4 },
|
|
{ "SLEW_CTL3", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0", 0x4d0a8, 0 },
|
|
{ "SLEW_CTL_SEL_BITS0_1", 14, 2 },
|
|
{ "SLEW_CTL_SEL_BITS2_3", 12, 2 },
|
|
{ "SLEW_CTL_SEL_BITS4_5", 10, 2 },
|
|
{ "SLEW_CTL_SEL_BITS6_7", 8, 2 },
|
|
{ "SLEW_CTL_SEL_BITS8_9", 6, 2 },
|
|
{ "SLEW_CTL_SEL_BITS10_11", 4, 2 },
|
|
{ "SLEW_CTL_SEL_BITS12_13", 2, 2 },
|
|
{ "SLEW_CTL_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1", 0x4d0ac, 0 },
|
|
{ "SLEW_CTL_SEL_BITS0_1", 14, 2 },
|
|
{ "SLEW_CTL_SEL_BITS2_3", 12, 2 },
|
|
{ "SLEW_CTL_SEL_BITS4_5", 10, 2 },
|
|
{ "SLEW_CTL_SEL_BITS6_7", 8, 2 },
|
|
{ "SLEW_CTL_SEL_BITS8_9", 6, 2 },
|
|
{ "SLEW_CTL_SEL_BITS10_11", 4, 2 },
|
|
{ "SLEW_CTL_SEL_BITS12_13", 2, 2 },
|
|
{ "SLEW_CTL_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_POWERDOWN_2", 0x4d0b0, 0 },
|
|
{ "ADR_LANE_0_11_PD", 4, 12 },
|
|
{ "ADR_LANE_12_15_PD", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_BIT_ENABLE", 0x4d200, 0 },
|
|
{ "BIT_ENABLE_0_11", 4, 12 },
|
|
{ "BIT_ENABLE_12_15", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE", 0x4d204, 0 },
|
|
{ "DI_ADR0_ADR1", 15, 1 },
|
|
{ "DI_ADR2_ADR3", 14, 1 },
|
|
{ "DI_ADR4_ADR5", 13, 1 },
|
|
{ "DI_ADR6_ADR7", 12, 1 },
|
|
{ "DI_ADR8_ADR9", 11, 1 },
|
|
{ "DI_ADR10_ADR11", 10, 1 },
|
|
{ "DI_ADR12_ADR13", 9, 1 },
|
|
{ "DI_ADR14_ADR15", 8, 1 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY0", 0x4d210, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY1", 0x4d214, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY2", 0x4d218, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY3", 0x4d21c, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY4", 0x4d220, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY5", 0x4d224, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY6", 0x4d228, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DELAY7", 0x4d22c, 0 },
|
|
{ "ADR_DELAY_BITS1_7", 8, 7 },
|
|
{ "ADR_DELAY_BITS9_15", 0, 7 },
|
|
{ "MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL", 0x4d230, 0 },
|
|
{ "ADR_TEST_LANE_PAIR_FAIL", 8, 8 },
|
|
{ "ADR_TEST_DATA_EN", 7, 1 },
|
|
{ "DADR_TEST_MODE", 5, 2 },
|
|
{ "ADR_TEST_4TO1_MODE", 4, 1 },
|
|
{ "ADR_TEST_RESET", 3, 1 },
|
|
{ "ADR_TEST_GEN_EN", 2, 1 },
|
|
{ "ADR_TEST_CLEAR_ERROR", 1, 1 },
|
|
{ "ADR_TEST_CHECK_EN", 0, 1 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0", 0x4d240, 0 },
|
|
{ "EN_SLICE_N_WR_0", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1", 0x4d244, 0 },
|
|
{ "EN_SLICE_N_WR_1", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2", 0x4d248, 0 },
|
|
{ "EN_SLICE_N_WR_2", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3", 0x4d24c, 0 },
|
|
{ "EN_SLICE_N_WR_3", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0", 0x4d250, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1", 0x4d254, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2", 0x4d258, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3", 0x4d25c, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0", 0x4d280, 0 },
|
|
{ "SLICE_SEL_REG_BITS0_1", 14, 2 },
|
|
{ "SLICE_SEL_REG_BITS2_3", 12, 2 },
|
|
{ "SLICE_SEL_REG_BITS4_5", 10, 2 },
|
|
{ "SLICE_SEL_REG_BITS6_7", 8, 2 },
|
|
{ "SLICE_SEL_REG_BITS8_9", 6, 2 },
|
|
{ "SLICE_SEL_REG_BITS10_11", 4, 2 },
|
|
{ "SLICE_SEL_REG_BITS12_13", 2, 2 },
|
|
{ "SLICE_SEL_REG_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1", 0x4d284, 0 },
|
|
{ "SLICE_SEL_REG_BITS0_1", 14, 2 },
|
|
{ "SLICE_SEL_REG_BITS2_3", 12, 2 },
|
|
{ "SLICE_SEL_REG_BITS4_5", 10, 2 },
|
|
{ "SLICE_SEL_REG_BITS6_7", 8, 2 },
|
|
{ "SLICE_SEL_REG_BITS8_9", 6, 2 },
|
|
{ "SLICE_SEL_REG_BITS10_11", 4, 2 },
|
|
{ "SLICE_SEL_REG_BITS12_13", 2, 2 },
|
|
{ "SLICE_SEL_REG_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE", 0x4d260, 0 },
|
|
{ "POST_CURSOR0", 12, 4 },
|
|
{ "POST_CURSOR1", 8, 4 },
|
|
{ "POST_CURSOR2", 4, 4 },
|
|
{ "POST_CURSOR3", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0", 0x4d2a0, 0 },
|
|
{ "POST_CUR_SEL_BITS0_1", 14, 2 },
|
|
{ "POST_CUR_SEL_BITS2_3", 12, 2 },
|
|
{ "POST_CUR_SEL_BITS4_5", 10, 2 },
|
|
{ "POST_CUR_SEL_BITS6_7", 8, 2 },
|
|
{ "POST_CUR_SEL_BITS8_9", 6, 2 },
|
|
{ "POST_CUR_SEL_BITS10_11", 4, 2 },
|
|
{ "POST_CUR_SEL_BITS12_13", 2, 2 },
|
|
{ "POST_CUR_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1", 0x4d2a4, 0 },
|
|
{ "POST_CUR_SEL_BITS0_1", 14, 2 },
|
|
{ "POST_CUR_SEL_BITS2_3", 12, 2 },
|
|
{ "POST_CUR_SEL_BITS4_5", 10, 2 },
|
|
{ "POST_CUR_SEL_BITS6_7", 8, 2 },
|
|
{ "POST_CUR_SEL_BITS8_9", 6, 2 },
|
|
{ "POST_CUR_SEL_BITS10_11", 4, 2 },
|
|
{ "POST_CUR_SEL_BITS12_13", 2, 2 },
|
|
{ "POST_CUR_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE", 0x4d268, 0 },
|
|
{ "SLEW_CTL0", 12, 4 },
|
|
{ "SLEW_CTL1", 8, 4 },
|
|
{ "SLEW_CTL2", 4, 4 },
|
|
{ "SLEW_CTL3", 0, 4 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0", 0x4d2a8, 0 },
|
|
{ "SLEW_CTL_SEL_BITS0_1", 14, 2 },
|
|
{ "SLEW_CTL_SEL_BITS2_3", 12, 2 },
|
|
{ "SLEW_CTL_SEL_BITS4_5", 10, 2 },
|
|
{ "SLEW_CTL_SEL_BITS6_7", 8, 2 },
|
|
{ "SLEW_CTL_SEL_BITS8_9", 6, 2 },
|
|
{ "SLEW_CTL_SEL_BITS10_11", 4, 2 },
|
|
{ "SLEW_CTL_SEL_BITS12_13", 2, 2 },
|
|
{ "SLEW_CTL_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1", 0x4d2ac, 0 },
|
|
{ "SLEW_CTL_SEL_BITS0_1", 14, 2 },
|
|
{ "SLEW_CTL_SEL_BITS2_3", 12, 2 },
|
|
{ "SLEW_CTL_SEL_BITS4_5", 10, 2 },
|
|
{ "SLEW_CTL_SEL_BITS6_7", 8, 2 },
|
|
{ "SLEW_CTL_SEL_BITS8_9", 6, 2 },
|
|
{ "SLEW_CTL_SEL_BITS10_11", 4, 2 },
|
|
{ "SLEW_CTL_SEL_BITS12_13", 2, 2 },
|
|
{ "SLEW_CTL_SEL_BITS14_15", 0, 2 },
|
|
{ "MC_ADR_DDRPHY_ADR_POWERDOWN_2", 0x4d2b0, 0 },
|
|
{ "ADR_LANE_0_11_PD", 4, 12 },
|
|
{ "ADR_LANE_12_15_PD", 0, 4 },
|
|
{ "MC_DDRPHY_ADR_PLL_VREG_CONFIG_0", 0x4e0c0, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_ADR_PLL_VREG_CONFIG_1", 0x4e0c4, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "VREG_VREGSPARE", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "INTERP_SIG_SLEW_0_3", 1, 4 },
|
|
{ "ANALOG_WRAPON", 0, 1 },
|
|
{ "MC_DDRPHY_ADR_SYSCLK_CNTL_PR", 0x4e0c8, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESE", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "CE0DLTVCC", 0, 2 },
|
|
{ "MC_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET", 0x4e0cc, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_ADR_SYSCLK_PR_VALUE_RO", 0x4e0d0, 0 },
|
|
{ "SLEW_LATE_SAMPLE", 15, 1 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "BB_LOCK", 7, 1 },
|
|
{ "SLEW_EARLY_SAMPLE", 6, 1 },
|
|
{ "SLEW_DONE_STATUS", 4, 2 },
|
|
{ "SLEW_CNTL", 0, 4 },
|
|
{ "MC_DDRPHY_ADR_GMTEST_ATEST_CNTL", 0x4e0d4, 0 },
|
|
{ "FLUSH", 15, 1 },
|
|
{ "GIANT_MUX_TEST_EN", 14, 1 },
|
|
{ "GIANT_MUX_TEST_VAL", 13, 1 },
|
|
{ "HS_PROBE_A_SEL_", 8, 4 },
|
|
{ "HS_PROBE_B_SEL_", 4, 4 },
|
|
{ "ATEST1CTL0", 3, 1 },
|
|
{ "ATEST1CTL1", 2, 1 },
|
|
{ "ATEST1CTL2", 1, 1 },
|
|
{ "ATEST1CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A0", 0x4e0d8, 0 },
|
|
{ "MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A1", 0x4e0dc, 0 },
|
|
{ "MC_DDRPHY_ADR_POWERDOWN_1", 0x4e0e0, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "ADR_RX_PD", 4, 1 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "DVCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_ADR_SLEW_CAL_CNTL", 0x4e0e4, 0 },
|
|
{ "SLEW_CAL_ENABLE", 15, 1 },
|
|
{ "SLEW_CAL_START", 14, 1 },
|
|
{ "SLEW_CAL_OVERRIDE_EN", 12, 1 },
|
|
{ "SLEW_CAL_OVERRIDE", 8, 4 },
|
|
{ "SLEW_TARGET_PR_OFFSET", 0, 5 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x4c000, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x4c004, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "WRAPSEL", 5, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x4c1f0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x4c1f4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x4c008, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4c00c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x4c010, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x4c014, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x4c1f8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x4c018, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4c01c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x4c1cc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x4c1d0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x4c0c0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x4c0c4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x4c024, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x4c170, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x4c174, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x4c0e0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x4c0e4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x4c0e8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x4c0ec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x4c0f0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x4c0f4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x4c0f8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x4c0fc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x4c100, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x4c104, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x4c108, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4c10c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x4c110, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x4c114, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x4c118, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4c11c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x4c120, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x4c124, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x4c128, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4c12c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x4c130, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x4c134, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x4c138, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4c13c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x4c140, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x4c144, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x4c148, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4c14c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x4c150, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x4c154, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x4c158, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4c15c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x4c160, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x4c164, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x4c168, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4c16c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x4c030, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x4c034, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x4c1c0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x4c1c4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x4c1c8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x4c180, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x4c184, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x4c188, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4c18c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x4c190, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x4c194, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x4c198, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4c19c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x4c1a0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x4c1a4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x4c1a8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x4c1ac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x4c028, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x4c038, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4c03c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x4c040, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x4c044, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4c04c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x4c050, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x4c054, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4c05c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x4c060, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "DDONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x4c064, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x4c068, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4c06c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x4c070, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x4c1d8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x4c1dc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x4c1e0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x4c1e8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x4c1e4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x4c1ec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x4c1d4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x4c074, 0 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x4c020, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x4c0c8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x4c0cc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x4c0d0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c078, 0 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c0d4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c0d8, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c1b4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x4c1b8, 0 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x4c0dc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4c02c, 0 },
|
|
{ "HS_PROBE_A_SEL", 11, 5 },
|
|
{ "HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c1fc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "ADR_RX_PD", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "DVCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c048, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DYN_MCTERM_CNTL_EN", 14, 1 },
|
|
{ "DYN_RX_GATE_CNTL_EN", 13, 1 },
|
|
{ "CALGATE_ON", 12, 1 },
|
|
{ "PER_RDCLK_UPDATE_DIS", 11, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x4c200, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x4c204, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "WRAPSEL", 5, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x4c3f0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x4c3f4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x4c208, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4c20c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x4c210, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x4c214, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x4c3f8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x4c218, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4c21c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x4c3cc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x4c3d0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x4c2c0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x4c2c4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x4c224, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x4c370, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x4c374, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x4c2e0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x4c2e4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x4c2e8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x4c2ec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x4c2f0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x4c2f4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x4c2f8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x4c2fc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x4c300, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x4c304, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x4c308, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4c30c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x4c310, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x4c314, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x4c318, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4c31c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x4c320, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x4c324, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x4c328, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4c32c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x4c330, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x4c334, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x4c338, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4c33c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x4c340, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x4c344, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x4c348, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4c34c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x4c350, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x4c354, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x4c358, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4c35c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x4c360, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x4c364, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x4c368, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4c36c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x4c230, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x4c234, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x4c3c0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x4c3c4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x4c3c8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x4c380, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x4c384, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x4c388, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4c38c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x4c390, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x4c394, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x4c398, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4c39c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x4c3a0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x4c3a4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x4c3a8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x4c3ac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x4c228, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x4c238, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4c23c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x4c240, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x4c244, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4c24c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x4c250, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x4c254, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4c25c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x4c260, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "DDONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x4c264, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x4c268, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4c26c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x4c270, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x4c3d8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x4c3dc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x4c3e0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x4c3e8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x4c3e4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x4c3ec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x4c3d4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x4c274, 0 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x4c220, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x4c2c8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x4c2cc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x4c2d0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c278, 0 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c2d4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c2d8, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c3b4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x4c3b8, 0 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x4c2dc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4c22c, 0 },
|
|
{ "HS_PROBE_A_SEL", 11, 5 },
|
|
{ "HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c3fc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "ADR_RX_PD", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "DVCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c248, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DYN_MCTERM_CNTL_EN", 14, 1 },
|
|
{ "DYN_RX_GATE_CNTL_EN", 13, 1 },
|
|
{ "CALGATE_ON", 12, 1 },
|
|
{ "PER_RDCLK_UPDATE_DIS", 11, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x4c400, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x4c404, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "WRAPSEL", 5, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x4c5f0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x4c5f4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x4c408, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4c40c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x4c410, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x4c414, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x4c5f8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x4c418, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4c41c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x4c5cc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x4c5d0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x4c4c0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x4c4c4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x4c424, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x4c570, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x4c574, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x4c4e0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x4c4e4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x4c4e8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x4c4ec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x4c4f0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x4c4f4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x4c4f8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x4c4fc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x4c500, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x4c504, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x4c508, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4c50c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x4c510, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x4c514, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x4c518, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4c51c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x4c520, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x4c524, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x4c528, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4c52c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x4c530, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x4c534, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x4c538, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4c53c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x4c540, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x4c544, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x4c548, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4c54c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x4c550, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x4c554, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x4c558, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4c55c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x4c560, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x4c564, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x4c568, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4c56c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x4c430, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x4c434, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x4c5c0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x4c5c4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x4c5c8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x4c580, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x4c584, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x4c588, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4c58c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x4c590, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x4c594, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x4c598, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4c59c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x4c5a0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x4c5a4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x4c5a8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x4c5ac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x4c428, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x4c438, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4c43c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x4c440, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x4c444, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4c44c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x4c450, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x4c454, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4c45c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x4c460, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "DDONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x4c464, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x4c468, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4c46c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x4c470, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x4c5d8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x4c5dc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x4c5e0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x4c5e8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x4c5e4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x4c5ec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x4c5d4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x4c474, 0 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x4c420, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x4c4c8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x4c4cc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x4c4d0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c478, 0 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c4d4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c4d8, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c5b4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x4c5b8, 0 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x4c4dc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4c42c, 0 },
|
|
{ "HS_PROBE_A_SEL", 11, 5 },
|
|
{ "HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c5fc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "ADR_RX_PD", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "DVCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c448, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DYN_MCTERM_CNTL_EN", 14, 1 },
|
|
{ "DYN_RX_GATE_CNTL_EN", 13, 1 },
|
|
{ "CALGATE_ON", 12, 1 },
|
|
{ "PER_RDCLK_UPDATE_DIS", 11, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x4c600, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x4c604, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "WRAPSEL", 5, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x4c7f0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x4c7f4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x4c608, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4c60c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x4c610, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x4c614, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x4c7f8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x4c618, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4c61c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x4c7cc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x4c7d0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x4c6c0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x4c6c4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x4c624, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x4c770, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x4c774, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x4c6e0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x4c6e4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x4c6e8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x4c6ec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x4c6f0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x4c6f4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x4c6f8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x4c6fc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x4c700, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x4c704, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x4c708, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4c70c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x4c710, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x4c714, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x4c718, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4c71c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x4c720, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x4c724, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x4c728, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4c72c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x4c730, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x4c734, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x4c738, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4c73c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x4c740, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x4c744, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x4c748, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4c74c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x4c750, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x4c754, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x4c758, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4c75c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x4c760, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x4c764, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x4c768, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4c76c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x4c630, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x4c634, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x4c7c0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x4c7c4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x4c7c8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x4c780, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x4c784, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x4c788, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4c78c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x4c790, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x4c794, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x4c798, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4c79c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x4c7a0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x4c7a4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x4c7a8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x4c7ac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x4c628, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x4c638, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4c63c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x4c640, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x4c644, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4c64c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x4c650, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x4c654, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4c65c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x4c660, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "DDONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x4c664, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x4c668, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4c66c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x4c670, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x4c7d8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x4c7dc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x4c7e0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x4c7e8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x4c7e4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x4c7ec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x4c7d4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x4c674, 0 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x4c620, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x4c6c8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x4c6cc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x4c6d0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c678, 0 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c6d4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c6d8, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c7b4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x4c7b8, 0 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x4c6dc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4c62c, 0 },
|
|
{ "HS_PROBE_A_SEL", 11, 5 },
|
|
{ "HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c7fc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "ADR_RX_PD", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "DVCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c648, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DYN_MCTERM_CNTL_EN", 14, 1 },
|
|
{ "DYN_RX_GATE_CNTL_EN", 13, 1 },
|
|
{ "CALGATE_ON", 12, 1 },
|
|
{ "PER_RDCLK_UPDATE_DIS", 11, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE0", 0x4c800, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_ENABLE1", 0x4c804, 0 },
|
|
{ "DATA_BIT_ENABLE_16_23", 8, 8 },
|
|
{ "DFT_FORCE_OUTPUTS", 7, 1 },
|
|
{ "DFT_PRBS7_GEN_EN", 6, 1 },
|
|
{ "WRAPSEL", 5, 1 },
|
|
{ "MRS_CMD_DATA_N0", 3, 1 },
|
|
{ "MRS_CMD_DATA_N1", 2, 1 },
|
|
{ "MRS_CMD_DATA_N2", 1, 1 },
|
|
{ "MRS_CMD_DATA_N3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP", 0x4c9f0, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP", 0x4c9f4, 0 },
|
|
{ "DATA_BIT_DISABLE_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR0", 0x4c808, 0 },
|
|
{ "MC_DDRPHY_DP18_DATA_BIT_DIR1", 0x4c80c, 0 },
|
|
{ "DATA_BIT_DIR_16_23", 8, 8 },
|
|
{ "WL_ADVANCE_DISABLE", 7, 1 },
|
|
{ "DISABLE_PING_PONG", 6, 1 },
|
|
{ "DELAY_PING_PONG_HALF", 5, 1 },
|
|
{ "ADVANCE_PING_PONG", 4, 1 },
|
|
{ "ATEST_MUX_CTL0", 3, 1 },
|
|
{ "ATEST_MUX_CTL1", 2, 1 },
|
|
{ "ATEST_MUX_CTL2", 1, 1 },
|
|
{ "ATEST_MUX_CTL3", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR", 0x4c810, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_EN_RP", 0x4c814, 0 },
|
|
{ "QUAD0_CLK16_BIT0", 15, 1 },
|
|
{ "QUAD1_CLK16_BIT1", 14, 1 },
|
|
{ "QUAD2_CLK16_BIT2", 13, 1 },
|
|
{ "QUAD3_CLK16_BIT3", 12, 1 },
|
|
{ "QUAD0_CLK18_BIT4", 11, 1 },
|
|
{ "QUAD1_CLK18_BIT5", 10, 1 },
|
|
{ "QUAD2_CLK20_BIT6", 9, 1 },
|
|
{ "QUAD3_CLK20_BIT7", 8, 1 },
|
|
{ "QUAD2_CLK22_BIT8", 7, 1 },
|
|
{ "QUAD3_CLK22_BIT9", 6, 1 },
|
|
{ "CLK16_SINGLE_ENDED_BIT10", 5, 1 },
|
|
{ "CLK18_SINGLE_ENDED_BIT11", 4, 1 },
|
|
{ "CLK20_SINGLE_ENDED_BIT12", 3, 1 },
|
|
{ "CLK22_SINGLE_ENDED_BIT13", 2, 1 },
|
|
{ "QUAD2_CLK18_BIT14", 1, 1 },
|
|
{ "QUAD3_CLK18_BIT15", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_DQ_WR_OFFSET_RP", 0x4c9f8, 0 },
|
|
{ "DQ_WR_OFFSET_N0", 12, 4 },
|
|
{ "DQ_WR_OFFSET_N1", 8, 4 },
|
|
{ "DQ_WR_OFFSET_N2", 4, 4 },
|
|
{ "DQ_WR_OFFSET_N3", 0, 4 },
|
|
{ "MC_DDRPHY_DP18_RX_PEAK_AMP", 0x4c818, 0 },
|
|
{ "PEAK_AMP_CTL_SIDE0", 13, 3 },
|
|
{ "PEAK_AMP_CTL_SIDE1", 9, 3 },
|
|
{ "SxMCVREF_0_3", 4, 4 },
|
|
{ "SxPODVREF", 3, 1 },
|
|
{ "DISABLE_TERMINATION", 2, 1 },
|
|
{ "READ_CENTERING_MODE", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR", 0x4c81c, 0 },
|
|
{ "SYSCLK_ENABLE", 15, 1 },
|
|
{ "SYSCLK_ROT_OVERRIDE", 8, 7 },
|
|
{ "SYSCLK_ROT_OVERRIDE_EN", 7, 1 },
|
|
{ "SYSCLK_PHASE_ALIGN_RESET", 6, 1 },
|
|
{ "SYSCLK_PHASE_CNTL_EN", 5, 1 },
|
|
{ "SYSCLK_PHASE_DEFAULT_EN", 4, 1 },
|
|
{ "SYSCLK_POS_EDGE_ALIGN", 3, 1 },
|
|
{ "CONTINUOUS_UPDATE", 2, 1 },
|
|
{ "MC_DDRPHY_DP18_SYSCLK_PR_VALUE", 0x4c9cc, 0 },
|
|
{ "SYSCLK_ROT", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_WRCLK_PR", 0x4c9d0, 0 },
|
|
{ "TSYS_WRCLK", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR", 0x4c8c0, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR", 0x4c8c4, 0 },
|
|
{ "DQSCLK_ROT_CLK_N0_N2", 8, 7 },
|
|
{ "DQSCLK_ROT_CLK_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR", 0x4c824, 0 },
|
|
{ "DQSCLK_SELECT0", 14, 2 },
|
|
{ "RDCLK_SELECT0", 12, 2 },
|
|
{ "DQSCLK_SELECT1", 10, 2 },
|
|
{ "RDCLK_SELECT1", 8, 2 },
|
|
{ "DQSCLK_SELECT2", 6, 2 },
|
|
{ "RDCLK_SELECT2", 4, 2 },
|
|
{ "DQSCLK_SELECT3", 2, 2 },
|
|
{ "RDCLK_SELECT3", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR", 0x4c970, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR", 0x4c974, 0 },
|
|
{ "INITIAL_DQS_ROT_N0_N2", 8, 7 },
|
|
{ "INITIAL_DQS_ROT_N1_N3", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP", 0x4c8e0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP", 0x4c8e4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP", 0x4c8e8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP", 0x4c8ec, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP", 0x4c8f0, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP", 0x4c8f4, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP", 0x4c8f8, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP", 0x4c8fc, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP", 0x4c900, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP", 0x4c904, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP", 0x4c908, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP", 0x4c90c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP", 0x4c910, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP", 0x4c914, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP", 0x4c918, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP", 0x4c91c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP", 0x4c920, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP", 0x4c924, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP", 0x4c928, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP", 0x4c92c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP", 0x4c930, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP", 0x4c934, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP", 0x4c938, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP", 0x4c93c, 0 },
|
|
{ "WR_DELAY", 6, 10 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR", 0x4c940, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR", 0x4c944, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR", 0x4c948, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR", 0x4c94c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR", 0x4c950, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR", 0x4c954, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR", 0x4c958, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR", 0x4c95c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR", 0x4c960, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR", 0x4c964, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR", 0x4c968, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR", 0x4c96c, 0 },
|
|
{ "RD_DELAY_BITS0_6", 9, 7 },
|
|
{ "RD_DELAY_BITS8_14", 1, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR", 0x4c830, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR", 0x4c834, 0 },
|
|
{ "OFFSET_BITS1_7", 8, 7 },
|
|
{ "OFFSET_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE0", 0x4c9c0, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_TIMING_REFERENCE1", 0x4c9c4, 0 },
|
|
{ "REFERENCE_BITS1_7", 8, 7 },
|
|
{ "REFERENCE_BITS9_15", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE", 0x4c9c8, 0 },
|
|
{ "REFERENCE", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR", 0x4c980, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR", 0x4c984, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR", 0x4c988, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR", 0x4c98c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR", 0x4c990, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR", 0x4c994, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR", 0x4c998, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR", 0x4c99c, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR", 0x4c9a0, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR", 0x4c9a4, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR", 0x4c9a8, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR", 0x4c9ac, 0 },
|
|
{ "RD_EYE_SIZE_BITS2_7", 8, 6 },
|
|
{ "RD_EYE_SIZE_BITS10_15", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DRIFT_LIMITS", 0x4c828, 0 },
|
|
{ "MIN_RD_EYE_SIZE", 8, 6 },
|
|
{ "MAX_DQS_DRIFT", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS0", 0x4c838, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS1", 0x4c83c, 0 },
|
|
{ "LEADING_EDGE_NOT_FOUND_1", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS2", 0x4c840, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_LVL_STATUS3", 0x4c844, 0 },
|
|
{ "TRAILING_EDGE_NOT_FOUND_16_23", 8, 8 },
|
|
{ "MC_DDRPHY_DP18_DQS_GATE_DELAY_RP", 0x4c84c, 0 },
|
|
{ "DQS_GATE_DELAY_N0", 12, 3 },
|
|
{ "DQS_GATE_DELAY_N1", 8, 3 },
|
|
{ "DQS_GATE_DELAY_N2", 4, 3 },
|
|
{ "DQS_GATE_DELAY_N3", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_RD_STATUS0", 0x4c850, 0 },
|
|
{ "NO_EYE_DETECTED", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3", 5, 1 },
|
|
{ "EYE_CLIPPING", 4, 1 },
|
|
{ "NO_DQS", 3, 1 },
|
|
{ "NO_LOCK", 2, 1 },
|
|
{ "DRIFT_ERROR", 1, 1 },
|
|
{ "MIN_EYE", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_ERROR_MASK0", 0x4c854, 0 },
|
|
{ "NO_EYE_DETECTED_MASK", 15, 1 },
|
|
{ "LEADING_EDGE_FOUND_MASK", 14, 1 },
|
|
{ "TRAILING_EDGE_FOUND_MASK", 13, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N0_MASK", 12, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N1_MASK", 11, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N2_MASK", 10, 1 },
|
|
{ "INCOMPLETE_RD_CAL_N3_MASK", 9, 1 },
|
|
{ "COARSE_PATTERN_ERR_N0_MASK", 8, 1 },
|
|
{ "COARSE_PATTERN_ERR_N1_MASK", 7, 1 },
|
|
{ "COARSE_PATTERN_ERR_N2_MASK", 6, 1 },
|
|
{ "COARSE_PATTERN_ERR_N3_MASK", 5, 1 },
|
|
{ "EYE_CLIPPING_MASK", 4, 1 },
|
|
{ "NO_DQS_MASK", 3, 1 },
|
|
{ "NO_LOCK_MASK", 2, 1 },
|
|
{ "DRIFT_ERROR_MASK", 1, 1 },
|
|
{ "MIN_EYE_MASK", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_LVL_STATUS0", 0x4c85c, 0 },
|
|
{ "CLK_LEVEL", 14, 2 },
|
|
{ "FINE_STEPPING", 13, 1 },
|
|
{ "DONE", 12, 1 },
|
|
{ "WL_ERR_CLK16_ST", 11, 1 },
|
|
{ "WL_ERR_CLK18_ST", 10, 1 },
|
|
{ "WL_ERR_CLK20_ST", 9, 1 },
|
|
{ "WL_ERR_CLK22_ST", 8, 1 },
|
|
{ "ZERO_DETECTED", 7, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS0", 0x4c860, 0 },
|
|
{ "BIT_CENTERED", 11, 5 },
|
|
{ "SMALL_STEP_LEFT", 10, 1 },
|
|
{ "BIG_STEP_RIGHT", 9, 1 },
|
|
{ "MATCH_STEP_RIGHT", 8, 1 },
|
|
{ "JUMP_BACK_RIGHT", 7, 1 },
|
|
{ "SMALL_STEP_RIGHT", 6, 1 },
|
|
{ "DDONE", 5, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS1", 0x4c864, 0 },
|
|
{ "FW_LEFT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_CNTR_STATUS2", 0x4c868, 0 },
|
|
{ "FW_RIGHT_SIDE", 5, 11 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR0", 0x4c86c, 0 },
|
|
{ "WL_ERR_CLK16", 15, 1 },
|
|
{ "WL_ERR_CLK18", 14, 1 },
|
|
{ "WL_ERR_CLK20", 13, 1 },
|
|
{ "WL_ERR_CLK22", 12, 1 },
|
|
{ "VALID_NS_BIG_L", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L", 6, 1 },
|
|
{ "VALID_NS_BIG_R", 5, 1 },
|
|
{ "INVALID_NS_BIG_R", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R", 2, 1 },
|
|
{ "OFFSET_ERR", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_WR_ERROR_MASK0", 0x4c870, 0 },
|
|
{ "WL_ERR_CLK16_MASK", 15, 1 },
|
|
{ "WL_ERR_CLK18_MASK", 14, 1 },
|
|
{ "WL_ERR_CLK20_MASK", 13, 1 },
|
|
{ "WR_ERR_CLK22_MASK", 12, 1 },
|
|
{ "VALID_NS_BIG_L_MASK", 7, 1 },
|
|
{ "INVALID_NS_SMALL_L_MASK", 6, 1 },
|
|
{ "VALID_NS_BIG_R_MASK", 5, 1 },
|
|
{ "INVALID_NS_BIG_R_MASK", 4, 1 },
|
|
{ "VALID_NS_JUMP_BACK_MASK", 3, 1 },
|
|
{ "INVALID_NS_SMALL_R_MASK", 2, 1 },
|
|
{ "OFFSET_ERR_MASK", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG0", 0x4c9d8, 0 },
|
|
{ "PLL_TUNE_0_2", 13, 3 },
|
|
{ "PLL_TUNECP_0_2", 10, 3 },
|
|
{ "PLL_TUNEF_0_5", 4, 6 },
|
|
{ "PLL_TUNEVCO_0_1", 2, 2 },
|
|
{ "PLL_PLLXTR_0_1", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PLL_CONFIG1", 0x4c9dc, 0 },
|
|
{ "PLL_TUNETDIV_0_2", 13, 3 },
|
|
{ "PLL_TUNEMDIV_0_1", 11, 2 },
|
|
{ "PLL_TUNEATST", 10, 1 },
|
|
{ "VREG_RANGE_0_1", 8, 2 },
|
|
{ "CE0DLTVCCA", 7, 1 },
|
|
{ "VREG_VCCTUNE_0_1", 5, 2 },
|
|
{ "CE0DLTVCCD1", 4, 1 },
|
|
{ "CE0DLTVCCD2", 3, 1 },
|
|
{ "S0INSDLYTAP", 2, 1 },
|
|
{ "S1INSDLYTAP", 1, 1 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_SLICE", 0x4c9e0, 0 },
|
|
{ "EN_SLICE_N_WR", 8, 8 },
|
|
{ "EN_SLICE_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_NFET_TERM", 0x4c9e8, 0 },
|
|
{ "EN_TERM_N_WR", 8, 8 },
|
|
{ "EN_TERM_N_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_SLICE", 0x4c9e4, 0 },
|
|
{ "EN_SLICE_P_WR", 8, 8 },
|
|
{ "EN_SLICE_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_PFET_TERM", 0x4c9ec, 0 },
|
|
{ "EN_TERM_P_WR", 8, 8 },
|
|
{ "EN_TERM_P_WR_FFE", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_IO_TX_CONFIG0", 0x4c9d4, 0 },
|
|
{ "INTERP_SIG_SLEW", 12, 4 },
|
|
{ "POST_CURSOR", 8, 4 },
|
|
{ "SLEW_CTL", 4, 4 },
|
|
{ "MC_DDRPHY_DP18_DFT_WRAP_STATUS", 0x4c874, 0 },
|
|
{ "CHECKER_RESET", 14, 1 },
|
|
{ "SYNC", 6, 6 },
|
|
{ "ERROR", 0, 6 },
|
|
{ "MC_DDRPHY_DP18_DFT_DIG_EYE", 0x4c820, 0 },
|
|
{ "DIGITAL_EYE_EN", 15, 1 },
|
|
{ "BUMP", 14, 1 },
|
|
{ "TRIG_PERIOD", 13, 1 },
|
|
{ "CNTL_POL", 12, 1 },
|
|
{ "CNTL_SRC", 8, 1 },
|
|
{ "DIGITAL_EYE_VALUE", 0, 8 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_0", 0x4c8c8, 0 },
|
|
{ "MEMINTD00_POS", 14, 2 },
|
|
{ "MEMINTD01_PO", 12, 2 },
|
|
{ "MEMINTD02_POS", 10, 2 },
|
|
{ "MEMINTD03_POS", 8, 2 },
|
|
{ "MEMINTD04_POS", 6, 2 },
|
|
{ "MEMINTD05_POS", 4, 2 },
|
|
{ "MEMINTD06_POS", 2, 2 },
|
|
{ "MEMINTD07_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_1", 0x4c8cc, 0 },
|
|
{ "MEMINTD08_POS", 14, 2 },
|
|
{ "MEMINTD09_POS", 12, 2 },
|
|
{ "MEMINTD10_POS", 10, 2 },
|
|
{ "MEMINTD11_POS", 8, 2 },
|
|
{ "MEMINTD12_POS", 6, 2 },
|
|
{ "MEMINTD13_POS", 4, 2 },
|
|
{ "MEMINTD14_POS", 2, 2 },
|
|
{ "MEMINTD15_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_PATTERN_POS_2", 0x4c8d0, 0 },
|
|
{ "MEMINTD16_POS", 14, 2 },
|
|
{ "MEMINTD17_POS", 12, 2 },
|
|
{ "MEMINTD18_POS", 10, 2 },
|
|
{ "MEMINTD19_POS", 8, 2 },
|
|
{ "MEMINTD20_POS", 6, 2 },
|
|
{ "MEMINTD21_POS", 4, 2 },
|
|
{ "MEMINTD22_POS", 2, 2 },
|
|
{ "MEMINTD23_POS", 0, 2 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG0", 0x4c878, 0 },
|
|
{ "SYSCLK_RDCLK_OFFSET", 8, 7 },
|
|
{ "SYSCLK_DQSCLK_OFFSET", 0, 7 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG1", 0x4c8d4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG2", 0x4c8d8, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG3", 0x4c9b4, 0 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG4", 0x4c9b8, 0 },
|
|
{ "MC_DDRPHY_DP18_DQSCLK_OFFSET", 0x4c8dc, 0 },
|
|
{ "DQS_OFFSET", 8, 7 },
|
|
{ "MC_DDRPHY_DP18_DEBUG_SEL", 0x4c82c, 0 },
|
|
{ "HS_PROBE_A_SEL", 11, 5 },
|
|
{ "HS_PROBE_B_SEL", 6, 5 },
|
|
{ "RD_DEBUG_SEL", 3, 3 },
|
|
{ "WR_DEBUG_SEL", 0, 3 },
|
|
{ "MC_DDRPHY_DP18_POWERDOWN_1", 0x4c9fc, 0 },
|
|
{ "MASTER_PD_CNTL", 15, 1 },
|
|
{ "ANALOG_INPUT_STAB2", 14, 1 },
|
|
{ "EYEDAC_PD", 13, 1 },
|
|
{ "ANALOG_OUTPUT_STAB", 9, 1 },
|
|
{ "ANALOG_INPUT_STAB1", 8, 1 },
|
|
{ "SYSCLK_CLK_GATE", 6, 2 },
|
|
{ "WR_FIFO_STAB", 5, 1 },
|
|
{ "ADR_RX_PD", 4, 1 },
|
|
{ "DP18_RX_PD", 2, 2 },
|
|
{ "TX_TRISTATE_CNTL", 1, 1 },
|
|
{ "DVCC_REG_PD", 0, 1 },
|
|
{ "MC_DDRPHY_DP18_RD_DIA_CONFIG5", 0x4c848, 0 },
|
|
{ "DYN_POWER_CNTL_EN", 15, 1 },
|
|
{ "DYN_MCTERM_CNTL_EN", 14, 1 },
|
|
{ "DYN_RX_GATE_CNTL_EN", 13, 1 },
|
|
{ "CALGATE_ON", 12, 1 },
|
|
{ "PER_RDCLK_UPDATE_DIS", 11, 1 },
|
|
{ "MC_DDRPHY_SEQ_RD_WR_DATA0", 0x4f200, 0 },
|
|
{ "MC_DDRPHY_SEQ_RD_WR_DATA1", 0x4f204, 0 },
|
|
{ "MC_DDRPHY_SEQ_CONFIG0", 0x4f208, 0 },
|
|
{ "MPR_PATTERN_BIT", 15, 1 },
|
|
{ "TWO_CYCLE_ADDR_EN", 14, 1 },
|
|
{ "MR_MASK_EN", 10, 4 },
|
|
{ "MC_DDRPHY_SEQ_RESERVED_ADDR0", 0x4f20c, 0 },
|
|
{ "MC_DDRPHY_SEQ_RESERVED_ADDR1", 0x4f210, 0 },
|
|
{ "MC_DDRPHY_SEQ_RESERVED_ADDR2", 0x4f214, 0 },
|
|
{ "MC_DDRPHY_SEQ_RESERVED_ADDR3", 0x4f218, 0 },
|
|
{ "MC_DDRPHY_SEQ_RESERVED_ADDR4", 0x4f21c, 0 },
|
|
{ "MC_DDRPHY_SEQ_ERROR_STATUS0", 0x4f220, 0 },
|
|
{ "MULTIPLE_REQ_ERROR", 15, 1 },
|
|
{ "INVALID_REQTYPE_ERRO", 14, 1 },
|
|
{ "EARLY_REQ_ERROR", 13, 1 },
|
|
{ "MULTIPLE_REQ_SOURCE", 10, 3 },
|
|
{ "INVALID_REQTYPE", 6, 4 },
|
|
{ "INVALID_REQ_SOURCE", 3, 3 },
|
|
{ "EARLY_REQ_SOURCE", 0, 3 },
|
|
{ "MC_DDRPHY_SEQ_ERROR_MASK0", 0x4f224, 0 },
|
|
{ "MULT_REQ_ERR_MASK", 15, 1 },
|
|
{ "INVALID_REQTYPE_ERR_MASK", 14, 1 },
|
|
{ "EARLY_REQ_ERR_MASK", 13, 1 },
|
|
{ "MC_DDRPHY_SEQ_ODT_WR_CONFIG0", 0x4f228, 0 },
|
|
{ "ODT_WR_VALUES_BITS0_7", 8, 8 },
|
|
{ "ODT_WR_VALUES_BITS8_15", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_WR_CONFIG1", 0x4f22c, 0 },
|
|
{ "ODT_WR_VALUES_BITS0_7", 8, 8 },
|
|
{ "ODT_WR_VALUES_BITS8_15", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_WR_CONFIG2", 0x4f230, 0 },
|
|
{ "ODT_WR_VALUES_BITS0_7", 8, 8 },
|
|
{ "ODT_WR_VALUES_BITS8_15", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_WR_CONFIG3", 0x4f234, 0 },
|
|
{ "ODT_WR_VALUES_BITS0_7", 8, 8 },
|
|
{ "ODT_WR_VALUES_BITS8_15", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_RD_CONFIG0", 0x4f238, 0 },
|
|
{ "ODT_RD_VALUES_x2", 8, 8 },
|
|
{ "ODT_RD_VALUES_x2plus1", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_RD_CONFIG1", 0x4f23c, 0 },
|
|
{ "ODT_RD_VALUES_x2", 8, 8 },
|
|
{ "ODT_RD_VALUES_x2plus1", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_RD_CONFIG2", 0x4f240, 0 },
|
|
{ "ODT_RD_VALUES_x2", 8, 8 },
|
|
{ "ODT_RD_VALUES_x2plus1", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_ODT_RD_CONFIG3", 0x4f244, 0 },
|
|
{ "ODT_RD_VALUES_x2", 8, 8 },
|
|
{ "ODT_RD_VALUES_x2plus1", 0, 8 },
|
|
{ "MC_DDRPHY_SEQ_MEM_TIMING_PARAM0", 0x4f248, 0 },
|
|
{ "TMOD_CYCLES", 12, 4 },
|
|
{ "TRCD_CYCLES", 8, 4 },
|
|
{ "TRP_CYCLES", 4, 4 },
|
|
{ "TRFC_CYCLES", 0, 4 },
|
|
{ "MC_DDRPHY_SEQ_MEM_TIMING_PARAM1", 0x4f24c, 0 },
|
|
{ "TZQINIT_CYCLES", 12, 4 },
|
|
{ "TZQCS_CYCLES", 8, 4 },
|
|
{ "TWLDQSEN_CYCLES", 4, 4 },
|
|
{ "TWRMRD_CYCLES", 0, 4 },
|
|
{ "MC_DDRPHY_SEQ_MEM_TIMING_PARAM2", 0x4f250, 0 },
|
|
{ "TODTLON_OFF_CYCLES", 12, 4 },
|
|
{ "TRC_CYCLES", 8, 4 },
|
|
{ "TMRSC_CYCLES", 4, 4 },
|
|
{ "MC_DDRPHY_WC_CONFIG0", 0x4f600, 0 },
|
|
{ "TWLO_TWLOE", 8, 8 },
|
|
{ "WL_ONE_DQS_PULSE", 7, 1 },
|
|
{ "FW_WR_RD", 1, 6 },
|
|
{ "CUSTOM_INIT_WRITE", 0, 1 },
|
|
{ "MC_DDRPHY_WC_CONFIG1", 0x4f604, 0 },
|
|
{ "BIG_STEP", 12, 4 },
|
|
{ "SMALL_STEP", 9, 3 },
|
|
{ "WR_PRE_DLY", 3, 6 },
|
|
{ "MC_DDRPHY_WC_CONFIG2", 0x4f608, 0 },
|
|
{ "NUM_VALID_SAMPLES", 12, 4 },
|
|
{ "FW_RD_WR", 6, 6 },
|
|
{ "EN_RESET_WR_DELAY_WL", 0, 1 },
|
|
{ "MC_DDRPHY_WC_CONFIG3", 0x4f614, 0 },
|
|
{ "DDR4_MRS_CMD_DQ_EN", 15, 1 },
|
|
{ "MRS_CMD_DQ_ON", 9, 6 },
|
|
{ "MRS_CMD_DQ_OFF", 3, 6 },
|
|
{ "MC_DDRPHY_WC_WRCLK_CNTL", 0x4f618, 0 },
|
|
{ "WRCLK_CAL_START", 15, 1 },
|
|
{ "WRCLK_CAL_DONE", 14, 1 },
|
|
{ "MC_DDRPHY_WC_ERROR_STATUS0", 0x4f60c, 0 },
|
|
{ "WR_CNTL_ERROR", 15, 1 },
|
|
{ "MC_DDRPHY_WC_ERROR_MASK0", 0x4f610, 0 },
|
|
{ "WR_CNTL_ERROR_MASK", 15, 1 },
|
|
{ "MC_DDRPHY_RC_CONFIG0", 0x4f400, 0 },
|
|
{ "GLOBAL_PHY_OFFSET", 12, 4 },
|
|
{ "ADVANCE_RD_VALID", 11, 1 },
|
|
{ "SINGLE_BIT_MPR_RP0", 6, 1 },
|
|
{ "SINGLE_BIT_MPR_RP1", 5, 1 },
|
|
{ "SINGLE_BIT_MPR_RP2", 4, 1 },
|
|
{ "SINGLE_BIT_MPR_RP3", 3, 1 },
|
|
{ "ALIGN_ON_EVEN_CYCLES", 2, 1 },
|
|
{ "PERFORM_RDCLK_ALIGN", 1, 1 },
|
|
{ "STAGGERED_PATTERN", 0, 1 },
|
|
{ "MC_DDRPHY_RC_CONFIG1", 0x4f404, 0 },
|
|
{ "OUTER_LOOP_CNT", 2, 14 },
|
|
{ "MC_DDRPHY_RC_CONFIG2", 0x4f408, 0 },
|
|
{ "CONSEQ_PASS", 11, 5 },
|
|
{ "BURST_WINDOW", 5, 2 },
|
|
{ "ALLOW_RD_FIFO_AUTO_R_ESET", 4, 1 },
|
|
{ "MC_DDRPHY_RC_CONFIG3", 0x4f41c, 0 },
|
|
{ "FINE_CAL_STEP_SIZE", 13, 3 },
|
|
{ "COARSE_CAL_STEP_SIZE", 9, 4 },
|
|
{ "DQ_SEL_QUAD", 7, 2 },
|
|
{ "DQ_SEL_LANE", 4, 3 },
|
|
{ "MC_DDRPHY_RC_PERIODIC", 0x4f420, 0 },
|
|
{ "MC_DDRPHY_RC_ERROR_STATUS0", 0x4f414, 0 },
|
|
{ "RD_CNTL_ERROR", 15, 1 },
|
|
{ "MC_DDRPHY_RC_ERROR_MASK0", 0x4f418, 0 },
|
|
{ "RD_CNTL_ERROR_MASK", 15, 1 },
|
|
{ "MC_DDRPHY_APB_CONFIG0", 0x4f800, 0 },
|
|
{ "DISABLE_PARITY_CHECKER", 15, 1 },
|
|
{ "GENERATE_EVEN_PARITY", 14, 1 },
|
|
{ "FORCE_ON_CLK_GATE", 13, 1 },
|
|
{ "DEBUG_BUS_SEL_LO", 12, 1 },
|
|
{ "DEBUG_BUS_SEL_HI", 8, 4 },
|
|
{ "MC_DDRPHY_APB_ERROR_STATUS0", 0x4f804, 0 },
|
|
{ "INVALID_ADDRESS", 15, 1 },
|
|
{ "WR_PAR_ERR", 14, 1 },
|
|
{ "MC_DDRPHY_APB_ERROR_MASK0", 0x4f808, 0 },
|
|
{ "INVALID_ADDRESS_MASK", 15, 1 },
|
|
{ "WR_PAR_ERR_MASK", 14, 1 },
|
|
{ "MC_DDRPHY_APB_DP18_POPULATION", 0x4f80c, 0 },
|
|
{ "DP18_0_Populated", 15, 1 },
|
|
{ "DP18_1_Populated", 14, 1 },
|
|
{ "DP18_2_Populated", 13, 1 },
|
|
{ "DP18_3_Populated", 12, 1 },
|
|
{ "DP18_4_Populated", 11, 1 },
|
|
{ "DP18_5_Populated", 10, 1 },
|
|
{ "DP18_6_Populated", 9, 1 },
|
|
{ "DP18_7_Populated", 8, 1 },
|
|
{ "DP18_8_Populated", 7, 1 },
|
|
{ "DP18_9_Populated", 6, 1 },
|
|
{ "DP18_10_Populated", 5, 1 },
|
|
{ "DP18_11_Populated", 4, 1 },
|
|
{ "DP18_12_Populated", 3, 1 },
|
|
{ "DP18_13_Populated", 2, 1 },
|
|
{ "DP18_14_Populated", 1, 1 },
|
|
{ "MC_DDRPHY_APB_ADR_POPULATION", 0x4f810, 0 },
|
|
{ "ADR16_0_Populated", 15, 1 },
|
|
{ "ADR16_1_Populated", 14, 1 },
|
|
{ "ADR16_2_Populated", 13, 1 },
|
|
{ "ADR16_3_Populated", 12, 1 },
|
|
{ "ADR12_0_Populated", 7, 1 },
|
|
{ "ADR12_1_Populated", 6, 1 },
|
|
{ "ADR12_2_Populated", 5, 1 },
|
|
{ "ADR12_3_Populated", 4, 1 },
|
|
{ "MC_DDRPHY_APB_ATEST_MUX_SEL", 0x4f814, 0 },
|
|
{ "ATEST_CNTL", 10, 6 },
|
|
{ "MC_UPCTL_SCFG", 0x48000, 0 },
|
|
{ "bbflags_timing", 8, 4 },
|
|
{ "nfifo_nif1_dis", 6, 1 },
|
|
{ "hw_low_power_en", 0, 1 },
|
|
{ "MC_UPCTL_SCTL", 0x48004, 0 },
|
|
{ "MC_UPCTL_STAT", 0x48008, 0 },
|
|
{ "lp_trig", 4, 3 },
|
|
{ "ctl_stat", 0, 3 },
|
|
{ "MC_UPCTL_INTRSTAT", 0x4800c, 0 },
|
|
{ "parity_intr", 1, 1 },
|
|
{ "ecc_intr", 0, 1 },
|
|
{ "MC_UPCTL_MCMD", 0x48040, 0 },
|
|
{ "start_cmd", 31, 1 },
|
|
{ "cmd_add_del", 24, 4 },
|
|
{ "rank_sel", 20, 4 },
|
|
{ "bank_addr", 17, 3 },
|
|
{ "cmd_addr", 4, 13 },
|
|
{ "cmd_opcode0", 0, 4 },
|
|
{ "MC_UPCTL_POWCTL", 0x48044, 0 },
|
|
{ "MC_UPCTL_POWSTAT", 0x48048, 0 },
|
|
{ "MC_UPCTL_CMDTSTAT", 0x4804c, 0 },
|
|
{ "MC_UPCTL_CMDTSTATEN", 0x48050, 0 },
|
|
{ "MC_UPCTL_MRRCFG0", 0x48060, 0 },
|
|
{ "MC_UPCTL_MRRSTAT0", 0x48064, 0 },
|
|
{ "mrrstat_beat3", 24, 8 },
|
|
{ "mrrstat_beat2", 16, 8 },
|
|
{ "mrrstat_beat1", 8, 8 },
|
|
{ "mrrstat_beat0", 0, 8 },
|
|
{ "MC_UPCTL_MRRSTAT1", 0x48068, 0 },
|
|
{ "mrrstat_beat7", 24, 8 },
|
|
{ "mrrstat_beat6", 16, 8 },
|
|
{ "mrrstat_beat5", 8, 8 },
|
|
{ "mrrstat_beat4", 0, 8 },
|
|
{ "MC_UPCTL_MCFG1", 0x4807c, 0 },
|
|
{ "hw_exit_idle_en", 31, 1 },
|
|
{ "hw_idle", 16, 8 },
|
|
{ "sr_idle", 0, 8 },
|
|
{ "MC_UPCTL_MCFG", 0x48080, 0 },
|
|
{ "mddr_lpddr2_clk_stop_idle", 24, 8 },
|
|
{ "mddr_lpddr2_en", 22, 2 },
|
|
{ "mddr_lpddr2_bl", 20, 2 },
|
|
{ "tfaw_cfg", 18, 2 },
|
|
{ "pd_exit_mode", 17, 1 },
|
|
{ "pd_type", 16, 1 },
|
|
{ "pd_idle", 8, 8 },
|
|
{ "lpddr2_s4", 6, 1 },
|
|
{ "ddr3_en", 5, 1 },
|
|
{ "stagger_cs", 4, 1 },
|
|
{ "two_t_en", 3, 1 },
|
|
{ "bl8int_en", 2, 1 },
|
|
{ "cke_or_en", 1, 1 },
|
|
{ "mem_bl", 0, 1 },
|
|
{ "MC_UPCTL_PPCFG", 0x48084, 0 },
|
|
{ "rpmem_dis", 1, 8 },
|
|
{ "ppmem_en", 0, 1 },
|
|
{ "MC_UPCTL_MSTAT", 0x48088, 0 },
|
|
{ "self_refresh", 2, 1 },
|
|
{ "clock_stop", 1, 1 },
|
|
{ "power_down", 0, 1 },
|
|
{ "MC_UPCTL_LPDDR2ZQCFG", 0x4808c, 0 },
|
|
{ "zqcl_op", 24, 8 },
|
|
{ "zqcl_ma", 16, 8 },
|
|
{ "zqcs_op", 8, 8 },
|
|
{ "zqcs_ma", 0, 8 },
|
|
{ "MC_UPCTL_DTUPDES", 0x48094, 0 },
|
|
{ "dtu_rd_missing", 13, 1 },
|
|
{ "dtu_eaffl", 9, 4 },
|
|
{ "dtu_random_error", 8, 1 },
|
|
{ "dtu_err_b7", 7, 1 },
|
|
{ "dtu_err_b6", 6, 1 },
|
|
{ "dtu_err_b5", 5, 1 },
|
|
{ "dtu_err_b4", 4, 1 },
|
|
{ "dtu_err_b3", 3, 1 },
|
|
{ "dtu_err_b2", 2, 1 },
|
|
{ "dtu_err_b1", 1, 1 },
|
|
{ "dtu_err_b0", 0, 1 },
|
|
{ "MC_UPCTL_DTUNA", 0x48098, 0 },
|
|
{ "MC_UPCTL_DTUNE", 0x4809c, 0 },
|
|
{ "MC_UPCTL_DTUPRD0", 0x480a0, 0 },
|
|
{ "dtu_allbits_1", 16, 16 },
|
|
{ "dtu_allbits_0", 0, 16 },
|
|
{ "MC_UPCTL_DTUPRD1", 0x480a4, 0 },
|
|
{ "dtu_allbits_3", 16, 16 },
|
|
{ "dtu_allbits_2", 0, 16 },
|
|
{ "MC_UPCTL_DTUPRD2", 0x480a8, 0 },
|
|
{ "dtu_allbits_5", 16, 16 },
|
|
{ "dtu_allbits_4", 0, 16 },
|
|
{ "MC_UPCTL_DTUPRD3", 0x480ac, 0 },
|
|
{ "dtu_allbits_7", 16, 16 },
|
|
{ "dtu_allbits_6", 0, 16 },
|
|
{ "MC_UPCTL_DTUAWDT", 0x480b0, 0 },
|
|
{ "number_ranks", 9, 2 },
|
|
{ "row_addr_width", 6, 2 },
|
|
{ "bank_addr_width", 3, 2 },
|
|
{ "column_addr_width", 0, 2 },
|
|
{ "MC_UPCTL_TOGCNT1U", 0x480c0, 0 },
|
|
{ "MC_UPCTL_TINIT", 0x480c4, 0 },
|
|
{ "MC_UPCTL_TRSTH", 0x480c8, 0 },
|
|
{ "MC_UPCTL_TOGCNT100N", 0x480cc, 0 },
|
|
{ "MC_UPCTL_TREFI", 0x480d0, 0 },
|
|
{ "MC_UPCTL_TMRD", 0x480d4, 0 },
|
|
{ "MC_UPCTL_TRFC", 0x480d8, 0 },
|
|
{ "MC_UPCTL_TRP", 0x480dc, 0 },
|
|
{ "prea_extra", 16, 2 },
|
|
{ "t_rp", 0, 4 },
|
|
{ "MC_UPCTL_TRTW", 0x480e0, 0 },
|
|
{ "MC_UPCTL_TAL", 0x480e4, 0 },
|
|
{ "MC_UPCTL_TCL", 0x480e8, 0 },
|
|
{ "MC_UPCTL_TCWL", 0x480ec, 0 },
|
|
{ "MC_UPCTL_TRAS", 0x480f0, 0 },
|
|
{ "MC_UPCTL_TRC", 0x480f4, 0 },
|
|
{ "MC_UPCTL_TRCD", 0x480f8, 0 },
|
|
{ "MC_UPCTL_TRRD", 0x480fc, 0 },
|
|
{ "MC_UPCTL_TRTP", 0x48100, 0 },
|
|
{ "MC_UPCTL_TWR", 0x48104, 0 },
|
|
{ "MC_UPCTL_TWTR", 0x48108, 0 },
|
|
{ "MC_UPCTL_TEXSR", 0x4810c, 0 },
|
|
{ "MC_UPCTL_TXP", 0x48110, 0 },
|
|
{ "MC_UPCTL_TXPDLL", 0x48114, 0 },
|
|
{ "MC_UPCTL_TZQCS", 0x48118, 0 },
|
|
{ "MC_UPCTL_TZQCSI", 0x4811c, 0 },
|
|
{ "MC_UPCTL_TDQS", 0x48120, 0 },
|
|
{ "MC_UPCTL_TCKSRE", 0x48124, 0 },
|
|
{ "MC_UPCTL_TCKSRX", 0x48128, 0 },
|
|
{ "MC_UPCTL_TCKE", 0x4812c, 0 },
|
|
{ "MC_UPCTL_TMOD", 0x48130, 0 },
|
|
{ "MC_UPCTL_TRSTL", 0x48134, 0 },
|
|
{ "MC_UPCTL_TZQCL", 0x48138, 0 },
|
|
{ "MC_UPCTL_TMRR", 0x4813c, 0 },
|
|
{ "MC_UPCTL_TCKESR", 0x48140, 0 },
|
|
{ "MC_UPCTL_TDPD", 0x48144, 0 },
|
|
{ "MC_UPCTL_ECCCFG", 0x48180, 0 },
|
|
{ "inline_syn_en", 4, 1 },
|
|
{ "ecc_en", 3, 1 },
|
|
{ "ecc_intr_en", 2, 1 },
|
|
{ "MC_UPCTL_ECCTST", 0x48184, 0 },
|
|
{ "MC_UPCTL_ECCCLR", 0x48188, 0 },
|
|
{ "clr_ecc_log", 1, 1 },
|
|
{ "clr_ecc_intr", 0, 1 },
|
|
{ "MC_UPCTL_ECCLOG", 0x4818c, 0 },
|
|
{ "MC_UPCTL_DTUWACTL", 0x48200, 0 },
|
|
{ "dtu_wr_rank", 30, 2 },
|
|
{ "dtu_wr_row0", 13, 16 },
|
|
{ "dtu_wr_bank", 10, 3 },
|
|
{ "dtu_wr_col", 0, 10 },
|
|
{ "MC_UPCTL_DTURACTL", 0x48204, 0 },
|
|
{ "dtu_rd_rank", 30, 2 },
|
|
{ "dtu_rd_row0", 13, 16 },
|
|
{ "dtu_rd_bank", 10, 3 },
|
|
{ "dtu_rd_col", 0, 10 },
|
|
{ "MC_UPCTL_DTUCFG", 0x48208, 0 },
|
|
{ "dtu_row_increments", 16, 7 },
|
|
{ "dtu_wr_multi_rd", 15, 1 },
|
|
{ "dtu_data_mask_en", 14, 1 },
|
|
{ "dtu_target_lane", 10, 4 },
|
|
{ "dtu_generate_random", 9, 1 },
|
|
{ "dtu_incr_banks", 8, 1 },
|
|
{ "dtu_incr_cols", 7, 1 },
|
|
{ "dtu_nalen", 1, 6 },
|
|
{ "dtu_enable", 0, 1 },
|
|
{ "MC_UPCTL_DTUECTL", 0x4820c, 0 },
|
|
{ "wr_multi_rd_rst", 2, 1 },
|
|
{ "run_error_reports", 1, 1 },
|
|
{ "run_dtu", 0, 1 },
|
|
{ "MC_UPCTL_DTUWD0", 0x48210, 0 },
|
|
{ "dtu_wr_byte3", 24, 8 },
|
|
{ "dtu_wr_byte2", 16, 8 },
|
|
{ "dtu_wr_byte1", 8, 8 },
|
|
{ "dtu_wr_byte0", 0, 8 },
|
|
{ "MC_UPCTL_DTUWD1", 0x48214, 0 },
|
|
{ "dtu_wr_byte7", 24, 8 },
|
|
{ "dtu_wr_byte6", 16, 8 },
|
|
{ "dtu_wr_byte5", 8, 8 },
|
|
{ "dtu_wr_byte4", 0, 8 },
|
|
{ "MC_UPCTL_DTUWD2", 0x48218, 0 },
|
|
{ "dtu_wr_byte11", 24, 8 },
|
|
{ "dtu_wr_byte10", 16, 8 },
|
|
{ "dtu_wr_byte9", 8, 8 },
|
|
{ "dtu_wr_byte8", 0, 8 },
|
|
{ "MC_UPCTL_DTUWD3", 0x4821c, 0 },
|
|
{ "dtu_wr_byte15", 24, 8 },
|
|
{ "dtu_wr_byte14", 16, 8 },
|
|
{ "dtu_wr_byte13", 8, 8 },
|
|
{ "dtu_wr_byte12", 0, 8 },
|
|
{ "MC_UPCTL_DTUWDM", 0x48220, 0 },
|
|
{ "MC_UPCTL_DTURD0", 0x48224, 0 },
|
|
{ "dtu_rd_byte3", 24, 8 },
|
|
{ "dtu_rd_byte2", 16, 8 },
|
|
{ "dtu_rd_byte1", 8, 8 },
|
|
{ "dtu_rd_byte0", 0, 8 },
|
|
{ "MC_UPCTL_DTURD1", 0x48228, 0 },
|
|
{ "dtu_rd_byte7", 24, 8 },
|
|
{ "dtu_rd_byte6", 16, 8 },
|
|
{ "dtu_rd_byte5", 8, 8 },
|
|
{ "dtu_rd_byte4", 0, 8 },
|
|
{ "MC_UPCTL_DTURD2", 0x4822c, 0 },
|
|
{ "dtu_rd_byte11", 24, 8 },
|
|
{ "dtu_rd_byte10", 16, 8 },
|
|
{ "dtu_rd_byte9", 8, 8 },
|
|
{ "dtu_rd_byte8", 0, 8 },
|
|
{ "MC_UPCTL_DTURD3", 0x48230, 0 },
|
|
{ "dtu_rd_byte15", 24, 8 },
|
|
{ "dtu_rd_byte14", 16, 8 },
|
|
{ "dtu_rd_byte13", 8, 8 },
|
|
{ "dtu_rd_byte12", 0, 8 },
|
|
{ "MC_UPCTL_DTULFSRWD", 0x48234, 0 },
|
|
{ "MC_UPCTL_DTULFSRRD", 0x48238, 0 },
|
|
{ "MC_UPCTL_DTUEAF", 0x4823c, 0 },
|
|
{ "ea_rank", 30, 2 },
|
|
{ "ea_row0", 13, 16 },
|
|
{ "ea_bank", 10, 3 },
|
|
{ "ea_column", 0, 10 },
|
|
{ "MC_UPCTL_DFITCTRLDELAY", 0x48240, 0 },
|
|
{ "MC_UPCTL_DFIODTCFG", 0x48244, 0 },
|
|
{ "rank3_odt_default", 28, 1 },
|
|
{ "rank3_odt_write_sel", 27, 1 },
|
|
{ "rank3_odt_write_nsel", 26, 1 },
|
|
{ "rank3_odt_read_sel", 25, 1 },
|
|
{ "rank3_odt_read_nsel", 24, 1 },
|
|
{ "rank2_odt_default", 20, 1 },
|
|
{ "rank2_odt_write_sel", 19, 1 },
|
|
{ "rank2_odt_write_nsel", 18, 1 },
|
|
{ "rank2_odt_read_sel", 17, 1 },
|
|
{ "rank2_odt_read_nsel", 16, 1 },
|
|
{ "rank1_odt_default", 12, 1 },
|
|
{ "rank1_odt_write_sel", 11, 1 },
|
|
{ "rank1_odt_write_nsel", 10, 1 },
|
|
{ "rank1_odt_read_sel", 9, 1 },
|
|
{ "rank1_odt_read_nsel", 8, 1 },
|
|
{ "rank0_odt_default", 4, 1 },
|
|
{ "rank0_odt_write_sel", 3, 1 },
|
|
{ "rank0_odt_write_nsel", 2, 1 },
|
|
{ "rank0_odt_read_sel", 1, 1 },
|
|
{ "rank0_odt_read_nsel", 0, 1 },
|
|
{ "MC_UPCTL_DFIODTCFG1", 0x48248, 0 },
|
|
{ "odt_len_b8_r", 24, 3 },
|
|
{ "odt_len_bl8_w", 16, 3 },
|
|
{ "odt_lat_r", 8, 5 },
|
|
{ "odt_lat_w", 0, 5 },
|
|
{ "MC_UPCTL_DFIODTRANKMAP", 0x4824c, 0 },
|
|
{ "odt_rank_map3", 12, 4 },
|
|
{ "odt_rank_map2", 8, 4 },
|
|
{ "odt_rank_map1", 4, 4 },
|
|
{ "odt_rank_map0", 0, 4 },
|
|
{ "MC_UPCTL_DFITPHYWRDATA", 0x48250, 0 },
|
|
{ "MC_UPCTL_DFITPHYWRLAT", 0x48254, 0 },
|
|
{ "MC_UPCTL_DFITRDDATAEN", 0x48260, 0 },
|
|
{ "MC_UPCTL_DFITPHYRDLAT", 0x48264, 0 },
|
|
{ "MC_UPCTL_DFITPHYUPDTYPE0", 0x48270, 0 },
|
|
{ "MC_UPCTL_DFITPHYUPDTYPE1", 0x48274, 0 },
|
|
{ "MC_UPCTL_DFITPHYUPDTYPE2", 0x48278, 0 },
|
|
{ "MC_UPCTL_DFITPHYUPDTYPE3", 0x4827c, 0 },
|
|
{ "MC_UPCTL_DFITCTRLUPDMIN", 0x48280, 0 },
|
|
{ "MC_UPCTL_DFITCTRLUPDMAX", 0x48284, 0 },
|
|
{ "MC_UPCTL_DFITCTRLUPDDLY", 0x48288, 0 },
|
|
{ "MC_UPCTL_DFIUPDCFG", 0x48290, 0 },
|
|
{ "dfi_phyupd_en", 1, 1 },
|
|
{ "dfi_ctrlupd_en", 0, 1 },
|
|
{ "MC_UPCTL_DFITREFMSKI", 0x48294, 0 },
|
|
{ "MC_UPCTL_DFITCTRLUPDI", 0x48298, 0 },
|
|
{ "MC_UPCTL_DFITRCFG0", 0x482ac, 0 },
|
|
{ "dfi_wrlvl_rank_sel", 16, 4 },
|
|
{ "dfi_rdlvl_edge", 4, 9 },
|
|
{ "dfi_rdlvl_rank_sel", 0, 4 },
|
|
{ "MC_UPCTL_DFITRSTAT0", 0x482b0, 0 },
|
|
{ "dfi_wrlvl_mode", 16, 2 },
|
|
{ "dfi_rdlvl_gate_mode", 8, 2 },
|
|
{ "dfi_rdlvl_mode", 0, 2 },
|
|
{ "MC_UPCTL_DFITRWRLVLEN", 0x482b4, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLEN", 0x482b8, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLGATEEN", 0x482bc, 0 },
|
|
{ "MC_UPCTL_DFISTSTAT0", 0x482c0, 0 },
|
|
{ "dfi_data_byte_disable", 16, 9 },
|
|
{ "dfi_freq_ratio", 4, 2 },
|
|
{ "dfi_init_start0", 1, 1 },
|
|
{ "dfi_init_complete", 0, 1 },
|
|
{ "MC_UPCTL_DFISTCFG0", 0x482c4, 0 },
|
|
{ "dfi_data_byte_disable_en", 2, 1 },
|
|
{ "dfi_freq_ratio_en", 1, 1 },
|
|
{ "dfi_init_start", 0, 1 },
|
|
{ "MC_UPCTL_DFISTCFG1", 0x482c8, 0 },
|
|
{ "dfi_dram_clk_disable_en_dpd", 1, 1 },
|
|
{ "dfi_dram_clk_disable_en", 0, 1 },
|
|
{ "MC_UPCTL_DFITDRAMCLKEN", 0x482d0, 0 },
|
|
{ "MC_UPCTL_DFITDRAMCLKDIS", 0x482d4, 0 },
|
|
{ "MC_UPCTL_DFISTCFG2", 0x482d8, 0 },
|
|
{ "parity_en", 1, 1 },
|
|
{ "parity_intr_en", 0, 1 },
|
|
{ "MC_UPCTL_DFISTPARCLR", 0x482dc, 0 },
|
|
{ "parity_log_clr", 1, 1 },
|
|
{ "parity_intr_clr", 0, 1 },
|
|
{ "MC_UPCTL_DFISTPARLOG", 0x482e0, 0 },
|
|
{ "MC_UPCTL_DFILPCFG0", 0x482f0, 0 },
|
|
{ "dfi_lp_wakeup_dpd", 28, 4 },
|
|
{ "dfi_lp_en_dpd", 24, 1 },
|
|
{ "dfi_tlp_resp", 16, 4 },
|
|
{ "dfi_lp_en_sr", 8, 1 },
|
|
{ "dfi_lp_wakeup_pd", 4, 4 },
|
|
{ "dfi_lp_en_pd", 0, 1 },
|
|
{ "MC_UPCTL_DFITRWRLVLRESP0", 0x48300, 0 },
|
|
{ "MC_UPCTL_DFITRWRLVLRESP1", 0x48304, 0 },
|
|
{ "MC_UPCTL_DFITRWRLVLRESP2", 0x48308, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLRESP0", 0x4830c, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLRESP1", 0x48310, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLRESP2", 0x48314, 0 },
|
|
{ "MC_UPCTL_DFITRWRLVLDELAY0", 0x48318, 0 },
|
|
{ "MC_UPCTL_DFITRWRLVLDELAY1", 0x4831c, 0 },
|
|
{ "MC_UPCTL_DFITRWRLVLDELAY2", 0x48320, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLDELAY0", 0x48324, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLDELAY1", 0x48328, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLDELAY2", 0x4832c, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLGATEDELAY0", 0x48330, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLGATEDELAY1", 0x48334, 0 },
|
|
{ "MC_UPCTL_DFITRRDLVLGATEDELAY2", 0x48338, 0 },
|
|
{ "MC_UPCTL_DFITRCMD", 0x4833c, 0 },
|
|
{ "dfitrcmd_start", 31, 1 },
|
|
{ "dfitrcmd_en", 4, 9 },
|
|
{ "dfitrcmd_opcode", 0, 2 },
|
|
{ "MC_UPCTL_IPVR", 0x483f8, 0 },
|
|
{ "MC_UPCTL_IPTR", 0x483fc, 0 },
|
|
{ "MC_P_DDRPHY_RST_CTRL", 0x49300, 0 },
|
|
{ "PHY_DRAM_WL", 17, 5 },
|
|
{ "PHY_CALIB_DONE", 5, 1 },
|
|
{ "CTL_CAL_REQ", 4, 1 },
|
|
{ "CTL_CKE", 3, 1 },
|
|
{ "CTL_RST_N", 2, 1 },
|
|
{ "DDRIO_ENABLE", 1, 1 },
|
|
{ "PHY_RST_N", 0, 1 },
|
|
{ "MC_P_PERFORMANCE_CTRL", 0x49304, 0 },
|
|
{ "STALL_CHK_BIT", 2, 1 },
|
|
{ "DDR3_BRC_MODE", 1, 1 },
|
|
{ "RMW_PERF_CTRL", 0, 1 },
|
|
{ "MC_P_ECC_CTRL", 0x49308, 0 },
|
|
{ "ECC_BYPASS_BIST", 1, 1 },
|
|
{ "ECC_DISABLE", 0, 1 },
|
|
{ "MC_P_PAR_ENABLE", 0x4930c, 0 },
|
|
{ "ECC_UE_PAR_ENABLE", 3, 1 },
|
|
{ "ECC_CE_PAR_ENABLE", 2, 1 },
|
|
{ "PERR_REG_INT_ENABLE", 1, 1 },
|
|
{ "PERR_BLK_INT_ENABLE", 0, 1 },
|
|
{ "MC_P_PAR_CAUSE", 0x49310, 0 },
|
|
{ "ECC_UE_PAR_CAUSE", 3, 1 },
|
|
{ "ECC_CE_PAR_CAUSE", 2, 1 },
|
|
{ "FIFOR_PAR_CAUSE", 1, 1 },
|
|
{ "RDATA_FIFOR_PAR_CAUSE", 0, 1 },
|
|
{ "MC_P_INT_ENABLE", 0x49314, 0 },
|
|
{ "ECC_UE_INT_ENABLE", 2, 1 },
|
|
{ "ECC_CE_INT_ENABLE", 1, 1 },
|
|
{ "PERR_INT_ENABLE", 0, 1 },
|
|
{ "MC_P_INT_CAUSE", 0x49318, 0 },
|
|
{ "ECC_UE_INT_CAUSE", 2, 1 },
|
|
{ "ECC_CE_INT_CAUSE", 1, 1 },
|
|
{ "PERR_INT_CAUSE", 0, 1 },
|
|
{ "MC_P_ECC_STATUS", 0x4931c, 0 },
|
|
{ "ECC_CECNT", 16, 16 },
|
|
{ "ECC_UECNT", 0, 16 },
|
|
{ "MC_P_PHY_CTRL", 0x49320, 0 },
|
|
{ "MC_P_STATIC_CFG_STATUS", 0x49324, 0 },
|
|
{ "STATIC_AWEN", 23, 1 },
|
|
{ "STATIC_SWLAT", 18, 5 },
|
|
{ "STATIC_WLAT", 17, 1 },
|
|
{ "STATIC_ALIGN", 16, 1 },
|
|
{ "STATIC_SLAT", 11, 5 },
|
|
{ "STATIC_LAT", 10, 1 },
|
|
{ "STATIC_MODE", 9, 1 },
|
|
{ "STATIC_DEN", 6, 3 },
|
|
{ "STATIC_ORG", 5, 1 },
|
|
{ "STATIC_RKS", 4, 1 },
|
|
{ "STATIC_WIDTH", 1, 3 },
|
|
{ "STATIC_SLOW", 0, 1 },
|
|
{ "MC_P_CORE_PCTL_STAT", 0x49328, 0 },
|
|
{ "MC_P_DEBUG_CNT", 0x4932c, 0 },
|
|
{ "WDATA_OCNT", 8, 5 },
|
|
{ "RDATA_OCNT", 0, 5 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x49330, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x49334, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x49338, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x4933c, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x49340, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x49344, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x49348, 0 },
|
|
{ "MC_CE_ERR_DATA_RDATA", 0x4934c, 0 },
|
|
{ "MC_CE_COR_DATA_RDATA", 0x49350, 0 },
|
|
{ "MC_CE_COR_DATA_RDATA", 0x49354, 0 },
|
|
{ "MC_CE_COR_DATA_RDATA", 0x49358, 0 },
|
|
{ "MC_CE_COR_DATA_RDATA", 0x4935c, 0 },
|
|
{ "MC_CE_COR_DATA_RDATA", 0x49360, 0 },
|
|
{ "MC_CE_COR_DATA_RDATA", 0x49364, 0 },
|
|
{ "MC_CE_COR_DATA_RDATA", 0x49368, 0 },
|
|
{ "MC_CE_COR_DATA_RDATA", 0x4936c, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x49370, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x49374, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x49378, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x4937c, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x49380, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x49384, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x49388, 0 },
|
|
{ "MC_UE_ERR_DATA_RDATA", 0x4938c, 0 },
|
|
{ "MC_UE_COR_DATA_RDATA", 0x49390, 0 },
|
|
{ "MC_UE_COR_DATA_RDATA", 0x49394, 0 },
|
|
{ "MC_UE_COR_DATA_RDATA", 0x49398, 0 },
|
|
{ "MC_UE_COR_DATA_RDATA", 0x4939c, 0 },
|
|
{ "MC_UE_COR_DATA_RDATA", 0x493a0, 0 },
|
|
{ "MC_UE_COR_DATA_RDATA", 0x493a4, 0 },
|
|
{ "MC_UE_COR_DATA_RDATA", 0x493a8, 0 },
|
|
{ "MC_UE_COR_DATA_RDATA", 0x493ac, 0 },
|
|
{ "MC_CE_ADDR", 0x493b0, 0 },
|
|
{ "MC_UE_ADDR", 0x493b4, 0 },
|
|
{ "MC_P_DEEP_SLEEP", 0x493b8, 0 },
|
|
{ "SleepStatus", 1, 1 },
|
|
{ "SleepReq", 0, 1 },
|
|
{ "MC_P_FPGA_BONUS", 0x493bc, 0 },
|
|
{ "MC_P_DEBUG_CFG", 0x493c0, 0 },
|
|
{ "DEBUG_OR", 15, 1 },
|
|
{ "DEBUG_HI", 14, 1 },
|
|
{ "DEBUG_RPT", 13, 1 },
|
|
{ "DEBUGPAGE", 10, 3 },
|
|
{ "DEBUGSELH", 5, 5 },
|
|
{ "DEBUGSELL", 0, 5 },
|
|
{ "MC_P_DEBUG_RPT", 0x493c4, 0 },
|
|
{ "MC_P_BIST_CMD", 0x49400, 0 },
|
|
{ "START_BIST", 31, 1 },
|
|
{ "BURST_LEN", 16, 2 },
|
|
{ "BIST_CMD_GAP", 8, 8 },
|
|
{ "BIST_OPCODE", 0, 2 },
|
|
{ "MC_P_BIST_CMD_ADDR", 0x49404, 0 },
|
|
{ "MC_P_BIST_CMD_LEN", 0x49408, 0 },
|
|
{ "MC_P_BIST_DATA_PATTERN", 0x4940c, 0 },
|
|
{ "MC_P_BIST_USER_WDATA0", 0x49414, 0 },
|
|
{ "MC_P_BIST_USER_WDATA1", 0x49418, 0 },
|
|
{ "MC_P_BIST_USER_WDATA2", 0x4941c, 0 },
|
|
{ "USER_DATA_MASK", 8, 9 },
|
|
{ "USER_DATA2", 0, 8 },
|
|
{ "MC_P_BIST_NUM_ERR", 0x49480, 0 },
|
|
{ "MC_P_BIST_ERR_FIRST_ADDR", 0x49484, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x49488, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x4948c, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x49490, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x49494, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x49498, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x4949c, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x494a0, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x494a4, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x494a8, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x494ac, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x494b0, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x494b4, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x494b8, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x494bc, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x494c0, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x494c4, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x494c8, 0 },
|
|
{ "MC_P_BIST_STATUS_RDATA", 0x494cc, 0 },
|
|
{ "MC_P_BIST_CRC_SEED", 0x494d0, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_edc_t50_regs[] = {
|
|
{ "EDC_H_REF", 0x50000, 0 },
|
|
{ "SleepStatus", 31, 1 },
|
|
{ "SleepReq", 30, 1 },
|
|
{ "PING_PONG", 29, 1 },
|
|
{ "EDC_INST_NUM", 18, 1 },
|
|
{ "ENABLE_PERF", 17, 1 },
|
|
{ "ECC_BYPASS", 16, 1 },
|
|
{ "RefFreq", 0, 16 },
|
|
{ "EDC_H_BIST_CMD", 0x50004, 0 },
|
|
{ "START_BIST", 31, 1 },
|
|
{ "BURST_LEN", 16, 2 },
|
|
{ "BIST_CMD_GAP", 8, 8 },
|
|
{ "BIST_OPCODE", 0, 2 },
|
|
{ "EDC_H_BIST_CMD_ADDR", 0x50008, 0 },
|
|
{ "EDC_H_BIST_CMD_LEN", 0x5000c, 0 },
|
|
{ "EDC_H_BIST_DATA_PATTERN", 0x50010, 0 },
|
|
{ "EDC_H_BIST_USER_WDATA0", 0x50014, 0 },
|
|
{ "EDC_H_BIST_USER_WDATA1", 0x50018, 0 },
|
|
{ "EDC_H_BIST_USER_WDATA2", 0x5001c, 0 },
|
|
{ "USER_DATA_MASK", 8, 9 },
|
|
{ "USER_DATA2", 0, 8 },
|
|
{ "EDC_H_BIST_NUM_ERR", 0x50020, 0 },
|
|
{ "EDC_H_BIST_ERR_FIRST_ADDR", 0x50024, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50028, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5002c, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50030, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50034, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50038, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5003c, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50040, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50044, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50048, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5004c, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50050, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50054, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50058, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5005c, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50060, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50064, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50068, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5006c, 0 },
|
|
{ "EDC_H_PAR_ENABLE", 0x50070, 0 },
|
|
{ "ECC_UE_PAR_ENABLE", 2, 1 },
|
|
{ "ECC_CE_PAR_ENABLE", 1, 1 },
|
|
{ "PERR_PAR_ENABLE", 0, 1 },
|
|
{ "EDC_H_INT_ENABLE", 0x50074, 0 },
|
|
{ "ECC_UE_INT_ENABLE", 2, 1 },
|
|
{ "ECC_CE_INT_ENABLE", 1, 1 },
|
|
{ "PERR_INT_ENABLE", 0, 1 },
|
|
{ "EDC_H_INT_CAUSE", 0x50078, 0 },
|
|
{ "ECC_UE_INT0_CAUSE", 5, 1 },
|
|
{ "ECC_CE_INT0_CAUSE", 4, 1 },
|
|
{ "PERR_INT0_CAUSE", 3, 1 },
|
|
{ "ECC_UE_INT_CAUSE", 2, 1 },
|
|
{ "ECC_CE_INT_CAUSE", 1, 1 },
|
|
{ "PERR_INT_CAUSE", 0, 1 },
|
|
{ "EDC_H_ECC_STATUS", 0x5007c, 0 },
|
|
{ "ECC_CECNT", 16, 16 },
|
|
{ "ECC_UECNT", 0, 16 },
|
|
{ "EDC_H_ECC_ERR_SEL", 0x50080, 0 },
|
|
{ "EDC_H_ECC_ERR_ADDR", 0x50084, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50090, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50094, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50098, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x5009c, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500a0, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500a4, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500a8, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500ac, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500b0, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500b4, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500b8, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500bc, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500c0, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500c4, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500c8, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x500cc, 0 },
|
|
{ "EDC_H_BIST_CRC_SEED", 0x50400, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_edc_t51_regs[] = {
|
|
{ "EDC_H_REF", 0x50800, 0 },
|
|
{ "SleepStatus", 31, 1 },
|
|
{ "SleepReq", 30, 1 },
|
|
{ "PING_PONG", 29, 1 },
|
|
{ "EDC_INST_NUM", 18, 1 },
|
|
{ "ENABLE_PERF", 17, 1 },
|
|
{ "ECC_BYPASS", 16, 1 },
|
|
{ "RefFreq", 0, 16 },
|
|
{ "EDC_H_BIST_CMD", 0x50804, 0 },
|
|
{ "START_BIST", 31, 1 },
|
|
{ "BURST_LEN", 16, 2 },
|
|
{ "BIST_CMD_GAP", 8, 8 },
|
|
{ "BIST_OPCODE", 0, 2 },
|
|
{ "EDC_H_BIST_CMD_ADDR", 0x50808, 0 },
|
|
{ "EDC_H_BIST_CMD_LEN", 0x5080c, 0 },
|
|
{ "EDC_H_BIST_DATA_PATTERN", 0x50810, 0 },
|
|
{ "EDC_H_BIST_USER_WDATA0", 0x50814, 0 },
|
|
{ "EDC_H_BIST_USER_WDATA1", 0x50818, 0 },
|
|
{ "EDC_H_BIST_USER_WDATA2", 0x5081c, 0 },
|
|
{ "USER_DATA_MASK", 8, 9 },
|
|
{ "USER_DATA2", 0, 8 },
|
|
{ "EDC_H_BIST_NUM_ERR", 0x50820, 0 },
|
|
{ "EDC_H_BIST_ERR_FIRST_ADDR", 0x50824, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50828, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5082c, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50830, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50834, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50838, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5083c, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50840, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50844, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50848, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5084c, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50850, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50854, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50858, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5085c, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50860, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50864, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x50868, 0 },
|
|
{ "EDC_H_BIST_STATUS_RDATA", 0x5086c, 0 },
|
|
{ "EDC_H_PAR_ENABLE", 0x50870, 0 },
|
|
{ "ECC_UE_PAR_ENABLE", 2, 1 },
|
|
{ "ECC_CE_PAR_ENABLE", 1, 1 },
|
|
{ "PERR_PAR_ENABLE", 0, 1 },
|
|
{ "EDC_H_INT_ENABLE", 0x50874, 0 },
|
|
{ "ECC_UE_INT_ENABLE", 2, 1 },
|
|
{ "ECC_CE_INT_ENABLE", 1, 1 },
|
|
{ "PERR_INT_ENABLE", 0, 1 },
|
|
{ "EDC_H_INT_CAUSE", 0x50878, 0 },
|
|
{ "ECC_UE_INT0_CAUSE", 5, 1 },
|
|
{ "ECC_CE_INT0_CAUSE", 4, 1 },
|
|
{ "PERR_INT0_CAUSE", 3, 1 },
|
|
{ "ECC_UE_INT_CAUSE", 2, 1 },
|
|
{ "ECC_CE_INT_CAUSE", 1, 1 },
|
|
{ "PERR_INT_CAUSE", 0, 1 },
|
|
{ "EDC_H_ECC_STATUS", 0x5087c, 0 },
|
|
{ "ECC_CECNT", 16, 16 },
|
|
{ "ECC_UECNT", 0, 16 },
|
|
{ "EDC_H_ECC_ERR_SEL", 0x50880, 0 },
|
|
{ "EDC_H_ECC_ERR_ADDR", 0x50884, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50890, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50894, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x50898, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x5089c, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508a0, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508a4, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508a8, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508ac, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508b0, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508b4, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508b8, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508bc, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508c0, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508c4, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508c8, 0 },
|
|
{ "EDC_H_ECC_ERR_DATA_RDATA", 0x508cc, 0 },
|
|
{ "EDC_H_BIST_CRC_SEED", 0x50c00, 0 },
|
|
{ NULL }
|
|
};
|
|
|
|
struct reg_info t5_hma_t5_regs[] = {
|
|
{ "HMA_TABLE_ACCESS", 0x51000, 0 },
|
|
{ "TRIG", 31, 1 },
|
|
{ "RW", 30, 1 },
|
|
{ "L_SEL", 0, 4 },
|
|
{ "HMA_TABLE_LINE0", 0x51004, 0 },
|
|
{ "HMA_TABLE_LINE1", 0x51008, 0 },
|
|
{ "HMA_TABLE_LINE2", 0x5100c, 0 },
|
|
{ "HMA_TABLE_LINE3", 0x51010, 0 },
|
|
{ "HMA_TABLE_LINE4", 0x51014, 0 },
|
|
{ "HMA_TABLE_LINE5", 0x51018, 0 },
|
|
{ "FID", 16, 11 },
|
|
{ "NOS", 15, 1 },
|
|
{ "RO", 14, 1 },
|
|
{ "HMA_COOKIE", 0x5101c, 0 },
|
|
{ "C_REQ", 31, 1 },
|
|
{ "C_FID", 18, 11 },
|
|
{ "C_VAL", 8, 10 },
|
|
{ "C_SEL", 0, 4 },
|
|
{ "HMA_PAR_ENABLE", 0x51300, 0 },
|
|
{ "HMA_INT_ENABLE", 0x51304, 0 },
|
|
{ "HMA_INT_CAUSE", 0x51308, 0 },
|
|
{ NULL }
|
|
};
|