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I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
48 lines
1.9 KiB
C
48 lines
1.9 KiB
C
/* $FreeBSD$ */
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/*-
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* Copyright 1998 Massachusetts Institute of Technology
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*
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* Permission to use, copy, modify, and distribute this software and
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* its documentation for any purpose and without fee is hereby
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* granted, provided that both the above copyright notice and this
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* permission notice appear in all copies, that both the above
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* copyright notice and this permission notice appear in all
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* supporting documentation, and that the name of M.I.T. not be used
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* in advertising or publicity pertaining to distribution of the
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* software without specific, written prior permission. M.I.T. makes
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* no representations about the suitability of this software for any
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* purpose. It is provided "as is" without express or implied
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* warranty.
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*
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* THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
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* ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
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* SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _MACHINE_RESOURCE_H_
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#define _MACHINE_RESOURCE_H_ 1
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/*
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* Definitions of resource types for Intel Architecture machines
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* with support for legacy ISA devices and drivers.
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*/
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#define SYS_RES_IRQ 1 /* interrupt lines */
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#define SYS_RES_DRQ 2 /* isa dma lines */
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#define SYS_RES_MEMORY 3 /* i/o memory */
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#define SYS_RES_IOPORT 4 /* i/o ports */
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#ifdef NEW_PCIB
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#define PCI_RES_BUS 5 /* PCI bus numbers */
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#endif
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#endif /* !_MACHINE_RESOURCE_H_ */
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