mirror of
https://git.savannah.gnu.org/git/emacs.git
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* verilog-mode.el (verilog-getopt-file, verilog-set-define):
Remove extra save-excursions and make-variable-buffer-local's.
Suggested by Stefan Monnier.
(verilog-getopt-file, verilog-module-inside-filename-p)
(verilog-set-define): Merge GNU 1.35 and repair changes from
switching to using with-current-buffer.
(verilog-read-always-signals-recurse): Fix "a == 2'b00 ? b : c"
being treated as a number and confusing AUTORESET.
Reported by Dan Dever.
(verilog-auto-ignore-concat, verilog-read-sub-decls-expr):
Add verilog-auto-ignore-concat to fix backward compatibility with
older verilog-modes. Reported by Dan Katz.
(verilog-read-auto-template): Fix AUTO_TEMPLATEs with regexps
containing closing anchors "...$".
(verilog-read-decls): Fix AUTOREG not detecting "assign {a,b}".
Reported by Wade Smith.
(verilog-batch-execute-func) Comment on function usage.
(verilog-label-re): Fix regular expression for labels.
(verilog-label-re, verilog-calc-1): Support proper indent of named
asserts.
(verilog-backward-token, verilog-basic-complete-re)
(verilog-beg-of-statement, verilog-indent-re): Support proper
indent of the assert statement at the beginning of a block of text.
(verilog-beg-block-re, verilog-ovm-begin-re): Support the
`ovm_object_param_utils_begin and `ovm_component_param_utils_begin
tokens as begins.
This commit is contained in:
Stefan Monnier
parent
f6a074209a
commit
148623016f
@ -1,3 +1,45 @@
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2009-11-05 Wilson Snyder <wsnyder@wsnyder.org>
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* verilog-mode.el (verilog-getopt-file, verilog-set-define):
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Remove extra save-excursions and make-variable-buffer-local's.
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Suggested by Stefan Monnier.
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(verilog-getopt-file, verilog-module-inside-filename-p)
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(verilog-set-define): Merge GNU 1.35 and repair changes from
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switching to using with-current-buffer.
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(verilog-read-always-signals-recurse): Fix "a == 2'b00 ? b : c"
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being treated as a number and confusing AUTORESET.
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Reported by Dan Dever.
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(verilog-auto-ignore-concat, verilog-read-sub-decls-expr):
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Add verilog-auto-ignore-concat to fix backward compatibility with
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older verilog-modes. Reported by Dan Katz.
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(verilog-read-auto-template): Fix AUTO_TEMPLATEs with regexps
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containing closing anchors "...$".
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(verilog-read-decls): Fix AUTOREG not detecting "assign {a,b}".
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Reported by Wade Smith.
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(verilog-batch-execute-func) Comment on function usage.
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2009-11-05 Michael McNamara <mac@mail.brushroad.com>
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* verilog-mode.el (verilog-label-re): Fix regular expression for
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labels.
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(verilog-label-re, verilog-calc-1): Support proper indent of named
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asserts.
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(verilog-backward-token, verilog-basic-complete-re)
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(verilog-beg-of-statement, verilog-indent-re): Support proper
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indent of the assert statement at the beginning of a block of text.
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(verilog-beg-block-re, verilog-ovm-begin-re): Support the
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`ovm_object_param_utils_begin and `ovm_component_param_utils_begin
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tokens as begins.
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2009-11-05 Glenn Morris <rgm@gnu.org>
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* emacs-lisp/bytecomp.el (byte-compile-insert-header): Drop test for
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@ -118,9 +118,9 @@
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;;; Code:
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;; This variable will always hold the version number of the mode
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(defconst verilog-mode-version "525"
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(defconst verilog-mode-version "547"
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"Version of this Verilog mode.")
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(defconst verilog-mode-release-date "2009-07-02-GNU"
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(defconst verilog-mode-release-date "2009-11-05-GNU"
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"Release date of this Verilog mode.")
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(defconst verilog-mode-release-emacs t
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"If non-nil, this version of Verilog mode was released with Emacs itself.")
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@ -579,6 +579,16 @@ The name of the function or case will be set between the braces."
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:type 'boolean)
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(put 'verilog-auto-endcomments 'safe-local-variable 'verilog-booleanp)
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(defcustom verilog-auto-ignore-concat nil
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"*True means ignore signals in {...} concatenations for AUTOWIRE etc.
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This will exclude signals referenced as pin connections in {...}
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from AUTOWIRE, AUTOOUTPUT and friends. This flag should be set
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for backward compatibility only and not set in new designs; it
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may be removed in future versions."
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:group 'verilog-mode-actions
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:type 'boolean)
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(put 'verilog-auto-ignore-concat 'safe-local-variable 'verilog-booleanp)
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(defcustom verilog-auto-read-includes nil
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"*True means to automatically read includes before AUTOs.
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This will do a `verilog-read-defines' and `verilog-read-includes' before
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@ -701,7 +711,7 @@ always be saved."
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'(
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("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t)
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("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t)
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("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t)
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("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t)
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@ -869,11 +879,11 @@ the MSB or LSB of a signal inside an AUTORESET."
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(put 'verilog-assignment-delay 'safe-local-variable 'stringp)
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(defcustom verilog-auto-arg-sort nil
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"*If set, AUTOARG will sort signal names, rather than leave them in
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declaration order. Declaration order is advantageous with order based
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instantiations and is the default for backward compatibility. Sorted order
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reduces changes when declarations are moved around in a file, and it's bad
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practice to rely on order based instantiations anyhow."
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"*If set, AUTOARG signal names will be sorted, not in delaration order.
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Declaration order is advantageous with order based instantiations
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and is the default for backward compatibility. Sorted order
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reduces changes when declarations are moved around in a file, and
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it's bad practice to rely on order based instantiations anyhow."
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:group 'verilog-mode-auto
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:type 'boolean)
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(put 'verilog-auto-arg-sort 'safe-local-variable 'verilog-booleanp)
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@ -1473,7 +1483,7 @@ find the errors."
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(cdr compilation-error-regexp-alist-alist)))))
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(if (boundp 'compilation-font-lock-keywords)
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(progn
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(make-variable-buffer-local 'compilation-font-lock-keywords)
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(make-local-variable 'compilation-font-lock-keywords)
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(setq compilation-font-lock-keywords verilog-error-font-lock-keywords)
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(font-lock-set-defaults)))
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;; Need to re-run compilation-error-regexp builder
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@ -1524,8 +1534,10 @@ find the errors."
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(verilog-regexp-opt
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'(
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"`ovm_component_utils_begin"
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"`ovm_component_param_utils_begin"
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"`ovm_field_utils_begin"
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"`ovm_object_utils_begin"
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"`ovm_object_param_utils_begin"
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"`ovm_sequence_utils_begin"
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"`ovm_sequencer_utils_begin"
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) nil )))
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@ -1658,6 +1670,7 @@ find the errors."
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;; a,
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;; b :
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(defconst verilog-label-re (concat verilog-symbol-re "\\s-*:\\s-*"))
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(defconst verilog-no-indent-begin-re
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"\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\|always_comb\\|always_ff\\|always_latch\\)\\>")
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@ -1778,11 +1791,11 @@ find the errors."
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"\\(\\<always_ff\\>\\(\[ \t\]*@\\)?\\)\\|" ; 5
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"\\(\\<always_latch\\>\\(\[ \t\]*@\\)?\\)\\|" ; 6
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"\\(\\<fork\\>\\)\\|" ; 7
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"\\(\\<always\\>\\(\[ \t\]*@\\)?\\)\\|"
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"\\(\\<always\\>\\(\[ \t\]*@\\)?\\)\\|"
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"\\(\\<if\\>\\)\\|"
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"\\(\\<clocking\\>\\)\\|"
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"\\(\\<task\\>\\)\\|"
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"\\(\\<function\\>\\)\\|"
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"\\(\\<task\\>\\)\\|"
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"\\(\\<function\\>\\)\\|"
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"\\(\\<initial\\>\\)\\|"
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"\\(\\<interface\\>\\)\\|"
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"\\(\\<package\\>\\)\\|"
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@ -1813,8 +1826,10 @@ find the errors."
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"task"
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;;; OVM
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"`ovm_component_utils_begin"
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"`ovm_component_param_utils_begin"
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"`ovm_field_utils_begin"
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"`ovm_object_utils_begin"
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"`ovm_object_param_utils_begin"
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"`ovm_sequence_utils_begin"
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"`ovm_sequencer_utils_begin"
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@ -1998,8 +2013,10 @@ find the errors."
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"`time_scale"
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;; OVM Begin tokens
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"`ovm_component_utils_begin"
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"`ovm_component_param_utils_begin"
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"`ovm_field_utils_begin"
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"`ovm_object_utils_begin"
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"`ovm_object_param_utils_begin"
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"`ovm_sequence_utils_begin"
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"`ovm_sequencer_utils_begin"
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;; OVM End tokens
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@ -2050,7 +2067,7 @@ find the errors."
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`(
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"always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
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"import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
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"if" "for" "forever" "foreach" "else" "parameter" "do" "localparam"
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"if" "for" "forever" "foreach" "else" "parameter" "do" "localparam" "assert"
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))))
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(defconst verilog-complete-reg
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(concat
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@ -3245,7 +3262,7 @@ With ARG, first kill any existing labels."
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(looking-at "\\<")
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(forward-word -1)))
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(and
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(looking-at verilog-extended-complete-re)
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(looking-at verilog-complete-reg)
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(not (save-excursion
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(verilog-backward-token)
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(looking-at verilog-extended-complete-re))))
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@ -4137,7 +4154,10 @@ This lets programs calling batch mode to easily extract error messages."
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(defun verilog-batch-execute-func (funref)
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"Internal processing of a batch command, running FUNREF on all command arguments."
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(verilog-batch-error-wrapper
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;; !!! FIXME: Setting global variables like that is *VERY NASTY* !!! --Stef
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;; Setting global variables like that is *VERY NASTY* !!! --Stef
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;; However, this function is called only when Emacs is being used as
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;; a standalone language instead of as an editor, so we'll live.
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;;
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;; General globals needed
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(setq make-backup-files nil)
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(setq-default make-backup-files nil)
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@ -4466,11 +4486,13 @@ Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
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((looking-at "\\<property\\>")
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; *sigh*
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; {assert|assume|cover} property (); are complete
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; and could also be labeled: - foo: assert property
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; but
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; property ID () ... needs end_property
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(verilog-beg-of-statement)
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(if (looking-at "\\(assert\\|assume\\|cover\\)\\s-+property\\>")
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(throw 'nesting 'statement) ; We don't need an endproperty for these
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(if (looking-at (concat "\\(" verilog-label-re "\\)?"
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"\\(assert\\|assume\\|cover\\)\\s-+property\\>"))
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(throw 'continue 'statement) ; We don't need an endproperty for these
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(throw 'nesting 'block) ;We still need a endproperty
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))
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@ -4487,7 +4509,7 @@ Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
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((looking-at verilog-defun-level-re)
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(if (looking-at verilog-defun-level-generate-only-re)
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(if (verilog-in-generate-region-p)
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(throw 'continue 'foo) ; always block in a generate
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(throw 'continue 'foo) ; always block in a generate - keep looking
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(throw 'nesting 'defun))
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(throw 'nesting 'defun)))
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@ -4668,7 +4690,7 @@ Set point to where line starts."
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continued))
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(defun verilog-backward-token ()
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"Step backward token, returing true if nil if continued line."
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"Step backward token, returing true if this is a continued line."
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(interactive)
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(verilog-backward-syntactic-ws)
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(cond
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@ -6587,23 +6609,19 @@ Return a array of [outputs inouts inputs wire reg assign const]."
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((eq ?= (following-char))
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(setq rvalue t newsig nil)
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(forward-char 1))
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((and (or rvalue sig-paren)
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(cond ((and (eq ?, (following-char))
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(eq paren sig-paren))
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(setq rvalue nil)
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(forward-char 1)
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t)
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;; ,'s can occur inside {} & funcs
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((looking-at "[{(]")
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(setq paren (1+ paren))
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(forward-char 1)
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t)
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((looking-at "[})]")
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(setq paren (1- paren))
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(forward-char 1)
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(when (< paren sig-paren)
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(setq expect-signal nil)) ; ) that ends variables inside v2k arg list
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t))))
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((and (eq ?, (following-char))
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(eq paren sig-paren))
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(setq rvalue nil)
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(forward-char 1))
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;; ,'s can occur inside {} & funcs
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((looking-at "[{(]")
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(setq paren (1+ paren))
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(forward-char 1))
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((looking-at "[})]")
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(setq paren (1- paren))
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(forward-char 1)
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(when (< paren sig-paren)
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(setq expect-signal nil))) ; ) that ends variables inside v2k arg list
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((looking-at "\\s-*\\(\\[[^]]+\\]\\)")
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(goto-char (match-end 0))
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(cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
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@ -6674,7 +6692,6 @@ Return a array of [outputs inouts inputs wire reg assign const]."
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((and expect-signal
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(eq functask 0)
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(not rvalue)
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(eq paren sig-paren)
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(not (member keywd verilog-keywords)))
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;; Add new signal to expect-signal's variable
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(setq newsig (list keywd vec nil nil enum signed typedefed multidim modport))
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@ -6791,10 +6808,11 @@ Return a array of [outputs inouts inputs wire reg assign const]."
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(cond
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;; {..., a, b} requires us to recurse on a,b
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((string-match "^\\s-*{\\([^{}]*\\)}\\s-*$" expr)
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(let ((mlst (split-string (match-string 1 expr) ","))
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mstr)
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(while (setq mstr (pop mlst))
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(verilog-read-sub-decls-expr submoddecls comment port mstr))))
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(unless verilog-auto-ignore-concat
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(let ((mlst (split-string (match-string 1 expr) ","))
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mstr)
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(while (setq mstr (pop mlst))
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(verilog-read-sub-decls-expr submoddecls comment port mstr)))))
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(t
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(let (sig vec multidim)
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(cond ;; Find \signal. Final space is part of escaped signal name
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@ -7017,7 +7035,7 @@ IGNORE-NEXT is true to ignore next token, fake from inside case statement."
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(point)))
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sig-last-tolk sig-tolk
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sig-tolk nil)
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;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S\n" (point) keywd rvalue ignore-next end-else-check))))
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;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S gs=%S\n" (point) keywd rvalue ignore-next end-else-check got-sig))))
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(cond
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((equal keywd "\"")
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(or (re-search-forward "[^\\]\"" nil t)
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@ -7044,7 +7062,7 @@ IGNORE-NEXT is true to ignore next token, fake from inside case statement."
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(setq end-else-check t))
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(forward-char 1))
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((equal keywd "'")
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(if (looking-at "'s?[hdxbo][0-9a-fA-F_xz? \t]*")
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(if (looking-at "'[sS]?[hdxboHDXBO]?[ \t]*[0-9a-fA-F_xzXZ?]+")
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(goto-char (match-end 0))
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(forward-char 1)))
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((equal keywd ":") ;; Case statement, begin/end label, x?y:z
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@ -7137,10 +7155,7 @@ IGNORE-NEXT is true to ignore next token, fake from inside case statement."
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uses-delayed) ;; Found signal/rvalue; push if not function
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(search-forward ")")
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(verilog-read-always-signals-recurse nil nil nil)
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;;(if dbg (with-current-buffer (get-buffer-create "*vl-dbg*")
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;; (delete-region (point-min) (point-max))
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;; (insert dbg)
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;; (setq dbg "")))
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;;(if dbg (with-current-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg ""))
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;; Return what was found
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(list sigs-out nil sigs-in uses-delayed))))
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@ -7188,7 +7203,7 @@ list of ( (signal_name connection_name)... )."
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(goto-char (match-end 0))
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;; Parse "REGEXP"
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;; We reserve @"..." for future lisp expressions that evaluate once-per-AUTOINST
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(when (looking-at "\\s-*\"\\([^\"]*)\\)\"")
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(when (looking-at "\\s-*\"\\([^\"]*\\)\"")
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(setq tpl-regexp (match-string 1))
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(goto-char (match-end 0)))
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(search-forward "(")
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@ -7256,13 +7271,13 @@ Optionally associate it with the specified enumeration ENUMNAME."
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(let ((mac (intern (concat "vh-" defname))))
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;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
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;; Need to define to a constant if no value given
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(set (make-variable-buffer-local mac)
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(set (make-local-variable mac)
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(if (equal defvalue "") "1" defvalue)))
|
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(if enumname
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(let ((enumvar (intern (concat "venum-" enumname))))
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;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
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(unless (boundp enumvar) (set enumvar nil))
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(make-variable-buffer-local enumvar)
|
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(make-local-variable enumvar)
|
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(add-to-list enumvar defname)))))
|
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|
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(defun verilog-read-defines (&optional filename recurse subcall)
|
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@ -7499,8 +7514,7 @@ Some macros and such are also found and included. For dinotrace.el."
|
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(forward-line 1)
|
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(when (string-match "//" line)
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(setq line (substring line 0 (match-beginning 0))))
|
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;; Variables are buffer-local, so need right context.
|
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(with-current-buffer orig-buffer
|
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(with-current-buffer orig-buffer ; Variables are buffer-local, so need right context.
|
||||
(verilog-getopt line))))))
|
||||
|
||||
(defun verilog-getopt-flags ()
|
||||
@ -7602,15 +7616,16 @@ Allows version control to check out the file if need be."
|
||||
(vc-backend filename)))
|
||||
(let (pt)
|
||||
(with-current-buffer (find-file-noselect filename)
|
||||
(goto-char (point-min))
|
||||
(while (and
|
||||
;; It may be tempting to look for verilog-defun-re,
|
||||
;; don't, it slows things down a lot!
|
||||
(verilog-re-search-forward-quick "\\<module\\>" nil t)
|
||||
(verilog-re-search-forward-quick "[(;]" nil t))
|
||||
(if (equal module (verilog-read-module-name))
|
||||
(setq pt (point))))
|
||||
pt))))
|
||||
(save-excursion
|
||||
(goto-char (point-min))
|
||||
(while (and
|
||||
;; It may be tempting to look for verilog-defun-re,
|
||||
;; don't, it slows things down a lot!
|
||||
(verilog-re-search-forward-quick "\\<module\\>" nil t)
|
||||
(verilog-re-search-forward-quick "[(;]" nil t))
|
||||
(if (equal module (verilog-read-module-name))
|
||||
(setq pt (point))))
|
||||
pt)))))
|
||||
|
||||
(defun verilog-is-number (symbol)
|
||||
"Return true if SYMBOL is number-like."
|
||||
@ -9731,7 +9746,7 @@ same expansion will result from only extracting signals starting with i:
|
||||
|
||||
/*AUTOINOUTMODULE(\"ExampMain\",\"^i\")*/
|
||||
|
||||
You may also provide an optional second regulat expression, in
|
||||
You may also provide an optional second regular expression, in
|
||||
which case only signals which have that pin direction and data
|
||||
type will be included. This matches against everything before
|
||||
the signal name in the declaration, for example against
|
||||
|
||||
Loading…
Reference in New Issue
Block a user