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Fix ModelSim error regexp in vhdl-mode

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* lisp/progmodes/vhdl-mode.el (vhdl-compiler-alist): Fix ModelSim
error regexp.  Suggested by Reto Zimmermann <reto@gnu.org>.
(Bug#62508)
This commit is contained in:
Eli Zaretskii 2023-04-01 13:07:42 +03:00
parent 24ed9c7ae7
commit 89ac5ba11c
1 changed files with 1 additions and 1 deletions
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2
lisp/progmodes/vhdl-mode.el
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@ -286,7 +286,7 @@ Overrides local variable `indent-tabs-mode'."
;; counter_rtl.vhd(29):Conditional signal assignment line__29
("ModelSim" "vcom" "-93 -work \\1" "make" "-f \\1"
nil "vlib \\1; vmap \\2 \\1" "./" "work/" "Makefile" "modelsim"
("\\(ERROR:\\|WARNING\\[[0-9]+\\]:\\|\\*\\* Error:\\|\\*\\* Warning: \\[[0-9]+\\]\\| +\\) \\([^ ]+\\)(\\([0-9]+\\)):" 2 3 nil)
("^\\(ERROR\\|WARNING\\|\\*\\* Error\\|\\*\\* Warning\\)[^:]*:\\( *\[[0-9]+\]\\| ([^)]+)\\)? \\([^ \t\n]+\\)(\\([0-9]+\\)):" 3 4 nil)
("" 0)
("\\1/_primary.dat" "\\2/\\1.dat" "\\1/_primary.dat"
"\\1/_primary.dat" "\\1/body.dat" downcase))