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(verilog-auto-output)
(verilog-auto-input, verilog-auto-inout, verilog-auto) (verilog-delete-auto): Add optional regular expression to AUTOINPUT/AUTOOUTPUT/AUTOINOUT. (verilog-signals-matching-regexp): New internal function for signal matching.
This commit is contained in:
Dan Nicolaescu
parent
98db7a382a
commit
e2076c2c17
@ -1,3 +1,12 @@
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2008-03-25 Wilson Snyder <wsnyder@wsnyder.org>
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* progmodes/verilog-mode.el (verilog-auto-output)
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(verilog-auto-input, verilog-auto-inout, verilog-auto)
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(verilog-delete-auto): Add optional regular expression to
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AUTOINPUT/AUTOOUTPUT/AUTOINOUT.
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(verilog-signals-matching-regexp): New internal function for
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signal matching.
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2008-03-25 Johan Bockg$(Q)[(Brd <bojohan@gnu.org>
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* info.el (Info-isearch-search): Always return point.
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@ -7333,6 +7333,17 @@ and invalidating the cache."
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(setq enumlist (cdr enumlist))))
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(nreverse out-list)))
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(defun verilog-signals-matching-regexp (in-list regexp)
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"Return all signals in IN-LIST matching the given REGEXP, if non-nil."
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(if (not regexp)
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in-list
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(let (out-list)
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(while in-list
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(if (string-match regexp (verilog-sig-name (car in-list)))
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(setq out-list (cons (car in-list) out-list)))
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(setq in-list (cdr in-list)))
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(nreverse out-list))))
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(defun verilog-signals-not-matching-regexp (in-list regexp)
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"Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
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(if (not regexp)
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@ -7643,15 +7654,28 @@ called before and after this function, respectively."
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;; Allow user to customize
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(run-hooks 'verilog-before-delete-auto-hook)
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;; Remove those that have multi-line insertions
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(verilog-auto-re-search-do "/\\*AUTO\\(OUTPUTEVERY\\|CONCATCOMMENT\\|WIRE\\|REG\\|DEFINEVALUE\\|REGINPUT\\|INPUT\\|OUTPUT\\|INOUT\\|RESET\\|TIEOFF\\|UNUSED\\)\\*/"
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'verilog-delete-autos-lined)
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;; Remove those that have multi-line insertions with parameters
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(verilog-auto-re-search-do "/\\*AUTO\\(INOUTMODULE\\|ASCIIENUM\\)([^)]*)\\*/"
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'verilog-delete-autos-lined)
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;; Remove those that have multi-line insertions, possibly with parameters
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(verilog-auto-re-search-do
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(concat "/\\*"
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(eval-when-compile
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(verilog-regexp-words
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`("AUTOASCIIENUM" "AUTOCONCATCOMMENT" "AUTODEFINEVALUE"
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"AUTOINOUT" "AUTOINOUTMODULE" "AUTOINPUT" "AUTOOUTPUT"
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"AUTOOUTPUTEVERY"
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"AUTOREG" "AUTOREGINPUT" "AUTORESET" "AUTOTIEOFF"
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"AUTOUNUSED" "AUTOWIRE")))
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"\\(\\|([^)]*)\\|(\"[^\"]*\")\\)" ; Optional parens or quoted parameter
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"\\*/")
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'verilog-delete-autos-lined)
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;; Remove those that are in parenthesis
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(verilog-auto-re-search-do "/\\*\\(AS\\|AUTO\\(ARG\\|CONCATWIDTH\\|INST\\|INSTPARAM\\|SENSE\\)\\)\\*/"
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'verilog-delete-to-paren)
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(verilog-auto-re-search-do
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(concat "/\\*"
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(eval-when-compile
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(verilog-regexp-words
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`("AS" "AUTOARG" "AUTOCONCATWIDTH" "AUTOINST" "AUTOINSTPARAM"
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"AUTOSENSE")))
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"\\*/")
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'verilog-delete-to-paren)
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;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments
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(verilog-auto-re-search-do "\\.\\*"
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'verilog-delete-auto-star-all)
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@ -8636,7 +8660,7 @@ Typing \\[verilog-auto] will make this into:
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(goto-char pnt)
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(verilog-pretty-expr "//"))))))
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(defun verilog-auto-output ()
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(defun verilog-auto-output (&optional with-params)
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"Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
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Make output statements for any output signal from an /*AUTOINST*/ that
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isn't a input to another AUTOINST. This is useful for modules which
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@ -8676,10 +8700,18 @@ Typing \\[verilog-auto] will make this into:
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.ov (ov[31:0]),
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// Inputs
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.i (i));
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endmodule"
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endmodule
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You may also provide an optional regular expression, in which case only
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signals matching the regular expression will be included. For example the
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same expansion will result from only extracting outputs starting with ov:
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/*AUTOOUTPUT(\"^ov\")*/"
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(save-excursion
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;; Point must be at insertion point.
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(let* ((indent-pt (current-indentation))
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(regexp (and with-params
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(nth 0 (verilog-read-auto-params 1))))
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(v2k (verilog-in-paren))
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(modi (verilog-modi-current))
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(sig-list (verilog-signals-not-in
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@ -8688,6 +8720,9 @@ Typing \\[verilog-auto] will make this into:
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(verilog-modi-get-inouts modi)
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(verilog-modi-get-sub-inputs modi)
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(verilog-modi-get-sub-inouts modi)))))
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(when regexp
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(setq sig-list (verilog-signals-matching-regexp
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sig-list regexp)))
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(setq sig-list (verilog-signals-not-matching-regexp
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sig-list verilog-auto-output-ignore-regexp))
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(forward-line 1)
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@ -8749,7 +8784,7 @@ Typing \\[verilog-auto] will make this into:
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(verilog-insert-indent "// End of automatics\n"))
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(when v2k (verilog-repair-close-comma)))))
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(defun verilog-auto-input ()
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(defun verilog-auto-input (&optional with-params)
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"Expand AUTOINPUT statements, as part of \\[verilog-auto].
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Make input statements for any input signal into an /*AUTOINST*/ that
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isn't declared elsewhere inside the module. This is useful for modules which
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@ -8789,9 +8824,17 @@ Typing \\[verilog-auto] will make this into:
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.ov (ov[31:0]),
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// Inputs
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.i (i));
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endmodule"
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endmodule
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You may also provide an optional regular expression, in which case only
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signals matching the regular expression will be included. For example the
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same expansion will result from only extracting inputs starting with i:
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/*AUTOINPUT(\"^i\")*/"
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(save-excursion
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(let* ((indent-pt (current-indentation))
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(regexp (and with-params
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(nth 0 (verilog-read-auto-params 1))))
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(v2k (verilog-in-paren))
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(modi (verilog-modi-current))
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(sig-list (verilog-signals-not-in
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@ -8804,6 +8847,9 @@ Typing \\[verilog-auto] will make this into:
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(verilog-modi-get-gparams modi)
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(verilog-modi-get-sub-outputs modi)
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(verilog-modi-get-sub-inouts modi)))))
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(when regexp
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(setq sig-list (verilog-signals-matching-regexp
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sig-list regexp)))
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(setq sig-list (verilog-signals-not-matching-regexp
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sig-list verilog-auto-input-ignore-regexp))
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(forward-line 1)
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@ -8815,7 +8861,7 @@ Typing \\[verilog-auto] will make this into:
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(verilog-insert-indent "// End of automatics\n"))
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(when v2k (verilog-repair-close-comma)))))
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(defun verilog-auto-inout ()
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(defun verilog-auto-inout (&optional with-params)
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"Expand AUTOINOUT statements, as part of \\[verilog-auto].
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Make inout statements for any inout signal in an /*AUTOINST*/ that
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isn't declared elsewhere inside the module.
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@ -8854,10 +8900,18 @@ Typing \\[verilog-auto] will make this into:
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.ov (ov[31:0]),
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// Inputs
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.i (i));
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endmodule"
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endmodule
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You may also provide an optional regular expression, in which case only
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signals matching the regular expression will be included. For example the
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same expansion will result from only extracting inouts starting with i:
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/*AUTOINOUT(\"^i\")*/"
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(save-excursion
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;; Point must be at insertion point.
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(let* ((indent-pt (current-indentation))
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(regexp (and with-params
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(nth 0 (verilog-read-auto-params 1))))
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(v2k (verilog-in-paren))
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(modi (verilog-modi-current))
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(sig-list (verilog-signals-not-in
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@ -8867,6 +8921,9 @@ Typing \\[verilog-auto] will make this into:
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(verilog-modi-get-inputs modi)
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(verilog-modi-get-sub-inputs modi)
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(verilog-modi-get-sub-outputs modi)))))
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(when regexp
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(setq sig-list (verilog-signals-matching-regexp
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sig-list regexp)))
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(setq sig-list (verilog-signals-not-matching-regexp
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sig-list verilog-auto-inout-ignore-regexp))
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(forward-line 1)
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@ -9556,9 +9613,15 @@ Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.com."
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;; first in/outs from other files
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(verilog-auto-re-search-do "/\\*AUTOINOUTMODULE([^)]*)\\*/" 'verilog-auto-inout-module)
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;; next in/outs which need previous sucked inputs first
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(verilog-auto-search-do "/*AUTOOUTPUT*/" 'verilog-auto-output)
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(verilog-auto-search-do "/*AUTOINPUT*/" 'verilog-auto-input)
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(verilog-auto-search-do "/*AUTOINOUT*/" 'verilog-auto-inout)
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(verilog-auto-re-search-do "/\\*AUTOOUTPUT\\((\"[^\"]*\")\\)\\*/"
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'(lambda () (verilog-auto-output t)))
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(verilog-auto-re-search-do "/\\*AUTOOUTPUT\\*/" 'verilog-auto-output)
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(verilog-auto-re-search-do "/\\*AUTOINPUT\\((\"[^\"]*\")\\)\\*/"
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'(lambda () (verilog-auto-input t)))
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(verilog-auto-re-search-do "/\\*AUTOINPUT\\*/" 'verilog-auto-input)
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(verilog-auto-re-search-do "/\\*AUTOINOUT\\((\"[^\"]*\")\\)\\*/"
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'(lambda () (verilog-auto-inout t)))
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(verilog-auto-re-search-do "/\\*AUTOINOUT\\*/" 'verilog-auto-inout)
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;; Then tie off those in/outs
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(verilog-auto-search-do "/*AUTOTIEOFF*/" 'verilog-auto-tieoff)
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;; Wires/regs must be after inputs/outputs
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