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Fix various verilog-mode.el issues.

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* lisp/progmodes/verilog-mode.el (verilog-read-decls): Fix SystemVerilog
2012 import breaking AUTOINST.  Reported by Johannes Schaefer.
(verilog-auto-wire-type, verilog-insert-definition): Fix AUTOWIRE using
logic in top-level non-SystemVerilog module, bug1142.  Reported by Marcin K.
(verilog-define-abbrev-table) (verilog-mode-abbrev-table): Don't expand
abbrev inside comment/strings, bug1102. Reported by Slava Yuzhaninov.
(verilog-auto): Fix AUTORESET widths pulling from AUTOREGINPUT,
msg2143. Reported by Galen Seitz.
(verilog-modify-compile-command): Fix expansion of __FLAGS__ when
compile-command is globally set, bug1119.  Reported by Galen Seitz.
This commit is contained in:
Wilson Snyder 2017-05-08 13:44:47 -04:00
parent 73e3ed48e2
commit e93f39d2e6
1 changed files with 67 additions and 24 deletions
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91
lisp/progmodes/verilog-mode.el
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@ -123,7 +123,7 @@
;;
;; This variable will always hold the version number of the mode
(defconst verilog-mode-version "2016-11-14-26d3540-vpo-GNU"
(defconst verilog-mode-version "2017-05-08-b240c8f-vpo-GNU"
"Version of this Verilog mode.")
(defconst verilog-mode-release-emacs t
"If non-nil, this version of Verilog mode was released with Emacs itself.")
@ -387,6 +387,14 @@ wherever possible, since it is slow."
;; `("Verilog" ("MA" ["SAA" nil :help "Help SAA"] ["SAB" nil :help "Help SAA"])
;; "----" ["MB" nil :help "Help MB"]))
(defun verilog-define-abbrev-table (tablename definitions &optional docstring &rest props)
"Filter `define-abbrev-table' TABLENAME DEFINITIONS
Provides DOCSTRING PROPS in newer Emacs (23.1)."
(condition-case nil
(apply 'define-abbrev-table tablename definitions docstring props)
(error
(define-abbrev-table tablename definitions))))
(defun verilog-define-abbrev (table name expansion &optional hook)
"Filter `define-abbrev' TABLE NAME EXPANSION and call HOOK.
Provides SYSTEM-FLAG in newer Emacs."
@ -762,10 +770,13 @@ mode is experimental."
(defcustom verilog-auto-wire-type nil
"Non-nil specifies the data type to use with `verilog-auto-wire' etc.
Set this to \"logic\" for SystemVerilog code, or use `verilog-auto-logic'."
Set this to \"logic\" for SystemVerilog code, or use `verilog-auto-logic'.
Set this to \"wire\" to force use of wire when logic is otherwise appropriate;
this is generally only appropriate when making a non-SystemVerilog wrapper
containing SystemVerilog cells."
:version "24.1" ; rev673
:group 'verilog-mode-actions
:type 'boolean)
:type 'string)
(put 'verilog-auto-wire-type 'safe-local-variable `stringp)
(defcustom verilog-auto-endcomments t
@ -1356,13 +1367,13 @@ See also `verilog-case-fold'."
:type 'hook)
(defcustom verilog-before-save-font-hook nil
"Hook run before `verilog-save-font-mods' removes highlighting."
"Hook run before `verilog-save-font-no-change-functions' removes highlighting."
:version "24.3" ; rev735
:group 'verilog-mode-auto
:type 'hook)
(defcustom verilog-after-save-font-hook nil
"Hook run after `verilog-save-font-mods' restores highlighting."
"Hook run after `verilog-save-font-no-change-functions' restores highlighting."
:version "24.3" ; rev735
:group 'verilog-mode-auto
:type 'hook)
@ -1702,7 +1713,13 @@ If set will become buffer local.")
(defvar verilog-mode-abbrev-table nil
"Abbrev table in use in Verilog-mode buffers.")
(define-abbrev-table 'verilog-mode-abbrev-table ())
;;(makunbound 'verilog-mode-abbrev-table) ; For testing, clear out old defvar
(verilog-define-abbrev-table
'verilog-mode-abbrev-table ()
"Abbrev table for Verilog mode skeletons."
:case-fixed t
;; Only expand in code.
:enable-function (lambda () (not (verilog-in-comment-or-string-p))))
(verilog-define-abbrev verilog-mode-abbrev-table "class" "" 'verilog-sk-ovm-class)
(verilog-define-abbrev verilog-mode-abbrev-table "always" "" 'verilog-sk-always)
(verilog-define-abbrev verilog-mode-abbrev-table "begin" nil `verilog-sk-begin)
@ -1943,13 +1960,29 @@ be substituted."
t t command))
command)
;; Eliminate compile warning
(defvar verilog-compile-command-pre-mod)
(defvar verilog-compile-command-post-mod)
(defun verilog-modify-compile-command ()
"Update `compile-command' using `verilog-expand-command'."
(when (and
(stringp compile-command)
(string-match "\\b\\(__FLAGS__\\|__FILE__\\)\\b" compile-command))
(set (make-local-variable 'compile-command)
(verilog-expand-command compile-command))))
;; Entry into verilog-mode a call to this before Local Variables exist
;; Likewise user may have hook or something that changes the flags.
;; So, remember we're responsible for the expansion and on re-entry
;; recompute __FLAGS__ on each reentry.
(when (stringp compile-command)
(when (and
(boundp 'verilog-compile-command-post-mod)
(equal compile-command verilog-compile-command-post-mod))
(setq compile-command verilog-compile-command-pre-mod))
(when (and
(string-match "\\b\\(__FLAGS__\\|__FILE__\\)\\b" compile-command))
(set (make-local-variable 'verilog-compile-command-pre-mod)
compile-command)
(set (make-local-variable 'compile-command)
(verilog-expand-command compile-command))
(set (make-local-variable 'verilog-compile-command-post-mod)
compile-command))))
(if (featurep 'xemacs)
;; Following code only gets called from compilation-mode-hook on XEmacs to add error handling.
@ -8428,13 +8461,13 @@ Return an array of [outputs inouts inputs wire reg assign const]."
;;(if dbg (setq dbg (concat dbg (format "Pt %s Vec %s C%c Kwd'%s'\n" (point) vec (following-char) keywd))))
(cond
((looking-at "//")
(if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
(setq enum (match-string 2)))
(when (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
(setq enum (match-string 2)))
(search-forward "\n"))
((looking-at "/\\*")
(forward-char 2)
(if (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
(setq enum (match-string 2)))
(when (looking-at "[^\n]*\\(auto\\|synopsys\\)\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
(setq enum (match-string 2)))
(or (search-forward "*/")
(error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
((looking-at "(\\*")
@ -8447,7 +8480,7 @@ Return an array of [outputs inouts inputs wire reg assign const]."
(error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
((eq ?\; (following-char))
(cond (in-ign-to-semi ; Such as inside a "import ...;" in a module header
(setq in-ign-to-semi nil))
(setq in-ign-to-semi nil rvalue nil))
((and in-modport (not (eq in-modport t))) ; end of a modport declaration
(verilog-modport-decls-set
in-modport
@ -8503,7 +8536,8 @@ Return an array of [outputs inouts inputs wire reg assign const]."
(when (string-match "^\\\\" (match-string 1))
(setq keywd (concat keywd " "))) ; Escaped ID needs space at end
;; Add any :: package names to same identifier
(while (looking-at "\\s-*::\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
;; '*' here is for "import x::*"
(while (looking-at "\\s-*::\\s-*\\(\\*\\|[a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
(goto-char (match-end 0))
(setq keywd (concat keywd "::" (match-string 1)))
(when (string-match "^\\\\" (match-string 1))
@ -8568,8 +8602,8 @@ Return an array of [outputs inouts inputs wire reg assign const]."
(not (equal last-keywd "default")))
(setq in-clocking t))
((equal keywd "import")
(if v2kargs-ok ; import in module header, not a modport import
(setq in-ign-to-semi t rvalue t)))
(when v2kargs-ok ; import in module header, not a modport import
(setq in-ign-to-semi t rvalue t)))
((equal keywd "type")
(setq ptype t))
((equal keywd "var"))
@ -10358,13 +10392,21 @@ When MODI is non-null, also add to modi-cache, for tracking."
(verilog-insert-one-definition
sig
;; Want "type x" or "output type x", not "wire type x"
(cond ((or (verilog-sig-type sig)
(cond ((and (equal "wire" verilog-auto-wire-type)
(or (not (verilog-sig-type sig))
(equal "logic" (verilog-sig-type sig))))
(if (member direction '("input" "output" "inout"))
direction
"wire"))
;;
((or (verilog-sig-type sig)
verilog-auto-wire-type)
(concat
(when (member direction '("input" "output" "inout"))
(concat direction " "))
(or (verilog-sig-type sig)
(or (verilog-sig-type sig)
verilog-auto-wire-type)))
;;
((and verilog-auto-declare-nettype
(member direction '("input" "output" "inout")))
(concat direction " " verilog-auto-declare-nettype))
@ -13761,9 +13803,6 @@ Wilson Snyder (wsnyder@wsnyder.org)."
(verilog-auto-re-search-do "/\\*AUTOINSTPARAM\\*/" 'verilog-auto-inst-param)
(verilog-auto-re-search-do "/\\*AUTOINST\\*/" 'verilog-auto-inst)
(verilog-auto-re-search-do "\\.\\*" 'verilog-auto-star)
;; Doesn't matter when done, but combine it with a common changer
(verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
(verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
;; Must be done before autoin/out as creates a reg
(verilog-auto-re-search-do "/\\*AUTOASCIIENUM(.*?)\\*/" 'verilog-auto-ascii-enum)
;;
@ -13789,6 +13828,10 @@ Wilson Snyder (wsnyder@wsnyder.org)."
(verilog-auto-re-search-do "/\\*AUTOREGINPUT\\*/" 'verilog-auto-reg-input)
;; outputevery needs AUTOOUTPUTs done first
(verilog-auto-re-search-do "/\\*AUTOOUTPUTEVERY\\((.*?)\\)?\\*/" 'verilog-auto-output-every)
;; Doesn't matter when done, but combine it with a common changer
(verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
;; After AUTOREG*, as they may have set signal widths
(verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
;; After we've created all new variables
(verilog-auto-re-search-do "/\\*AUTOUNUSED\\*/" 'verilog-auto-unused)
;; Must be after all inputs outputs are generated