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27 lines
1.5 KiB
Plaintext
27 lines
1.5 KiB
Plaintext
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sis is an interactive program for the synthesis of both synchronous
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and asynchronous sequential circuits. The input can be given in state
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table format or as logical equations (for synchronous circuits), or
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as a signal transition graph (for asynchronous circuits); a target
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technology library is given in genlib format. The output is a netlist
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of gates in the target technology.
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The system includes various capabilities that are controlled interactively
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by the user. These include state minimization, state assignment,
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optimization for area and delay using retiming, optimization using
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standard algebraic and Boolean combinational techniques from MISII,
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performance optimization using restructuring, and technology mapping
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for optimal area and delay. Redundancy removal and 100% testability
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are provided for combinational and scan-path circuits. Formal verification
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is available for both combinational and sequential circuits, even for
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circuits with different state encodings.
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This distribution contains sis, nova (state assignment), jedi (state
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assignment), stamina (state minimization, from June Rho at University of
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Colorado, Boulder), sred (state minimization), espresso, blif2vst (mapped
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BLIF to structural VHDL translator), vst2blif (structural VHDL to BLIF
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translator), xsis (a front-end graphical interface to sis) and several stripped
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down packages from the OctTools (options, port, and utility) that are needed
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for some of the programs listed above.
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Frank Volf, volf@oasis.IAEhv.nl
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