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[ maintainer ] emulators/pearpc: fix SDL build via update, fix build with JITC
PearPC 0.3.1 includes my patch for configure.in which makes SDL usable and fixes stdint.h/inttypes.h trouble. Fix build with JITC cpu for gcc34 PR: ports/72442 Submitted by: Roman Bogorodskiy <bogorodskiy@inbox.ru>
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Notes:
svn2git
2021-03-31 03:12:20 +00:00
svn path=/head/; revision=119120
@ -6,7 +6,7 @@
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#
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PORTNAME= pearpc
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PORTVERSION= 0.3.0
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PORTVERSION= 0.3.1
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CATEGORIES= emulators
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MASTER_SITES= ${MASTER_SITE_SOURCEFORGE}
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MASTER_SITE_SUBDIR= ${PORTNAME}
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@ -42,6 +42,13 @@ CONFIGURE_ARGS+= --disable-fpo
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#CONFIGURE_ARGS+= --enable-ui=nogui
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#.endif
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.if defined(WITH_SDL)
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CONFIGURE_ARGS+= --enable-ui=sdl
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USE_SDL= sdl
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.else
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CONFIGURE_ARGS+= --enable-ui=x11
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.endif
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.include <bsd.port.pre.mk>
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# jitc_x86 is avaible only on x86
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@ -68,11 +75,6 @@ pre-everything::
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@${ECHO_MSG} ""
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.endif
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post-patch:
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.if ${OSVERSION} < 500000
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@${REINPLACE_CMD} -e 's|stdint.h|inttypes.h|' ${WRKSRC}/src/system/osapi/posix/types.h
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.endif
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post-configure:
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@${REINPLACE_CMD} -e 's|-lpthread|${PTHREAD_LIBS}|g' ${WRKSRC}/Makefile
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@${REINPLACE_CMD} -e 's|-lpthread|${PTHREAD_LIBS}|g' ${WRKSRC}/src/Makefile
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@ -1,2 +1,2 @@
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MD5 (pearpc-0.3.0.tar.gz) = 6d68187c78cae674a5efa6662c4cdb22
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SIZE (pearpc-0.3.0.tar.gz) = 814686
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MD5 (pearpc-0.3.1.tar.gz) = d7ac0566f6ab884029e374ac68842932
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SIZE (pearpc-0.3.1.tar.gz) = 834258
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41
emulators/pearpc/files/patch-gcc34
Normal file
41
emulators/pearpc/files/patch-gcc34
Normal file
@ -0,0 +1,41 @@
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--- src/cpu/cpu_jitc_x86/ppc_cpu.h.orig Tue Oct 5 15:48:01 2004
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+++ src/cpu/cpu_jitc_x86/ppc_cpu.h Tue Oct 5 17:03:40 2004
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@@ -112,7 +112,8 @@
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uint32 current_code_base;
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} PACKED;
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-enum PPC_Register {
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+
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+/*enum PPC_Register {
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PPC_REG_NO = 0,
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PPC_GPR0 = offsetof(PPC_CPU_State, gpr),
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PPC_FPR1 = offsetof(PPC_CPU_State, fpr),
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@@ -132,7 +133,27 @@
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PPC_PVR = offsetof(PPC_CPU_State, pvr),
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PPC_HID0 = offsetof(PPC_CPU_State, hid),
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PPC_HID1 = offsetof(PPC_CPU_State, hid)+sizeof (uint32),
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-};
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+};*/
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+#define PPC_Register size_t
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+#define PPC_REG_NO 0
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+#define PPC_GPR0 offsetof(PPC_CPU_State, gpr)
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+#define PPC_FPR1 offsetof(PPC_CPU_State, fpr)
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+#define PPC_CR offsetof(PPC_CPU_State, cr)
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+#define PPC_FPSCR offsetof(PPC_CPU_State, fpscr)
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+#define PPC_XER offsetof(PPC_CPU_State, xer)
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+#define PPC_LR offsetof(PPC_CPU_State, lr)
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+#define PPC_CTR offsetof(PPC_CPU_State, ctr)
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+#define PPC_MSR offsetof(PPC_CPU_State, msr)
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+#define PPC_SRR0 offsetof(PPC_CPU_State, srr)
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+#define PPC_SRR1 offsetof(PPC_CPU_State, srr)+sizeof (uint32)
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+#define PPC_DSISR offsetof(PPC_CPU_State, dsisr)
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+#define PPC_DAR offsetof(PPC_CPU_State, dar)
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+#define PPC_DEC offsetof(PPC_CPU_State, dec)
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+#define PPC_SDR1 offsetof(PPC_CPU_State, sdr1)
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+#define PPC_EAR offsetof(PPC_CPU_State, ear)
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+#define PPC_PVR offsetof(PPC_CPU_State, pvr)
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+#define PPC_HID0 offsetof(PPC_CPU_State, hid)
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+#define PPC_HID1 offsetof(PPC_CPU_State, hid)+sizeof (uint32)
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enum PPC_CRx {
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PPC_CR0=0,
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