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Parameterize the target's byte ordering in the packing list. This
fixes the package builds for sparc64. PR: ports/57265 Submitted by: Marius Strobl <marius@alchemy.franken.de>
This commit is contained in:
parent
f19ea98306
commit
3684501415
Notes:
svn2git
2021-03-31 03:12:20 +00:00
svn path=/head/; revision=90647
@ -20,7 +20,8 @@ DIST_SUBDIR= ezm3
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INSTALL_TARGET= all
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INSTALL_TARGET= all
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MAKE_ARGS+= M3OPTIONS="-DBUILD_ALL -DSHIP_ALL"
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MAKE_ARGS+= M3OPTIONS="-DBUILD_ALL -DSHIP_ALL"
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MAN1= m3bundle.1
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MAN1= m3bundle.1
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PLIST_SUB+= ARCH=${ARCH} TARGET=${TARGET} WORDSIZE=${WORDSIZE}
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PLIST_SUB+= ARCH=${ARCH} TARGET=${TARGET} WORDSIZE=${WORDSIZE} \
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ENDIANESS=${ENDIANESS}
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SCRIPTS_ENV+= TARGET=${TARGET}
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SCRIPTS_ENV+= TARGET=${TARGET}
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USE_BZIP2= yes
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USE_BZIP2= yes
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USE_GMAKE= yes
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USE_GMAKE= yes
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@ -41,14 +42,17 @@ BROKEN= Not supported on versions earlier than 4.1-RELEASE
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.if ${ARCH} == "alpha"
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.if ${ARCH} == "alpha"
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TARGET= FBSD_ALPHA
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TARGET= FBSD_ALPHA
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WORDSIZE= 64
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WORDSIZE= 64
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ENDIANESS= le
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BOOTSTRAP= ezm3-${PORTVERSION}a-${TARGET}-boot.tar.bz2
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BOOTSTRAP= ezm3-${PORTVERSION}a-${TARGET}-boot.tar.bz2
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.elif ${ARCH} == "i386"
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.elif ${ARCH} == "i386"
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TARGET= FreeBSD4
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TARGET= FreeBSD4
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WORDSIZE= 32
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WORDSIZE= 32
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ENDIANESS= le
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BOOTSTRAP= ezm3-${PORTVERSION}-${TARGET}-boot.tar.bz2
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BOOTSTRAP= ezm3-${PORTVERSION}-${TARGET}-boot.tar.bz2
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.elif ${ARCH} == "sparc64"
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.elif ${ARCH} == "sparc64"
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TARGET= FBSD_SPARC64
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TARGET= FBSD_SPARC64
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WORDSIZE= 64
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WORDSIZE= 64
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ENDIANESS= be
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BOOTSTRAP= ezm3-${PORTVERSION}-${TARGET}-boot.tar.bz2
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BOOTSTRAP= ezm3-${PORTVERSION}-${TARGET}-boot.tar.bz2
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.endif
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.endif
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@ -299,8 +299,8 @@ lib/m3/pkg/m3core/src/float/Common/LongFloat.i3
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lib/m3/pkg/m3core/src/float/Common/RealFloat.i3
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lib/m3/pkg/m3core/src/float/Common/RealFloat.i3
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lib/m3/pkg/m3core/src/float/IEEE-default/FPU.i3
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lib/m3/pkg/m3core/src/float/IEEE-default/FPU.i3
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lib/m3/pkg/m3core/src/float/IEEE-default/FloatMode.i3
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lib/m3/pkg/m3core/src/float/IEEE-default/FloatMode.i3
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lib/m3/pkg/m3core/src/float/IEEE-le/LongRealRep.i3
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lib/m3/pkg/m3core/src/float/IEEE-%%ENDIANESS%%/LongRealRep.i3
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lib/m3/pkg/m3core/src/float/IEEE-le/RealRep.i3
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lib/m3/pkg/m3core/src/float/IEEE-%%ENDIANESS%%/RealRep.i3
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lib/m3/pkg/m3core/src/float/IEEE/Extended.i3
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lib/m3/pkg/m3core/src/float/IEEE/Extended.i3
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lib/m3/pkg/m3core/src/float/IEEE/LongReal.i3
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lib/m3/pkg/m3core/src/float/IEEE/LongReal.i3
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lib/m3/pkg/m3core/src/float/IEEE/Real.i3
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lib/m3/pkg/m3core/src/float/IEEE/Real.i3
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@ -971,7 +971,7 @@ share/ezm3/COPYRIGHT
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@dirrm lib/m3/pkg/m3core/src/C
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@dirrm lib/m3/pkg/m3core/src/C
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@dirrm lib/m3/pkg/m3core/src/float/IEEE-default
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@dirrm lib/m3/pkg/m3core/src/float/IEEE-default
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@dirrm lib/m3/pkg/m3core/src/float/IEEE
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@dirrm lib/m3/pkg/m3core/src/float/IEEE
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@dirrm lib/m3/pkg/m3core/src/float/IEEE-le
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@dirrm lib/m3/pkg/m3core/src/float/IEEE-%%ENDIANESS%%
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@dirrm lib/m3/pkg/m3core/src/float/Common
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@dirrm lib/m3/pkg/m3core/src/float/Common
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@dirrm lib/m3/pkg/m3core/src/float
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@dirrm lib/m3/pkg/m3core/src/float
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@dirrm lib/m3/pkg/m3core/src/convert
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@dirrm lib/m3/pkg/m3core/src/convert
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