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cad/yosys-systemverilog: Broken

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Reported by:	fallout
This commit is contained in:
Yuri Victorovich 2023-07-28 23:39:15 -07:00
parent e36fdf5bf7
commit 3a3bceadc7
1 changed files with 2 additions and 0 deletions
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2
cad/yosys-systemverilog/Makefile
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@ -10,6 +10,8 @@ WWW= https://github.com/antmicro/yosys-systemverilog
LICENSE= APACHE20
LICENSE_FILE= ${WRKSRC}/LICENSE
BROKEN= incompatible yet with the latest cad/uhdm, see https://github.com/antmicro/yosys-systemverilog/issues/1845
BUILD_DEPENDS= bash:shells/bash \
yosys>0:cad/yosys
LIB_DEPENDS= libcapnp.so:devel/capnproto \