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Remove expired port:

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2018-08-20 comms/usrp: Broken for more than 5 months
This commit is contained in:
Rene Ladan 2018-08-21 18:32:30 +00:00
parent 0ffa9d4e69
commit 4fd72d2cfe
Notes: svn2git 2021-03-31 03:12:20 +00:00 
svn path=/head/; revision=477750
44 changed files with 1 additions and 2925 deletions
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1
MOVED
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@ -10489,3 +10489,4 @@ mail/mutt14-lite||2018-08-21|Remove expired slave port
net/coda6_client||2018-08-21|Remove expired slave port
net/openmq-client||2018-08-21|Remove expired slave port
net-p2p/twister||2018-08-21|Has expired: Broken for more than 5 months
comms/usrp||2018-08-21|Has expired: Broken for more than 5 months

1
comms/Makefile
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@ -191,7 +191,6 @@
SUBDIR += uird
SUBDIR += unixcw
SUBDIR += usbmuxd
SUBDIR += usrp
SUBDIR += viewfax
SUBDIR += vrflash
SUBDIR += wsjt

113
comms/usrp/Makefile
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@ -1,113 +0,0 @@
# $FreeBSD$
PORTNAME= usrp
PORTVERSION= 3.4.3
PORTREVISION= 19
CATEGORIES= comms hamradio
MASTER_SITES= LOCAL/adrian
DISTNAME= Ettus-USRP-3.4.3
MAINTAINER= hamradio@FreeBSD.org
COMMENT= Ettus Research USRP driver framework
BROKEN= fails to build with boost 1.66, see bug 224088
DEPRECATED= Broken for more than 5 months
EXPIRATION_DATE= 2018-08-20
LIB_DEPENDS= ${PY_BOOST}
BUILD_DEPENDS= ${LOCALBASE}/include/boost/tuple/tuple.hpp:devel/boost-libs \
cheetah-analyze:devel/py-cheetah \
rst2html:textproc/py-docutils \
orcc:devel/orc \
sdcc:lang/sdcc
USES= compiler:c++0x cmake:outsource,noninja gmake pkgconfig python:run \
dos2unix shebangfix
COMPILER_FEATURES= libc++
USE_LDCONFIG= yes
CMAKE_SOURCE_PATH= ${WRKSRC}/host
MAKE_JOBS_UNSAFE= yes
SHEBANG_GLOB= *.py
# for excruciating debug use this -db
#CMAKE_ARGS+= --debug-output --trace
DOCSDIR= share/doc/uhd
WRKSRC= ${WRKDIR}/EttusResearch-UHD-Mirror-6047010
OPTIONS_DEFINE= USRP1 USRP2 DOCS DOXYGEN
OPTIONS_DEFAULT= USRP1 USRP2
USRP1_DESC= Build Ettus USRP1 firmware
USRP2_DESC= Build Ettus USRP2 firmware
OPTIONS_SUB= yes
.include <bsd.port.pre.mk>
.if ${OPSYS} == FreeBSD && ${OSVERSION} >= 1100000
BROKEN_i386= does not build on i386 FreeBSD 11.x and later
.endif
.if ${PORT_OPTIONS:MDOXYGEN}
BUILD_DEPENDS+= doxygen:devel/doxygen
CMAKE_ARGS+= -DENABLE_DOXYGEN:STRING="ON"
HAVEDOCS= YES
.endif
.if ${PORT_OPTIONS:MUSRP1}
BUILD_DEPENDS+= sdcc:lang/sdcc
USRP1= YES
.endif
.if ${PORT_OPTIONS:MUSRP2}
BUILD_DEPENDS+= ${LOCALBASE}/zpu/bin/zpu-elf-gcc:devel/zpu-gcc \
${LOCALBASE}/zpu/bin/zpu-elf-as:devel/zpu-binutils
USRP2= YES
.endif
CONFIGURE_WRKSRC= ${WRKSRC}/host
CMAKE_SOURCE_PATH= ${WRKSRC}/host
# usrp1 and usrp2 should be ports of their own
post-build:
# build usrp firmware
(export PATH=${LOCALBASE}/zpu/bin:${PATH};\
cd ${WRKSRC}/images && ${GMAKE} -f Makefile images)
.if USRP1
(cd ${WRKSRC}/images && ${GMAKE} -f Makefile images_usrp1)
.endif
.if USRP2
#firmware/fx2/build
(export PATH=${LOCALBASE}/zpu/bin:${PATH};\
cd ${WRKSRC}/images && ${GMAKE} -f Makefile images_usrp2)
.endif
do-install:
# install host component
# hack the install prefix now
@${REINPLACE_CMD} -e "s|/usr/local|${STAGEDIR}${PREFIX}|g" \
${CONFIGURE_WRKSRC}/cmake_install.cmake
cd ${CONFIGURE_WRKSRC} && ${MAKE} install
# install usrp firmware
${MKDIR} ${STAGEDIR}${PREFIX}/share/uhd
${MKDIR} ${STAGEDIR}${PREFIX}/share/uhd/images
.if USRP2
.for f in usrp_n200_fw.bin usrp2_fw.bin \
usrp_n210_fw.bin
${INSTALL_DATA} ${WRKSRC}/images/images/${f} ${STAGEDIR}${PREFIX}/share/uhd/images/$f
.endfor
.endif
.if USRP1
.for f in usrp1_fw.ihx usrp1_fpga.rbf usrp1_fpga_4rx.rbf usrp_b100_fw.ihx
${INSTALL_DATA} ${WRKSRC}/images/images/${f} ${STAGEDIR}${PREFIX}/share/uhd/images/$f
.endfor
${MKDIR} ${STAGEDIR}${PREFIX}/share/uhd/fpga/usrp1/rev2
${INSTALL_DATA} ${WRKSRC}/fpga/usrp1/rbf/rev2/*.rbf \
${STAGEDIR}${PREFIX}/share/uhd/fpga/usrp1/rev2
${MKDIR} ${STAGEDIR}${PREFIX}/share/uhd/fpga/usrp1/rev4
${INSTALL_DATA} ${WRKSRC}/fpga/usrp1/rbf/rev4/*.rbf \
${STAGEDIR}${PREFIX}/share/uhd/fpga/usrp1/rev4
.endif
.include <bsd.port.post.mk>

2
comms/usrp/distinfo
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@ -1,2 +0,0 @@
SHA256 (Ettus-USRP-3.4.3.tar.gz) = 536b3b1ba7c9bb1b7c87c197708083b47efb3b3cdc14b841230f093fa915961b
SIZE (Ettus-USRP-3.4.3.tar.gz) = 6215038

20
comms/usrp/files/patch-firmware_fx2_CMakeLists.txt
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@ -1,20 +0,0 @@
--- firmware/fx2/CMakeLists.txt.orig 2012-07-30 14:09:48.000000000 -0500
+++ firmware/fx2/CMakeLists.txt 2012-10-27 08:07:39.000000000 -0500
@@ -25,13 +25,16 @@
# Set toolchain to use SDCC
########################################################################
# we're doing mixed ASM and C
-ENABLE_LANGUAGE(ASM_SDCC)
+ENABLE_LANGUAGE(ASM_SDCC OPTIONAL)
+
+#SET(CMAKE_ASM_SDCC_COMPILER /usr/local/bin/sdcc)
########################################################################
# C flags and linking flags
########################################################################
ADD_DEFINITIONS(-DHAVE_USRP2)
set(CMAKE_C_LINK_FLAGS "--code-loc 0x0000 --code-size 0x1800 --xram-loc 0x1800 --xram-size 0x0800 -Wl '-b USBDESCSEG = 0xE000'")
+set(C_DEFINES "--code-loc 0x0000 --code-size 0x1800 --xram-loc 0x1800 --xram-size 0x0800 -Wl '-b USBDESCSEG = 0xE000'")
set(CMAKE_C_FLAGS "--no-xinit-opt")
########################################################################

11
comms/usrp/files/patch-firmware_fx2_b100_CMakeLists.txt
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@ -1,11 +0,0 @@
--- firmware/fx2/b100/CMakeLists.txt.orig 2012-10-10 16:53:23.000000000 -0500
+++ firmware/fx2/b100/CMakeLists.txt 2012-10-10 16:53:31.000000000 -0500
@@ -66,7 +66,7 @@
set_source_files_properties(
${CMAKE_CURRENT_SOURCE_DIR}/usrp_main.c
- PROPERTIES COMPILE_FLAGS "--std-sdcc99 --opt-code-speed --fommit-frame-pointer"
+ PROPERTIES COMPILE_FLAGS "--std-sdcc99 --opt-code-speed --fomit-frame-pointer"
)
add_executable(b100_fw ${b100_sources})

11
comms/usrp/files/patch-firmware_fx2_b100_board_specific.c
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@ -1,11 +0,0 @@
--- firmware/fx2/b100/board_specific.c.orig 2012-10-10 13:42:54.000000000 -0500
+++ firmware/fx2/b100/board_specific.c 2012-10-10 13:43:04.000000000 -0500
@@ -58,7 +58,7 @@
// NOP on usrp1
}
-static xdata unsigned char xbuf[1];
+static __xdata unsigned char xbuf[1];
void
init_board (void)

29
comms/usrp/files/patch-firmware_fx2_b100_eeprom_io.c
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@ -1,29 +0,0 @@
--- firmware/fx2/b100/eeprom_io.c.orig 2012-10-10 13:40:13.000000000 -0500
+++ firmware/fx2/b100/eeprom_io.c 2012-10-10 13:40:39.000000000 -0500
@@ -27,12 +27,12 @@
// returns non-zero if successful, else 0
unsigned char
eeprom_read (unsigned char i2c_addr, unsigned char eeprom_offset,
- xdata unsigned char *buf, unsigned char len)
+ __xdata unsigned char *buf, unsigned char len)
{
// We setup a random read by first doing a "zero byte write".
// Writes carry an address. Reads use an implicit address.
- static xdata unsigned char cmd[1];
+ static __xdata unsigned char cmd[1];
cmd[0] = eeprom_offset;
if (!i2c_write(i2c_addr, cmd, 1))
return 0;
@@ -46,9 +46,9 @@
// returns non-zero if successful, else 0
unsigned char
eeprom_write (unsigned char i2c_addr, unsigned char eeprom_offset,
- const xdata unsigned char *buf, unsigned char len)
+ const __xdata unsigned char *buf, unsigned char len)
{
- static xdata unsigned char cmd[2];
+ static __xdata unsigned char cmd[2];
unsigned char ok;
while (len-- > 0){

17
comms/usrp/files/patch-firmware_fx2_b100_eeprom_io.h
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@ -1,17 +0,0 @@
--- firmware/fx2/b100/eeprom_io.h.orig 2012-10-10 16:55:20.000000000 -0500
+++ firmware/fx2/b100/eeprom_io.h 2012-10-10 16:55:36.000000000 -0500
@@ -27,12 +27,12 @@
// returns non-zero if successful, else 0
unsigned char
eeprom_read (unsigned char i2c_addr, unsigned char eeprom_offset,
- xdata unsigned char *buf, unsigned char len);
+ __xdata unsigned char *buf, unsigned char len);
// returns non-zero if successful, else 0
unsigned char
eeprom_write (unsigned char i2c_addr, unsigned char eeprom_offset,
- const xdata unsigned char *buf, unsigned char len);
+ const __xdata unsigned char *buf, unsigned char len);
#endif /* INCLUDED_EEPROM_IO_H */

40
comms/usrp/files/patch-firmware_fx2_b100_fpga_load.c
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@ -1,40 +0,0 @@
--- firmware/fx2/b100/fpga_load.c.orig 2012-10-10 13:41:50.000000000 -0500
+++ firmware/fx2/b100/fpga_load.c 2012-10-10 16:37:38.000000000 -0500
@@ -82,9 +82,9 @@
#else
static void
-clock_out_config_byte (unsigned char bits) _naked
+clock_out_config_byte (unsigned char bits) __naked
{
- _asm
+ __asm
mov a, dpl
rlc a
@@ -129,14 +129,14 @@
ret
- _endasm;
+ __endasm;
}
#endif
static void
clock_out_bytes (unsigned char bytecount,
- unsigned char xdata *p)
+ unsigned char __xdata *p)
{
while (bytecount-- > 0)
clock_out_config_byte (*p++);
@@ -156,7 +156,7 @@
* ALTERA_NSTATUS = 1 (input)
*/
unsigned char
-fpga_load_xfer (xdata unsigned char *p, unsigned char bytecount)
+fpga_load_xfer (__xdata unsigned char *p, unsigned char bytecount)
{
clock_out_bytes (bytecount, p);
return 1;

18
comms/usrp/files/patch-firmware_fx2_b100_fpga_rev2.c
View File

@ -1,18 +0,0 @@
--- firmware/fx2/b100/fpga_rev2.c.orig 2012-10-10 13:42:24.000000000 -0500
+++ firmware/fx2/b100/fpga_rev2.c 2012-10-10 13:42:45.000000000 -0500
@@ -29,13 +29,13 @@
unsigned char g_rx_reset = 0;
void
-fpga_write_reg (unsigned char regno, const xdata unsigned char *regval)
+fpga_write_reg (unsigned char regno, const __xdata unsigned char *regval)
{
//nop
}
-static xdata unsigned char regval[4] = {0, 0, 0, 0};
+static __xdata unsigned char regval[4] = {0, 0, 0, 0};
// Resets both AD9862's and the FPGA serial bus interface.

29
comms/usrp/files/patch-firmware_fx2_b100_gpif.c
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@ -1,29 +0,0 @@
--- firmware/fx2/b100/gpif.c.orig 2012-10-10 13:39:33.000000000 -0500
+++ firmware/fx2/b100/gpif.c 2012-10-10 13:39:56.000000000 -0500
@@ -156,7 +156,7 @@
// END DO NOT EDIT
// DO NOT EDIT ...
-const char xdata WaveData[128] =
+const char __xdata WaveData[128] =
{
// Wave 0
/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
@@ -182,7 +182,7 @@
// END DO NOT EDIT
// DO NOT EDIT ...
-const char xdata FlowStates[36] =
+const char __xdata FlowStates[36] =
{
/* Wave 0 FlowStates */ 0x81,0x2D,0x0E,0x00,0x00,0x04,0x03,0x02,0x00,
/* Wave 1 FlowStates */ 0x81,0x2D,0x09,0x00,0x00,0x04,0x03,0x02,0x00,
@@ -192,7 +192,7 @@
// END DO NOT EDIT
// DO NOT EDIT ...
-const char xdata InitData[7] =
+const char __xdata InitData[7] =
{
/* Regs */ 0xA0,0x00,0x00,0x00,0xEE,0x4E,0x00
};

39
comms/usrp/files/patch-firmware_fx2_b100_usrp_main.c
View File

@ -1,39 +0,0 @@
--- firmware/fx2/b100/usrp_main.c.orig 2012-10-10 13:41:00.000000000 -0500
+++ firmware/fx2/b100/usrp_main.c 2012-10-10 16:35:30.000000000 -0500
@@ -54,14 +54,14 @@
unsigned char g_rx_enable = 0;
unsigned char g_rx_overrun = 0;
unsigned char g_tx_underrun = 0;
-bit enable_gpif = 0;
+__bit enable_gpif = 0;
/*
* the host side fpga loader code pushes an MD5 hash of the bitstream
* into hash1.
*/
#define USRP_HASH_SIZE 16
-xdata at USRP_HASH_SLOT_1_ADDR unsigned char hash1[USRP_HASH_SIZE];
+__xdata __at USRP_HASH_SLOT_1_ADDR unsigned char hash1[USRP_HASH_SIZE];
//void clear_fpga_data_fifo(void);
@@ -220,7 +220,7 @@
* Toggle led 0
*/
void
-isr_tick (void) interrupt
+isr_tick (void) __interrupt
{
static unsigned char count = 1;
@@ -239,8 +239,8 @@
void
patch_usb_descriptors(void)
{
- static xdata unsigned char hw_rev;
- static xdata unsigned char serial_no[SERIAL_NO_LEN];
+ static __xdata unsigned char hw_rev;
+ static __xdata unsigned char serial_no[SERIAL_NO_LEN];
unsigned char i;
eeprom_read(I2C_ADDR_BOOT, HW_REV_OFFSET, &hw_rev, 1); // LSB of device id

18
comms/usrp/files/patch-firmware_fx2_b100_usrp_regs.h
View File

@ -1,18 +0,0 @@
--- firmware/fx2/b100/usrp_regs.h.orig 2012-10-10 16:32:04.000000000 -0500
+++ firmware/fx2/b100/usrp_regs.h 2012-10-10 16:33:34.000000000 -0500
@@ -59,11 +59,11 @@
#define PORT_A_ADDR 0x80
#define PORT_C_ADDR 0xA0
-sbit at PORT_A_ADDR+0 bitALTERA_DCLK; // 0x80 is the bit address of PORT A
-sbit at PORT_A_ADDR+1 bitALTERA_NCONFIG;
-sbit at PORT_A_ADDR+3 bitALTERA_DATA0;
+__sbit __at PORT_A_ADDR+0 bitALTERA_DCLK; // 0x80 is the bit address of PORT A
+__sbit __at PORT_A_ADDR+1 bitALTERA_NCONFIG;
+__sbit __at PORT_A_ADDR+3 bitALTERA_DATA0;
-sbit at PORT_C_ADDR+7 bitALTERA_CONF_DONE;
+__sbit __at PORT_C_ADDR+7 bitALTERA_CONF_DONE;
/* Port B: GPIF FD[7:0] */

40
comms/usrp/files/patch-firmware_fx2_common_delay.c
View File

@ -1,40 +0,0 @@
--- firmware/fx2/common/delay.c.orig 2012-07-30 14:09:48.000000000 -0500
+++ firmware/fx2/common/delay.c 2012-10-07 19:36:36.000000000 -0500
@@ -24,11 +24,12 @@
* Delay approximately 1 microsecond (including overhead in udelay).
*/
static void
-udelay1 (void) _naked
+udelay1 (void)
+//__naked
{
- _asm ; lcall that got us here took 4 bus cycles
+ __asm ; lcall that got us here took 4 bus cycles
ret ; 4 bus cycles
- _endasm;
+ __endasm;
}
/*
@@ -51,9 +52,10 @@
* but explains the factor of 4 problem below).
*/
static void
-mdelay1 (void) _naked
+mdelay1 (void)
+// _naked
{
- _asm
+ __asm
mov dptr,#(-1200 & 0xffff)
002$:
inc dptr ; 3 bus cycles
@@ -62,7 +64,7 @@
jnz 002$ ; 3 bus cycles
ret
- _endasm;
+ __endasm;
}
void

11
comms/usrp/files/patch-firmware_fx2_common_eeprom_init.c
View File

@ -1,11 +0,0 @@
--- firmware/fx2/common/eeprom_init.c.orig 2012-07-30 14:09:48.000000000 -0500
+++ firmware/fx2/common/eeprom_init.c 2012-10-07 20:10:02.000000000 -0500
@@ -28,7 +28,7 @@
* into hash1.
*/
#define USRP_HASH_SIZE 16
-xdata at USRP_HASH_SLOT_0_ADDR unsigned char hash0[USRP_HASH_SIZE];
+__xdata __at USRP_HASH_SLOT_0_ADDR unsigned char hash0[USRP_HASH_SIZE];
#define REG_RX_PWR_DN 1

11
comms/usrp/files/patch-firmware_fx2_common_fpga_load.h
View File

@ -1,11 +0,0 @@
--- firmware/fx2/common/fpga_load.h.orig 2012-07-30 14:09:48.000000000 -0500
+++ firmware/fx2/common/fpga_load.h 2012-10-07 19:38:19.000000000 -0500
@@ -22,7 +22,7 @@
#define INCLUDED_FPGA_LOAD_H
unsigned char fpga_load_begin (void);
-unsigned char fpga_load_xfer (xdata unsigned char *p, unsigned char len);
+unsigned char fpga_load_xfer (__xdata unsigned char *p, unsigned char len);
unsigned char fpga_load_end (void);
#endif /* INCLUDED_FPGA_LOAD_H */

821
comms/usrp/files/patch-firmware_fx2_common_fx2regs.h
View File

@ -1,821 +0,0 @@
--- firmware/fx2/common/fx2regs.h.orig 2012-07-30 14:09:48.000000000 -0500
+++ firmware/fx2/common/fx2regs.h 2012-10-10 13:21:13.000000000 -0500
@@ -48,22 +48,22 @@
// The Ez-USB FX2 registers are defined here. We use FX2regs.h for register
// address allocation by using "#define ALLOCATE_EXTERN".
// When using "#define ALLOCATE_EXTERN", you get (for instance):
-// xdata volatile BYTE OUT7BUF[64] _at_ 0x7B40;
+// __xdata volatile BYTE OUT7BUF[64] __at 0x7B40;
// Such lines are created from FX2.h by using the preprocessor.
// Incidently, these lines will not generate any space in the resulting hex
// file; they just bind the symbols to the addresses for compilation.
// You just need to put "#define ALLOCATE_EXTERN" in your main program file;
// i.e. fw.c or a stand-alone C source file.
// Without "#define ALLOCATE_EXTERN", you just get the external reference:
-// extern xdata volatile BYTE OUT7BUF[64] ;// 0x7B40;
+// extern __xdata volatile BYTE OUT7BUF[64] ;// 0x7B40;
// This uses the concatenation operator "##" to insert a comment "//"
-// to cut off the end of the line, "_at_ 0x7B40;", which is not wanted.
+// to cut off the end of the line, "__at 0x7B40;", which is not wanted.
*/
#ifdef ALLOCATE_EXTERN
#define EXTERN
-#define _AT_(a) at a
+#define _AT_(a) __at a
#else
#define EXTERN extern
#define _AT_ ;/ ## /
@@ -72,162 +72,162 @@
typedef unsigned char BYTE;
typedef unsigned short WORD;
-EXTERN xdata _AT_(0xE400) volatile BYTE GPIF_WAVE_DATA[128];
-EXTERN xdata _AT_(0xE480) volatile BYTE RES_WAVEDATA_END ;
+EXTERN __xdata _AT_(0xE400) volatile BYTE GPIF_WAVE_DATA[128];
+EXTERN __xdata _AT_(0xE480) volatile BYTE RES_WAVEDATA_END ;
// General Configuration
-EXTERN xdata _AT_(0xE600) volatile BYTE CPUCS ; // Control & Status
-EXTERN xdata _AT_(0xE601) volatile BYTE IFCONFIG ; // Interface Configuration
-EXTERN xdata _AT_(0xE602) volatile BYTE PINFLAGSAB ; // FIFO FLAGA and FLAGB Assignments
-EXTERN xdata _AT_(0xE603) volatile BYTE PINFLAGSCD ; // FIFO FLAGC and FLAGD Assignments
-EXTERN xdata _AT_(0xE604) volatile BYTE FIFORESET ; // Restore FIFOS to default state
-EXTERN xdata _AT_(0xE605) volatile BYTE BREAKPT ; // Breakpoint
-EXTERN xdata _AT_(0xE606) volatile BYTE BPADDRH ; // Breakpoint Address H
-EXTERN xdata _AT_(0xE607) volatile BYTE BPADDRL ; // Breakpoint Address L
-EXTERN xdata _AT_(0xE608) volatile BYTE UART230 ; // 230 Kbaud clock for T0,T1,T2
-EXTERN xdata _AT_(0xE609) volatile BYTE FIFOPINPOLAR ; // FIFO polarities
-EXTERN xdata _AT_(0xE60A) volatile BYTE REVID ; // Chip Revision
-EXTERN xdata _AT_(0xE60B) volatile BYTE REVCTL ; // Chip Revision Control
+EXTERN __xdata _AT_(0xE600) volatile BYTE CPUCS ; // Control & Status
+EXTERN __xdata _AT_(0xE601) volatile BYTE IFCONFIG ; // Interface Configuration
+EXTERN __xdata _AT_(0xE602) volatile BYTE PINFLAGSAB ; // FIFO FLAGA and FLAGB Assignments
+EXTERN __xdata _AT_(0xE603) volatile BYTE PINFLAGSCD ; // FIFO FLAGC and FLAGD Assignments
+EXTERN __xdata _AT_(0xE604) volatile BYTE FIFORESET ; // Restore FIFOS to default state
+EXTERN __xdata _AT_(0xE605) volatile BYTE BREAKPT ; // Breakpoint
+EXTERN __xdata _AT_(0xE606) volatile BYTE BPADDRH ; // Breakpoint Address H
+EXTERN __xdata _AT_(0xE607) volatile BYTE BPADDRL ; // Breakpoint Address L
+EXTERN __xdata _AT_(0xE608) volatile BYTE UART230 ; // 230 Kbaud clock for T0,T1,T2
+EXTERN __xdata _AT_(0xE609) volatile BYTE FIFOPINPOLAR ; // FIFO polarities
+EXTERN __xdata _AT_(0xE60A) volatile BYTE REVID ; // Chip Revision
+EXTERN __xdata _AT_(0xE60B) volatile BYTE REVCTL ; // Chip Revision Control
// Endpoint Configuration
-EXTERN xdata _AT_(0xE610) volatile BYTE EP1OUTCFG ; // Endpoint 1-OUT Configuration
-EXTERN xdata _AT_(0xE611) volatile BYTE EP1INCFG ; // Endpoint 1-IN Configuration
-EXTERN xdata _AT_(0xE612) volatile BYTE EP2CFG ; // Endpoint 2 Configuration
-EXTERN xdata _AT_(0xE613) volatile BYTE EP4CFG ; // Endpoint 4 Configuration
-EXTERN xdata _AT_(0xE614) volatile BYTE EP6CFG ; // Endpoint 6 Configuration
-EXTERN xdata _AT_(0xE615) volatile BYTE EP8CFG ; // Endpoint 8 Configuration
-EXTERN xdata _AT_(0xE618) volatile BYTE EP2FIFOCFG ; // Endpoint 2 FIFO configuration
-EXTERN xdata _AT_(0xE619) volatile BYTE EP4FIFOCFG ; // Endpoint 4 FIFO configuration
-EXTERN xdata _AT_(0xE61A) volatile BYTE EP6FIFOCFG ; // Endpoint 6 FIFO configuration
-EXTERN xdata _AT_(0xE61B) volatile BYTE EP8FIFOCFG ; // Endpoint 8 FIFO configuration
-EXTERN xdata _AT_(0xE620) volatile BYTE EP2AUTOINLENH ; // Endpoint 2 Packet Length H (IN only)
-EXTERN xdata _AT_(0xE621) volatile BYTE EP2AUTOINLENL ; // Endpoint 2 Packet Length L (IN only)
-EXTERN xdata _AT_(0xE622) volatile BYTE EP4AUTOINLENH ; // Endpoint 4 Packet Length H (IN only)
-EXTERN xdata _AT_(0xE623) volatile BYTE EP4AUTOINLENL ; // Endpoint 4 Packet Length L (IN only)
-EXTERN xdata _AT_(0xE624) volatile BYTE EP6AUTOINLENH ; // Endpoint 6 Packet Length H (IN only)
-EXTERN xdata _AT_(0xE625) volatile BYTE EP6AUTOINLENL ; // Endpoint 6 Packet Length L (IN only)
-EXTERN xdata _AT_(0xE626) volatile BYTE EP8AUTOINLENH ; // Endpoint 8 Packet Length H (IN only)
-EXTERN xdata _AT_(0xE627) volatile BYTE EP8AUTOINLENL ; // Endpoint 8 Packet Length L (IN only)
-EXTERN xdata _AT_(0xE630) volatile BYTE EP2FIFOPFH ; // EP2 Programmable Flag trigger H
-EXTERN xdata _AT_(0xE631) volatile BYTE EP2FIFOPFL ; // EP2 Programmable Flag trigger L
-EXTERN xdata _AT_(0xE632) volatile BYTE EP4FIFOPFH ; // EP4 Programmable Flag trigger H
-EXTERN xdata _AT_(0xE633) volatile BYTE EP4FIFOPFL ; // EP4 Programmable Flag trigger L
-EXTERN xdata _AT_(0xE634) volatile BYTE EP6FIFOPFH ; // EP6 Programmable Flag trigger H
-EXTERN xdata _AT_(0xE635) volatile BYTE EP6FIFOPFL ; // EP6 Programmable Flag trigger L
-EXTERN xdata _AT_(0xE636) volatile BYTE EP8FIFOPFH ; // EP8 Programmable Flag trigger H
-EXTERN xdata _AT_(0xE637) volatile BYTE EP8FIFOPFL ; // EP8 Programmable Flag trigger L
-EXTERN xdata _AT_(0xE640) volatile BYTE EP2ISOINPKTS ; // EP2 (if ISO) IN Packets per frame (1-3)
-EXTERN xdata _AT_(0xE641) volatile BYTE EP4ISOINPKTS ; // EP4 (if ISO) IN Packets per frame (1-3)
-EXTERN xdata _AT_(0xE642) volatile BYTE EP6ISOINPKTS ; // EP6 (if ISO) IN Packets per frame (1-3)
-EXTERN xdata _AT_(0xE643) volatile BYTE EP8ISOINPKTS ; // EP8 (if ISO) IN Packets per frame (1-3)
-EXTERN xdata _AT_(0xE648) volatile BYTE INPKTEND ; // Force IN Packet End
-EXTERN xdata _AT_(0xE649) volatile BYTE OUTPKTEND ; // Force OUT Packet End
+EXTERN __xdata _AT_(0xE610) volatile BYTE EP1OUTCFG ; // Endpoint 1-OUT Configuration
+EXTERN __xdata _AT_(0xE611) volatile BYTE EP1INCFG ; // Endpoint 1-IN Configuration
+EXTERN __xdata _AT_(0xE612) volatile BYTE EP2CFG ; // Endpoint 2 Configuration
+EXTERN __xdata _AT_(0xE613) volatile BYTE EP4CFG ; // Endpoint 4 Configuration
+EXTERN __xdata _AT_(0xE614) volatile BYTE EP6CFG ; // Endpoint 6 Configuration
+EXTERN __xdata _AT_(0xE615) volatile BYTE EP8CFG ; // Endpoint 8 Configuration
+EXTERN __xdata _AT_(0xE618) volatile BYTE EP2FIFOCFG ; // Endpoint 2 FIFO configuration
+EXTERN __xdata _AT_(0xE619) volatile BYTE EP4FIFOCFG ; // Endpoint 4 FIFO configuration
+EXTERN __xdata _AT_(0xE61A) volatile BYTE EP6FIFOCFG ; // Endpoint 6 FIFO configuration
+EXTERN __xdata _AT_(0xE61B) volatile BYTE EP8FIFOCFG ; // Endpoint 8 FIFO configuration
+EXTERN __xdata _AT_(0xE620) volatile BYTE EP2AUTOINLENH ; // Endpoint 2 Packet Length H (IN only)
+EXTERN __xdata _AT_(0xE621) volatile BYTE EP2AUTOINLENL ; // Endpoint 2 Packet Length L (IN only)
+EXTERN __xdata _AT_(0xE622) volatile BYTE EP4AUTOINLENH ; // Endpoint 4 Packet Length H (IN only)
+EXTERN __xdata _AT_(0xE623) volatile BYTE EP4AUTOINLENL ; // Endpoint 4 Packet Length L (IN only)
+EXTERN __xdata _AT_(0xE624) volatile BYTE EP6AUTOINLENH ; // Endpoint 6 Packet Length H (IN only)
+EXTERN __xdata _AT_(0xE625) volatile BYTE EP6AUTOINLENL ; // Endpoint 6 Packet Length L (IN only)
+EXTERN __xdata _AT_(0xE626) volatile BYTE EP8AUTOINLENH ; // Endpoint 8 Packet Length H (IN only)
+EXTERN __xdata _AT_(0xE627) volatile BYTE EP8AUTOINLENL ; // Endpoint 8 Packet Length L (IN only)
+EXTERN __xdata _AT_(0xE630) volatile BYTE EP2FIFOPFH ; // EP2 Programmable Flag trigger H
+EXTERN __xdata _AT_(0xE631) volatile BYTE EP2FIFOPFL ; // EP2 Programmable Flag trigger L
+EXTERN __xdata _AT_(0xE632) volatile BYTE EP4FIFOPFH ; // EP4 Programmable Flag trigger H
+EXTERN __xdata _AT_(0xE633) volatile BYTE EP4FIFOPFL ; // EP4 Programmable Flag trigger L
+EXTERN __xdata _AT_(0xE634) volatile BYTE EP6FIFOPFH ; // EP6 Programmable Flag trigger H
+EXTERN __xdata _AT_(0xE635) volatile BYTE EP6FIFOPFL ; // EP6 Programmable Flag trigger L
+EXTERN __xdata _AT_(0xE636) volatile BYTE EP8FIFOPFH ; // EP8 Programmable Flag trigger H
+EXTERN __xdata _AT_(0xE637) volatile BYTE EP8FIFOPFL ; // EP8 Programmable Flag trigger L
+EXTERN __xdata _AT_(0xE640) volatile BYTE EP2ISOINPKTS ; // EP2 (if ISO) IN Packets per frame (1-3)
+EXTERN __xdata _AT_(0xE641) volatile BYTE EP4ISOINPKTS ; // EP4 (if ISO) IN Packets per frame (1-3)
+EXTERN __xdata _AT_(0xE642) volatile BYTE EP6ISOINPKTS ; // EP6 (if ISO) IN Packets per frame (1-3)
+EXTERN __xdata _AT_(0xE643) volatile BYTE EP8ISOINPKTS ; // EP8 (if ISO) IN Packets per frame (1-3)
+EXTERN __xdata _AT_(0xE648) volatile BYTE INPKTEND ; // Force IN Packet End
+EXTERN __xdata _AT_(0xE649) volatile BYTE OUTPKTEND ; // Force OUT Packet End
// Interrupts
-EXTERN xdata _AT_(0xE650) volatile BYTE EP2FIFOIE ; // Endpoint 2 Flag Interrupt Enable
-EXTERN xdata _AT_(0xE651) volatile BYTE EP2FIFOIRQ ; // Endpoint 2 Flag Interrupt Request
-EXTERN xdata _AT_(0xE652) volatile BYTE EP4FIFOIE ; // Endpoint 4 Flag Interrupt Enable
-EXTERN xdata _AT_(0xE653) volatile BYTE EP4FIFOIRQ ; // Endpoint 4 Flag Interrupt Request
-EXTERN xdata _AT_(0xE654) volatile BYTE EP6FIFOIE ; // Endpoint 6 Flag Interrupt Enable
-EXTERN xdata _AT_(0xE655) volatile BYTE EP6FIFOIRQ ; // Endpoint 6 Flag Interrupt Request
-EXTERN xdata _AT_(0xE656) volatile BYTE EP8FIFOIE ; // Endpoint 8 Flag Interrupt Enable
-EXTERN xdata _AT_(0xE657) volatile BYTE EP8FIFOIRQ ; // Endpoint 8 Flag Interrupt Request
-EXTERN xdata _AT_(0xE658) volatile BYTE IBNIE ; // IN-BULK-NAK Interrupt Enable
-EXTERN xdata _AT_(0xE659) volatile BYTE IBNIRQ ; // IN-BULK-NAK interrupt Request
-EXTERN xdata _AT_(0xE65A) volatile BYTE NAKIE ; // Endpoint Ping NAK interrupt Enable
-EXTERN xdata _AT_(0xE65B) volatile BYTE NAKIRQ ; // Endpoint Ping NAK interrupt Request
-EXTERN xdata _AT_(0xE65C) volatile BYTE USBIE ; // USB Int Enables
-EXTERN xdata _AT_(0xE65D) volatile BYTE USBIRQ ; // USB Interrupt Requests
-EXTERN xdata _AT_(0xE65E) volatile BYTE EPIE ; // Endpoint Interrupt Enables
-EXTERN xdata _AT_(0xE65F) volatile BYTE EPIRQ ; // Endpoint Interrupt Requests
-EXTERN xdata _AT_(0xE660) volatile BYTE GPIFIE ; // GPIF Interrupt Enable
-EXTERN xdata _AT_(0xE661) volatile BYTE GPIFIRQ ; // GPIF Interrupt Request
-EXTERN xdata _AT_(0xE662) volatile BYTE USBERRIE ; // USB Error Interrupt Enables
-EXTERN xdata _AT_(0xE663) volatile BYTE USBERRIRQ ; // USB Error Interrupt Requests
-EXTERN xdata _AT_(0xE664) volatile BYTE ERRCNTLIM ; // USB Error counter and limit
-EXTERN xdata _AT_(0xE665) volatile BYTE CLRERRCNT ; // Clear Error Counter EC[3..0]
-EXTERN xdata _AT_(0xE666) volatile BYTE INT2IVEC ; // Interupt 2 (USB) Autovector
-EXTERN xdata _AT_(0xE667) volatile BYTE INT4IVEC ; // Interupt 4 (FIFOS & GPIF) Autovector
-EXTERN xdata _AT_(0xE668) volatile BYTE INTSETUP ; // Interrupt 2&4 Setup
+EXTERN __xdata _AT_(0xE650) volatile BYTE EP2FIFOIE ; // Endpoint 2 Flag Interrupt Enable
+EXTERN __xdata _AT_(0xE651) volatile BYTE EP2FIFOIRQ ; // Endpoint 2 Flag Interrupt Request
+EXTERN __xdata _AT_(0xE652) volatile BYTE EP4FIFOIE ; // Endpoint 4 Flag Interrupt Enable
+EXTERN __xdata _AT_(0xE653) volatile BYTE EP4FIFOIRQ ; // Endpoint 4 Flag Interrupt Request
+EXTERN __xdata _AT_(0xE654) volatile BYTE EP6FIFOIE ; // Endpoint 6 Flag Interrupt Enable
+EXTERN __xdata _AT_(0xE655) volatile BYTE EP6FIFOIRQ ; // Endpoint 6 Flag Interrupt Request
+EXTERN __xdata _AT_(0xE656) volatile BYTE EP8FIFOIE ; // Endpoint 8 Flag Interrupt Enable
+EXTERN __xdata _AT_(0xE657) volatile BYTE EP8FIFOIRQ ; // Endpoint 8 Flag Interrupt Request
+EXTERN __xdata _AT_(0xE658) volatile BYTE IBNIE ; // IN-BULK-NAK Interrupt Enable
+EXTERN __xdata _AT_(0xE659) volatile BYTE IBNIRQ ; // IN-BULK-NAK interrupt Request
+EXTERN __xdata _AT_(0xE65A) volatile BYTE NAKIE ; // Endpoint Ping NAK interrupt Enable
+EXTERN __xdata _AT_(0xE65B) volatile BYTE NAKIRQ ; // Endpoint Ping NAK interrupt Request
+EXTERN __xdata _AT_(0xE65C) volatile BYTE USBIE ; // USB Int Enables
+EXTERN __xdata _AT_(0xE65D) volatile BYTE USBIRQ ; // USB Interrupt Requests
+EXTERN __xdata _AT_(0xE65E) volatile BYTE EPIE ; // Endpoint Interrupt Enables
+EXTERN __xdata _AT_(0xE65F) volatile BYTE EPIRQ ; // Endpoint Interrupt Requests
+EXTERN __xdata _AT_(0xE660) volatile BYTE GPIFIE ; // GPIF Interrupt Enable
+EXTERN __xdata _AT_(0xE661) volatile BYTE GPIFIRQ ; // GPIF Interrupt Request
+EXTERN __xdata _AT_(0xE662) volatile BYTE USBERRIE ; // USB Error Interrupt Enables
+EXTERN __xdata _AT_(0xE663) volatile BYTE USBERRIRQ ; // USB Error Interrupt Requests
+EXTERN __xdata _AT_(0xE664) volatile BYTE ERRCNTLIM ; // USB Error counter and limit
+EXTERN __xdata _AT_(0xE665) volatile BYTE CLRERRCNT ; // Clear Error Counter EC[3..0]
+EXTERN __xdata _AT_(0xE666) volatile BYTE INT2IVEC ; // Interupt 2 (USB) Autovector
+EXTERN __xdata _AT_(0xE667) volatile BYTE INT4IVEC ; // Interupt 4 (FIFOS & GPIF) Autovector
+EXTERN __xdata _AT_(0xE668) volatile BYTE INTSETUP ; // Interrupt 2&4 Setup
// Input/Output
-EXTERN xdata _AT_(0xE670) volatile BYTE PORTACFG ; // I/O PORTA Alternate Configuration
-EXTERN xdata _AT_(0xE671) volatile BYTE PORTCCFG ; // I/O PORTC Alternate Configuration
-EXTERN xdata _AT_(0xE672) volatile BYTE PORTECFG ; // I/O PORTE Alternate Configuration
-EXTERN xdata _AT_(0xE678) volatile BYTE I2CS ; // Control & Status
-EXTERN xdata _AT_(0xE679) volatile BYTE I2DAT ; // Data
-EXTERN xdata _AT_(0xE67A) volatile BYTE I2CTL ; // I2C Control
-EXTERN xdata _AT_(0xE67B) volatile BYTE XAUTODAT1 ; // Autoptr1 MOVX access
-EXTERN xdata _AT_(0xE67C) volatile BYTE XAUTODAT2 ; // Autoptr2 MOVX access
+EXTERN __xdata _AT_(0xE670) volatile BYTE PORTACFG ; // I/O PORTA Alternate Configuration
+EXTERN __xdata _AT_(0xE671) volatile BYTE PORTCCFG ; // I/O PORTC Alternate Configuration
+EXTERN __xdata _AT_(0xE672) volatile BYTE PORTECFG ; // I/O PORTE Alternate Configuration
+EXTERN __xdata _AT_(0xE678) volatile BYTE I2CS ; // Control & Status
+EXTERN __xdata _AT_(0xE679) volatile BYTE I2DAT ; // Data
+EXTERN __xdata _AT_(0xE67A) volatile BYTE I2CTL ; // I2C Control
+EXTERN __xdata _AT_(0xE67B) volatile BYTE XAUTODAT1 ; // Autoptr1 MOVX access
+EXTERN __xdata _AT_(0xE67C) volatile BYTE XAUTODAT2 ; // Autoptr2 MOVX access
#define EXTAUTODAT1 XAUTODAT1
#define EXTAUTODAT2 XAUTODAT2
// USB Control
-EXTERN xdata _AT_(0xE680) volatile BYTE USBCS ; // USB Control & Status
-EXTERN xdata _AT_(0xE681) volatile BYTE SUSPEND ; // Put chip into suspend
-EXTERN xdata _AT_(0xE682) volatile BYTE WAKEUPCS ; // Wakeup source and polarity
-EXTERN xdata _AT_(0xE683) volatile BYTE TOGCTL ; // Toggle Control
-EXTERN xdata _AT_(0xE684) volatile BYTE USBFRAMEH ; // USB Frame count H
-EXTERN xdata _AT_(0xE685) volatile BYTE USBFRAMEL ; // USB Frame count L
-EXTERN xdata _AT_(0xE686) volatile BYTE MICROFRAME ; // Microframe count, 0-7
-EXTERN xdata _AT_(0xE687) volatile BYTE FNADDR ; // USB Function address
+EXTERN __xdata _AT_(0xE680) volatile BYTE USBCS ; // USB Control & Status
+EXTERN __xdata _AT_(0xE681) volatile BYTE SUSPEND ; // Put chip into suspend
+EXTERN __xdata _AT_(0xE682) volatile BYTE WAKEUPCS ; // Wakeup source and polarity
+EXTERN __xdata _AT_(0xE683) volatile BYTE TOGCTL ; // Toggle Control
+EXTERN __xdata _AT_(0xE684) volatile BYTE USBFRAMEH ; // USB Frame count H
+EXTERN __xdata _AT_(0xE685) volatile BYTE USBFRAMEL ; // USB Frame count L
+EXTERN __xdata _AT_(0xE686) volatile BYTE MICROFRAME ; // Microframe count, 0-7
+EXTERN __xdata _AT_(0xE687) volatile BYTE FNADDR ; // USB Function address
// Endpoints
-EXTERN xdata _AT_(0xE68A) volatile BYTE EP0BCH ; // Endpoint 0 Byte Count H
-EXTERN xdata _AT_(0xE68B) volatile BYTE EP0BCL ; // Endpoint 0 Byte Count L
-EXTERN xdata _AT_(0xE68D) volatile BYTE EP1OUTBC ; // Endpoint 1 OUT Byte Count
-EXTERN xdata _AT_(0xE68F) volatile BYTE EP1INBC ; // Endpoint 1 IN Byte Count
-EXTERN xdata _AT_(0xE690) volatile BYTE EP2BCH ; // Endpoint 2 Byte Count H
-EXTERN xdata _AT_(0xE691) volatile BYTE EP2BCL ; // Endpoint 2 Byte Count L
-EXTERN xdata _AT_(0xE694) volatile BYTE EP4BCH ; // Endpoint 4 Byte Count H
-EXTERN xdata _AT_(0xE695) volatile BYTE EP4BCL ; // Endpoint 4 Byte Count L
-EXTERN xdata _AT_(0xE698) volatile BYTE EP6BCH ; // Endpoint 6 Byte Count H
-EXTERN xdata _AT_(0xE699) volatile BYTE EP6BCL ; // Endpoint 6 Byte Count L
-EXTERN xdata _AT_(0xE69C) volatile BYTE EP8BCH ; // Endpoint 8 Byte Count H
-EXTERN xdata _AT_(0xE69D) volatile BYTE EP8BCL ; // Endpoint 8 Byte Count L
-EXTERN xdata _AT_(0xE6A0) volatile BYTE EP0CS ; // Endpoint Control and Status
-EXTERN xdata _AT_(0xE6A1) volatile BYTE EP1OUTCS ; // Endpoint 1 OUT Control and Status
-EXTERN xdata _AT_(0xE6A2) volatile BYTE EP1INCS ; // Endpoint 1 IN Control and Status
-EXTERN xdata _AT_(0xE6A3) volatile BYTE EP2CS ; // Endpoint 2 Control and Status
-EXTERN xdata _AT_(0xE6A4) volatile BYTE EP4CS ; // Endpoint 4 Control and Status
-EXTERN xdata _AT_(0xE6A5) volatile BYTE EP6CS ; // Endpoint 6 Control and Status
-EXTERN xdata _AT_(0xE6A6) volatile BYTE EP8CS ; // Endpoint 8 Control and Status
-EXTERN xdata _AT_(0xE6A7) volatile BYTE EP2FIFOFLGS ; // Endpoint 2 Flags
-EXTERN xdata _AT_(0xE6A8) volatile BYTE EP4FIFOFLGS ; // Endpoint 4 Flags
-EXTERN xdata _AT_(0xE6A9) volatile BYTE EP6FIFOFLGS ; // Endpoint 6 Flags
-EXTERN xdata _AT_(0xE6AA) volatile BYTE EP8FIFOFLGS ; // Endpoint 8 Flags
-EXTERN xdata _AT_(0xE6AB) volatile BYTE EP2FIFOBCH ; // EP2 FIFO total byte count H
-EXTERN xdata _AT_(0xE6AC) volatile BYTE EP2FIFOBCL ; // EP2 FIFO total byte count L
-EXTERN xdata _AT_(0xE6AD) volatile BYTE EP4FIFOBCH ; // EP4 FIFO total byte count H
-EXTERN xdata _AT_(0xE6AE) volatile BYTE EP4FIFOBCL ; // EP4 FIFO total byte count L
-EXTERN xdata _AT_(0xE6AF) volatile BYTE EP6FIFOBCH ; // EP6 FIFO total byte count H
-EXTERN xdata _AT_(0xE6B0) volatile BYTE EP6FIFOBCL ; // EP6 FIFO total byte count L
-EXTERN xdata _AT_(0xE6B1) volatile BYTE EP8FIFOBCH ; // EP8 FIFO total byte count H
-EXTERN xdata _AT_(0xE6B2) volatile BYTE EP8FIFOBCL ; // EP8 FIFO total byte count L
-EXTERN xdata _AT_(0xE6B3) volatile BYTE SUDPTRH ; // Setup Data Pointer high address byte
-EXTERN xdata _AT_(0xE6B4) volatile BYTE SUDPTRL ; // Setup Data Pointer low address byte
-EXTERN xdata _AT_(0xE6B5) volatile BYTE SUDPTRCTL ; // Setup Data Pointer Auto Mode
-EXTERN xdata _AT_(0xE6B8) volatile BYTE SETUPDAT[8] ; // 8 bytes of SETUP data
+EXTERN __xdata _AT_(0xE68A) volatile BYTE EP0BCH ; // Endpoint 0 Byte Count H
+EXTERN __xdata _AT_(0xE68B) volatile BYTE EP0BCL ; // Endpoint 0 Byte Count L
+EXTERN __xdata _AT_(0xE68D) volatile BYTE EP1OUTBC ; // Endpoint 1 OUT Byte Count
+EXTERN __xdata _AT_(0xE68F) volatile BYTE EP1INBC ; // Endpoint 1 IN Byte Count
+EXTERN __xdata _AT_(0xE690) volatile BYTE EP2BCH ; // Endpoint 2 Byte Count H
+EXTERN __xdata _AT_(0xE691) volatile BYTE EP2BCL ; // Endpoint 2 Byte Count L
+EXTERN __xdata _AT_(0xE694) volatile BYTE EP4BCH ; // Endpoint 4 Byte Count H
+EXTERN __xdata _AT_(0xE695) volatile BYTE EP4BCL ; // Endpoint 4 Byte Count L
+EXTERN __xdata _AT_(0xE698) volatile BYTE EP6BCH ; // Endpoint 6 Byte Count H
+EXTERN __xdata _AT_(0xE699) volatile BYTE EP6BCL ; // Endpoint 6 Byte Count L
+EXTERN __xdata _AT_(0xE69C) volatile BYTE EP8BCH ; // Endpoint 8 Byte Count H
+EXTERN __xdata _AT_(0xE69D) volatile BYTE EP8BCL ; // Endpoint 8 Byte Count L
+EXTERN __xdata _AT_(0xE6A0) volatile BYTE EP0CS ; // Endpoint Control and Status
+EXTERN __xdata _AT_(0xE6A1) volatile BYTE EP1OUTCS ; // Endpoint 1 OUT Control and Status
+EXTERN __xdata _AT_(0xE6A2) volatile BYTE EP1INCS ; // Endpoint 1 IN Control and Status
+EXTERN __xdata _AT_(0xE6A3) volatile BYTE EP2CS ; // Endpoint 2 Control and Status
+EXTERN __xdata _AT_(0xE6A4) volatile BYTE EP4CS ; // Endpoint 4 Control and Status
+EXTERN __xdata _AT_(0xE6A5) volatile BYTE EP6CS ; // Endpoint 6 Control and Status
+EXTERN __xdata _AT_(0xE6A6) volatile BYTE EP8CS ; // Endpoint 8 Control and Status
+EXTERN __xdata _AT_(0xE6A7) volatile BYTE EP2FIFOFLGS ; // Endpoint 2 Flags
+EXTERN __xdata _AT_(0xE6A8) volatile BYTE EP4FIFOFLGS ; // Endpoint 4 Flags
+EXTERN __xdata _AT_(0xE6A9) volatile BYTE EP6FIFOFLGS ; // Endpoint 6 Flags
+EXTERN __xdata _AT_(0xE6AA) volatile BYTE EP8FIFOFLGS ; // Endpoint 8 Flags
+EXTERN __xdata _AT_(0xE6AB) volatile BYTE EP2FIFOBCH ; // EP2 FIFO total byte count H
+EXTERN __xdata _AT_(0xE6AC) volatile BYTE EP2FIFOBCL ; // EP2 FIFO total byte count L
+EXTERN __xdata _AT_(0xE6AD) volatile BYTE EP4FIFOBCH ; // EP4 FIFO total byte count H
+EXTERN __xdata _AT_(0xE6AE) volatile BYTE EP4FIFOBCL ; // EP4 FIFO total byte count L
+EXTERN __xdata _AT_(0xE6AF) volatile BYTE EP6FIFOBCH ; // EP6 FIFO total byte count H
+EXTERN __xdata _AT_(0xE6B0) volatile BYTE EP6FIFOBCL ; // EP6 FIFO total byte count L
+EXTERN __xdata _AT_(0xE6B1) volatile BYTE EP8FIFOBCH ; // EP8 FIFO total byte count H
+EXTERN __xdata _AT_(0xE6B2) volatile BYTE EP8FIFOBCL ; // EP8 FIFO total byte count L
+EXTERN __xdata _AT_(0xE6B3) volatile BYTE SUDPTRH ; // Setup Data Pointer high address byte
+EXTERN __xdata _AT_(0xE6B4) volatile BYTE SUDPTRL ; // Setup Data Pointer low address byte
+EXTERN __xdata _AT_(0xE6B5) volatile BYTE SUDPTRCTL ; // Setup Data Pointer Auto Mode
+EXTERN __xdata _AT_(0xE6B8) volatile BYTE SETUPDAT[8] ; // 8 bytes of SETUP data
// GPIF
-EXTERN xdata _AT_(0xE6C0) volatile BYTE GPIFWFSELECT ; // Waveform Selector
-EXTERN xdata _AT_(0xE6C1) volatile BYTE GPIFIDLECS ; // GPIF Done, GPIF IDLE drive mode
-EXTERN xdata _AT_(0xE6C2) volatile BYTE GPIFIDLECTL ; // Inactive Bus, CTL states
-EXTERN xdata _AT_(0xE6C3) volatile BYTE GPIFCTLCFG ; // CTL OUT pin drive
-EXTERN xdata _AT_(0xE6C4) volatile BYTE GPIFADRH ; // GPIF Address H
-EXTERN xdata _AT_(0xE6C5) volatile BYTE GPIFADRL ; // GPIF Address L
-
-EXTERN xdata _AT_(0xE6CE) volatile BYTE GPIFTCB3 ; // GPIF Transaction Count Byte 3
-EXTERN xdata _AT_(0xE6CF) volatile BYTE GPIFTCB2 ; // GPIF Transaction Count Byte 2
-EXTERN xdata _AT_(0xE6D0) volatile BYTE GPIFTCB1 ; // GPIF Transaction Count Byte 1
-EXTERN xdata _AT_(0xE6D1) volatile BYTE GPIFTCB0 ; // GPIF Transaction Count Byte 0
+EXTERN __xdata _AT_(0xE6C0) volatile BYTE GPIFWFSELECT ; // Waveform Selector
+EXTERN __xdata _AT_(0xE6C1) volatile BYTE GPIFIDLECS ; // GPIF Done, GPIF IDLE drive mode
+EXTERN __xdata _AT_(0xE6C2) volatile BYTE GPIFIDLECTL ; // Inactive Bus, CTL states
+EXTERN __xdata _AT_(0xE6C3) volatile BYTE GPIFCTLCFG ; // CTL OUT pin drive
+EXTERN __xdata _AT_(0xE6C4) volatile BYTE GPIFADRH ; // GPIF Address H
+EXTERN __xdata _AT_(0xE6C5) volatile BYTE GPIFADRL ; // GPIF Address L
+
+EXTERN __xdata _AT_(0xE6CE) volatile BYTE GPIFTCB3 ; // GPIF Transaction Count Byte 3
+EXTERN __xdata _AT_(0xE6CF) volatile BYTE GPIFTCB2 ; // GPIF Transaction Count Byte 2
+EXTERN __xdata _AT_(0xE6D0) volatile BYTE GPIFTCB1 ; // GPIF Transaction Count Byte 1
+EXTERN __xdata _AT_(0xE6D1) volatile BYTE GPIFTCB0 ; // GPIF Transaction Count Byte 0
#define EP2GPIFTCH GPIFTCB1 // these are here for backwards compatibility
#define EP2GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
@@ -238,68 +238,68 @@
#define EP8GPIFTCH GPIFTCB1 // these are here for backwards compatibility
#define EP8GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)
-// EXTERN xdata volatile BYTE EP2GPIFTCH _AT_ 0xE6D0; // EP2 GPIF Transaction Count High
-// EXTERN xdata volatile BYTE EP2GPIFTCL _AT_ 0xE6D1; // EP2 GPIF Transaction Count Low
-EXTERN xdata _AT_(0xE6D2) volatile BYTE EP2GPIFFLGSEL ; // EP2 GPIF Flag select
-EXTERN xdata _AT_(0xE6D3) volatile BYTE EP2GPIFPFSTOP ; // Stop GPIF EP2 transaction on prog. flag
-EXTERN xdata _AT_(0xE6D4) volatile BYTE EP2GPIFTRIG ; // EP2 FIFO Trigger
-// EXTERN xdata volatile BYTE EP4GPIFTCH _AT_ 0xE6D8; // EP4 GPIF Transaction Count High
-// EXTERN xdata volatile BYTE EP4GPIFTCL _AT_ 0xE6D9; // EP4 GPIF Transactionr Count Low
-EXTERN xdata _AT_(0xE6DA) volatile BYTE EP4GPIFFLGSEL ; // EP4 GPIF Flag select
-EXTERN xdata _AT_(0xE6DB) volatile BYTE EP4GPIFPFSTOP ; // Stop GPIF EP4 transaction on prog. flag
-EXTERN xdata _AT_(0xE6DC) volatile BYTE EP4GPIFTRIG ; // EP4 FIFO Trigger
-// EXTERN xdata volatile BYTE EP6GPIFTCH _AT_ 0xE6E0; // EP6 GPIF Transaction Count High
-// EXTERN xdata volatile BYTE EP6GPIFTCL _AT_ 0xE6E1; // EP6 GPIF Transaction Count Low
-EXTERN xdata _AT_(0xE6E2) volatile BYTE EP6GPIFFLGSEL ; // EP6 GPIF Flag select
-EXTERN xdata _AT_(0xE6E3) volatile BYTE EP6GPIFPFSTOP ; // Stop GPIF EP6 transaction on prog. flag
-EXTERN xdata _AT_(0xE6E4) volatile BYTE EP6GPIFTRIG ; // EP6 FIFO Trigger
-// EXTERN xdata volatile BYTE EP8GPIFTCH _AT_ 0xE6E8; // EP8 GPIF Transaction Count High
-// EXTERN xdata volatile BYTE EP8GPIFTCL _AT_ 0xE6E9; // EP8GPIF Transaction Count Low
-EXTERN xdata _AT_(0xE6EA) volatile BYTE EP8GPIFFLGSEL ; // EP8 GPIF Flag select
-EXTERN xdata _AT_(0xE6EB) volatile BYTE EP8GPIFPFSTOP ; // Stop GPIF EP8 transaction on prog. flag
-EXTERN xdata _AT_(0xE6EC) volatile BYTE EP8GPIFTRIG ; // EP8 FIFO Trigger
-EXTERN xdata _AT_(0xE6F0) volatile BYTE XGPIFSGLDATH ; // GPIF Data H (16-bit mode only)
-EXTERN xdata _AT_(0xE6F1) volatile BYTE XGPIFSGLDATLX ; // Read/Write GPIF Data L & trigger transac
-EXTERN xdata _AT_(0xE6F2) volatile BYTE XGPIFSGLDATLNOX ; // Read GPIF Data L, no transac trigger
-EXTERN xdata _AT_(0xE6F3) volatile BYTE GPIFREADYCFG ; // Internal RDY,Sync/Async, RDY5CFG
-EXTERN xdata _AT_(0xE6F4) volatile BYTE GPIFREADYSTAT ; // RDY pin states
-EXTERN xdata _AT_(0xE6F5) volatile BYTE GPIFABORT ; // Abort GPIF cycles
+// EXTERN __xdata volatile BYTE EP2GPIFTCH _AT_ 0xE6D0; // EP2 GPIF Transaction Count High
+// EXTERN __xdata volatile BYTE EP2GPIFTCL _AT_ 0xE6D1; // EP2 GPIF Transaction Count Low
+EXTERN __xdata _AT_(0xE6D2) volatile BYTE EP2GPIFFLGSEL ; // EP2 GPIF Flag select
+EXTERN __xdata _AT_(0xE6D3) volatile BYTE EP2GPIFPFSTOP ; // Stop GPIF EP2 transaction on prog. flag
+EXTERN __xdata _AT_(0xE6D4) volatile BYTE EP2GPIFTRIG ; // EP2 FIFO Trigger
+// EXTERN __xdata volatile BYTE EP4GPIFTCH _AT_ 0xE6D8; // EP4 GPIF Transaction Count High
+// EXTERN __xdata volatile BYTE EP4GPIFTCL _AT_ 0xE6D9; // EP4 GPIF Transactionr Count Low
+EXTERN __xdata _AT_(0xE6DA) volatile BYTE EP4GPIFFLGSEL ; // EP4 GPIF Flag select
+EXTERN __xdata _AT_(0xE6DB) volatile BYTE EP4GPIFPFSTOP ; // Stop GPIF EP4 transaction on prog. flag
+EXTERN __xdata _AT_(0xE6DC) volatile BYTE EP4GPIFTRIG ; // EP4 FIFO Trigger
+// EXTERN __xdata volatile BYTE EP6GPIFTCH _AT_ 0xE6E0; // EP6 GPIF Transaction Count High
+// EXTERN __xdata volatile BYTE EP6GPIFTCL _AT_ 0xE6E1; // EP6 GPIF Transaction Count Low
+EXTERN __xdata _AT_(0xE6E2) volatile BYTE EP6GPIFFLGSEL ; // EP6 GPIF Flag select
+EXTERN __xdata _AT_(0xE6E3) volatile BYTE EP6GPIFPFSTOP ; // Stop GPIF EP6 transaction on prog. flag
+EXTERN __xdata _AT_(0xE6E4) volatile BYTE EP6GPIFTRIG ; // EP6 FIFO Trigger
+// EXTERN __xdata volatile BYTE EP8GPIFTCH _AT_ 0xE6E8; // EP8 GPIF Transaction Count High
+// EXTERN __xdata volatile BYTE EP8GPIFTCL _AT_ 0xE6E9; // EP8GPIF Transaction Count Low
+EXTERN __xdata _AT_(0xE6EA) volatile BYTE EP8GPIFFLGSEL ; // EP8 GPIF Flag select
+EXTERN __xdata _AT_(0xE6EB) volatile BYTE EP8GPIFPFSTOP ; // Stop GPIF EP8 transaction on prog. flag
+EXTERN __xdata _AT_(0xE6EC) volatile BYTE EP8GPIFTRIG ; // EP8 FIFO Trigger
+EXTERN __xdata _AT_(0xE6F0) volatile BYTE XGPIFSGLDATH ; // GPIF Data H (16-bit mode only)
+EXTERN __xdata _AT_(0xE6F1) volatile BYTE XGPIFSGLDATLX ; // Read/Write GPIF Data L & trigger transac
+EXTERN __xdata _AT_(0xE6F2) volatile BYTE XGPIFSGLDATLNOX ; // Read GPIF Data L, no transac trigger
+EXTERN __xdata _AT_(0xE6F3) volatile BYTE GPIFREADYCFG ; // Internal RDY,Sync/Async, RDY5CFG
+EXTERN __xdata _AT_(0xE6F4) volatile BYTE GPIFREADYSTAT ; // RDY pin states
+EXTERN __xdata _AT_(0xE6F5) volatile BYTE GPIFABORT ; // Abort GPIF cycles
// UDMA
-EXTERN xdata _AT_(0xE6C6) volatile BYTE FLOWSTATE ; //Defines GPIF flow state
-EXTERN xdata _AT_(0xE6C7) volatile BYTE FLOWLOGIC ; //Defines flow/hold decision criteria
-EXTERN xdata _AT_(0xE6C8) volatile BYTE FLOWEQ0CTL ; //CTL states during active flow state
-EXTERN xdata _AT_(0xE6C9) volatile BYTE FLOWEQ1CTL ; //CTL states during hold flow state
-EXTERN xdata _AT_(0xE6CA) volatile BYTE FLOWHOLDOFF ;
-EXTERN xdata _AT_(0xE6CB) volatile BYTE FLOWSTB ; //CTL/RDY Signal to use as master data strobe
-EXTERN xdata _AT_(0xE6CC) volatile BYTE FLOWSTBEDGE ; //Defines active master strobe edge
-EXTERN xdata _AT_(0xE6CD) volatile BYTE FLOWSTBHPERIOD ; //Half Period of output master strobe
-EXTERN xdata _AT_(0xE60C) volatile BYTE GPIFHOLDAMOUNT ; //Data delay shift
-EXTERN xdata _AT_(0xE67D) volatile BYTE UDMACRCH ; //CRC Upper byte
-EXTERN xdata _AT_(0xE67E) volatile BYTE UDMACRCL ; //CRC Lower byte
-EXTERN xdata _AT_(0xE67F) volatile BYTE UDMACRCQUAL ; //UDMA In only, host terminated use only
+EXTERN __xdata _AT_(0xE6C6) volatile BYTE FLOWSTATE ; //Defines GPIF flow state
+EXTERN __xdata _AT_(0xE6C7) volatile BYTE FLOWLOGIC ; //Defines flow/hold decision criteria
+EXTERN __xdata _AT_(0xE6C8) volatile BYTE FLOWEQ0CTL ; //CTL states during active flow state
+EXTERN __xdata _AT_(0xE6C9) volatile BYTE FLOWEQ1CTL ; //CTL states during hold flow state
+EXTERN __xdata _AT_(0xE6CA) volatile BYTE FLOWHOLDOFF ;
+EXTERN __xdata _AT_(0xE6CB) volatile BYTE FLOWSTB ; //CTL/RDY Signal to use as master data strobe
+EXTERN __xdata _AT_(0xE6CC) volatile BYTE FLOWSTBEDGE ; //Defines active master strobe edge
+EXTERN __xdata _AT_(0xE6CD) volatile BYTE FLOWSTBHPERIOD ; //Half Period of output master strobe
+EXTERN __xdata _AT_(0xE60C) volatile BYTE GPIFHOLDAMOUNT ; //Data delay shift
+EXTERN __xdata _AT_(0xE67D) volatile BYTE UDMACRCH ; //CRC Upper byte
+EXTERN __xdata _AT_(0xE67E) volatile BYTE UDMACRCL ; //CRC Lower byte
+EXTERN __xdata _AT_(0xE67F) volatile BYTE UDMACRCQUAL ; //UDMA In only, host terminated use only
// Debug/Test
-EXTERN xdata _AT_(0xE6F8) volatile BYTE DBUG ; // Debug
-EXTERN xdata _AT_(0xE6F9) volatile BYTE TESTCFG ; // Test configuration
-EXTERN xdata _AT_(0xE6FA) volatile BYTE USBTEST ; // USB Test Modes
-EXTERN xdata _AT_(0xE6FB) volatile BYTE CT1 ; // Chirp Test--Override
-EXTERN xdata _AT_(0xE6FC) volatile BYTE CT2 ; // Chirp Test--FSM
-EXTERN xdata _AT_(0xE6FD) volatile BYTE CT3 ; // Chirp Test--Control Signals
-EXTERN xdata _AT_(0xE6FE) volatile BYTE CT4 ; // Chirp Test--Inputs
+EXTERN __xdata _AT_(0xE6F8) volatile BYTE DBUG ; // Debug
+EXTERN __xdata _AT_(0xE6F9) volatile BYTE TESTCFG ; // Test configuration
+EXTERN __xdata _AT_(0xE6FA) volatile BYTE USBTEST ; // USB Test Modes
+EXTERN __xdata _AT_(0xE6FB) volatile BYTE CT1 ; // Chirp Test--Override
+EXTERN __xdata _AT_(0xE6FC) volatile BYTE CT2 ; // Chirp Test--FSM
+EXTERN __xdata _AT_(0xE6FD) volatile BYTE CT3 ; // Chirp Test--Control Signals
+EXTERN __xdata _AT_(0xE6FE) volatile BYTE CT4 ; // Chirp Test--Inputs
// Endpoint Buffers
-EXTERN xdata _AT_(0xE740) volatile BYTE EP0BUF[64] ; // EP0 IN-OUT buffer
-EXTERN xdata _AT_(0xE780) volatile BYTE EP1OUTBUF[64] ; // EP1-OUT buffer
-EXTERN xdata _AT_(0xE7C0) volatile BYTE EP1INBUF[64] ; // EP1-IN buffer
-EXTERN xdata _AT_(0xF000) volatile BYTE EP2FIFOBUF[1024] ; // 512/1024-byte EP2 buffer (IN or OUT)
-EXTERN xdata _AT_(0xF400) volatile BYTE EP4FIFOBUF[1024] ; // 512 byte EP4 buffer (IN or OUT)
-EXTERN xdata _AT_(0xF800) volatile BYTE EP6FIFOBUF[1024] ; // 512/1024-byte EP6 buffer (IN or OUT)
-EXTERN xdata _AT_(0xFC00) volatile BYTE EP8FIFOBUF[1024] ; // 512 byte EP8 buffer (IN or OUT)
+EXTERN __xdata _AT_(0xE740) volatile BYTE EP0BUF[64] ; // EP0 IN-OUT buffer
+EXTERN __xdata _AT_(0xE780) volatile BYTE EP1OUTBUF[64] ; // EP1-OUT buffer
+EXTERN __xdata _AT_(0xE7C0) volatile BYTE EP1INBUF[64] ; // EP1-IN buffer
+EXTERN __xdata _AT_(0xF000) volatile BYTE EP2FIFOBUF[1024] ; // 512/1024-byte EP2 buffer (IN or OUT)
+EXTERN __xdata _AT_(0xF400) volatile BYTE EP4FIFOBUF[1024] ; // 512 byte EP4 buffer (IN or OUT)
+EXTERN __xdata _AT_(0xF800) volatile BYTE EP6FIFOBUF[1024] ; // 512/1024-byte EP6 buffer (IN or OUT)
+EXTERN __xdata _AT_(0xFC00) volatile BYTE EP8FIFOBUF[1024] ; // 512 byte EP8 buffer (IN or OUT)
#undef EXTERN
#undef _AT_
@@ -312,201 +312,201 @@
"ezregs.inc" which includes the same basic information for assembly inclusion.
-----------------------------------------------------------------------------*/
-sfr at 0x80 IOA;
-sfr at 0x81 SP;
-sfr at 0x82 DPL;
-sfr at 0x83 DPH;
-sfr at 0x84 DPL1;
-sfr at 0x85 DPH1;
-sfr at 0x86 DPS;
+__sfr __at 0x80 IOA;
+__sfr __at 0x81 SP;
+__sfr __at 0x82 DPL;
+__sfr __at 0x83 DPH;
+__sfr __at 0x84 DPL1;
+__sfr __at 0x85 DPH1;
+__sfr __at 0x86 DPS;
/* DPS */
- sbit at 0x86+0 SEL;
-sfr at 0x87 PCON; /* PCON */
+ __sbit __at 0x86+0 SEL;
+__sfr __at 0x87 PCON; /* PCON */
//sbit IDLE = 0x87+0;
//sbit STOP = 0x87+1;
//sbit GF0 = 0x87+2;
//sbit GF1 = 0x87+3;
//sbit SMOD0 = 0x87+7;
-sfr at 0x88 TCON;
+__sfr __at 0x88 TCON;
/* TCON */
- sbit at 0x88+0 IT0;
- sbit at 0x88+1 IE0;
- sbit at 0x88+2 IT1;
- sbit at 0x88+3 IE1;
- sbit at 0x88+4 TR0;
- sbit at 0x88+5 TF0;
- sbit at 0x88+6 TR1;
- sbit at 0x88+7 TF1;
-sfr at 0x89 TMOD;
+ __sbit __at 0x88+0 IT0;
+ __sbit __at 0x88+1 IE0;
+ __sbit __at 0x88+2 IT1;
+ __sbit __at 0x88+3 IE1;
+ __sbit __at 0x88+4 TR0;
+ __sbit __at 0x88+5 TF0;
+ __sbit __at 0x88+6 TR1;
+ __sbit __at 0x88+7 TF1;
+__sfr __at 0x89 TMOD;
/* TMOD */
- //sbit M00 = 0x89+0;
- //sbit M10 = 0x89+1;
- //sbit CT0 = 0x89+2;
- //sbit GATE0 = 0x89+3;
- //sbit M01 = 0x89+4;
- //sbit M11 = 0x89+5;
- //sbit CT1 = 0x89+6;
- //sbit GATE1 = 0x89+7;
-sfr at 0x8A TL0;
-sfr at 0x8B TL1;
-sfr at 0x8C TH0;
-sfr at 0x8D TH1;
-sfr at 0x8E CKCON;
+ //__sbit M00 = 0x89+0;
+ //__sbit M10 = 0x89+1;
+ //__sbit CT0 = 0x89+2;
+ //__sbit GATE0 = 0x89+3;
+ //__sbit M01 = 0x89+4;
+ //__sbit M11 = 0x89+5;
+ //__sbit CT1 = 0x89+6;
+ //__sbit GATE1 = 0x89+7;
+__sfr __at 0x8A TL0;
+__sfr __at 0x8B TL1;
+__sfr __at 0x8C TH0;
+__sfr __at 0x8D TH1;
+__sfr __at 0x8E CKCON;
/* CKCON */
- //sbit MD0 = 0x89+0;
- //sbit MD1 = 0x89+1;
- //sbit MD2 = 0x89+2;
- //sbit T0M = 0x89+3;
- //sbit T1M = 0x89+4;
- //sbit T2M = 0x89+5;
-// sfr at 0x8F SPC_FNC; // Was WRS in Reg320
+ //__sbit MD0 = 0x89+0;
+ //__sbit MD1 = 0x89+1;
+ //__sbit MD2 = 0x89+2;
+ //__sbit T0M = 0x89+3;
+ //__sbit T1M = 0x89+4;
+ //__sbit T2M = 0x89+5;
+// __sfr __at 0x8F SPC_FNC; // Was WRS in Reg320
/* CKCON */
- //sbit WRS = 0x8F+0;
-sfr at 0x90 IOB;
-sfr at 0x91 EXIF; // EXIF Bit Values differ from Reg320
+ //__sbit WRS = 0x8F+0;
+__sfr __at 0x90 IOB;
+__sfr __at 0x91 EXIF; // EXIF Bit Values differ from Reg320
/* EXIF */
- //sbit USBINT = 0x91+4;
- //sbit I2CINT = 0x91+5;
- //sbit IE4 = 0x91+6;
- //sbit IE5 = 0x91+7;
-sfr at 0x92 MPAGE;
-sfr at 0x98 SCON0;
+ //__sbit USBINT = 0x91+4;
+ //__sbit I2CINT = 0x91+5;
+ //__sbit IE4 = 0x91+6;
+ //__sbit IE5 = 0x91+7;
+__sfr __at 0x92 MPAGE;
+__sfr __at 0x98 SCON0;
/* SCON0 */
- sbit at 0x98+0 RI;
- sbit at 0x98+1 TI;
- sbit at 0x98+2 RB8;
- sbit at 0x98+3 TB8;
- sbit at 0x98+4 REN;
- sbit at 0x98+5 SM2;
- sbit at 0x98+6 SM1;
- sbit at 0x98+7 SM0;
-sfr at 0x99 SBUF0;
-
-sfr at 0x9A APTR1H;
-sfr at 0x9B APTR1L;
-sfr at 0x9C AUTODAT1;
-sfr at 0x9D AUTOPTRH2;
-sfr at 0x9E AUTOPTRL2;
-sfr at 0x9F AUTODAT2;
-sfr at 0xA0 IOC;
-sfr at 0xA1 INT2CLR;
-sfr at 0xA2 INT4CLR;
+ __sbit __at 0x98+0 RI;
+ __sbit __at 0x98+1 TI;
+ __sbit __at 0x98+2 RB8;
+ __sbit __at 0x98+3 TB8;
+ __sbit __at 0x98+4 REN;
+ __sbit __at 0x98+5 SM2;
+ __sbit __at 0x98+6 SM1;
+ __sbit __at 0x98+7 SM0;
+__sfr __at 0x99 SBUF0;
+
+__sfr __at 0x9A APTR1H;
+__sfr __at 0x9B APTR1L;
+__sfr __at 0x9C AUTODAT1;
+__sfr __at 0x9D AUTOPTRH2;
+__sfr __at 0x9E AUTOPTRL2;
+__sfr __at 0x9F AUTODAT2;
+__sfr __at 0xA0 IOC;
+__sfr __at 0xA1 INT2CLR;
+__sfr __at 0xA2 INT4CLR;
#define AUTOPTRH1 APTR1H
#define AUTOPTRL1 APTR1L
-sfr at 0xA8 IE;
+__sfr __at 0xA8 IE;
/* IE */
- sbit at 0xA8+0 EX0;
- sbit at 0xA8+1 ET0;
- sbit at 0xA8+2 EX1;
- sbit at 0xA8+3 ET1;
- sbit at 0xA8+4 ES0;
- sbit at 0xA8+5 ET2;
- sbit at 0xA8+6 ES1;
- sbit at 0xA8+7 EA;
+ __sbit __at 0xA8+0 EX0;
+ __sbit __at 0xA8+1 ET0;
+ __sbit __at 0xA8+2 EX1;
+ __sbit __at 0xA8+3 ET1;
+ __sbit __at 0xA8+4 ES0;
+ __sbit __at 0xA8+5 ET2;
+ __sbit __at 0xA8+6 ES1;
+ __sbit __at 0xA8+7 EA;
-sfr at 0xAA EP2468STAT;
+__sfr __at 0xAA EP2468STAT;
/* EP2468STAT */
- //sbit EP2E = 0xAA+0;
- //sbit EP2F = 0xAA+1;
- //sbit EP4E = 0xAA+2;
- //sbit EP4F = 0xAA+3;
- //sbit EP6E = 0xAA+4;
- //sbit EP6F = 0xAA+5;
- //sbit EP8E = 0xAA+6;
- //sbit EP8F = 0xAA+7;
-
-sfr at 0xAB EP24FIFOFLGS;
-sfr at 0xAC EP68FIFOFLGS;
-sfr at 0xAF AUTOPTRSETUP;
+ //__sbit EP2E = 0xAA+0;
+ //__sbit EP2F = 0xAA+1;
+ //__sbit EP4E = 0xAA+2;
+ //__sbit EP4F = 0xAA+3;
+ //__sbit EP6E = 0xAA+4;
+ //__sbit EP6F = 0xAA+5;
+ //__sbit EP8E = 0xAA+6;
+ //__sbit EP8F = 0xAA+7;
+
+__sfr __at 0xAB EP24FIFOFLGS;
+__sfr __at 0xAC EP68FIFOFLGS;
+__sfr __at 0xAF AUTOPTRSETUP;
/* AUTOPTRSETUP */
- // sbit EXTACC = 0xAF+0;
- // sbit APTR1FZ = 0xAF+1;
- // sbit APTR2FZ = 0xAF+2;
-
-sfr at 0xB0 IOD;
-sfr at 0xB1 IOE;
-sfr at 0xB2 OEA;
-sfr at 0xB3 OEB;
-sfr at 0xB4 OEC;
-sfr at 0xB5 OED;
-sfr at 0xB6 OEE;
+ // __sbit EXTACC = 0xAF+0;
+ // __sbit APTR1FZ = 0xAF+1;
+ // __sbit APTR2FZ = 0xAF+2;
+
+__sfr __at 0xB0 IOD;
+__sfr __at 0xB1 IOE;
+__sfr __at 0xB2 OEA;
+__sfr __at 0xB3 OEB;
+__sfr __at 0xB4 OEC;
+__sfr __at 0xB5 OED;
+__sfr __at 0xB6 OEE;
-sfr at 0xB8 IP;
+__sfr __at 0xB8 IP;
/* IP */
- sbit at 0xB8+0 PX0;
- sbit at 0xB8+1 PT0;
- sbit at 0xB8+2 PX1;
- sbit at 0xB8+3 PT1;
- sbit at 0xB8+4 PS0;
- sbit at 0xB8+5 PT2;
- sbit at 0xB8+6 PS1;
+ __sbit __at 0xB8+0 PX0;
+ __sbit __at 0xB8+1 PT0;
+ __sbit __at 0xB8+2 PX1;
+ __sbit __at 0xB8+3 PT1;
+ __sbit __at 0xB8+4 PS0;
+ __sbit __at 0xB8+5 PT2;
+ __sbit __at 0xB8+6 PS1;
-sfr at 0xBA EP01STAT;
-sfr at 0xBB GPIFTRIG;
+__sfr __at 0xBA EP01STAT;
+__sfr __at 0xBB GPIFTRIG;
-sfr at 0xBD GPIFSGLDATH;
-sfr at 0xBE GPIFSGLDATLX;
-sfr at 0xBF GPIFSGLDATLNOX;
+__sfr __at 0xBD GPIFSGLDATH;
+__sfr __at 0xBE GPIFSGLDATLX;
+__sfr __at 0xBF GPIFSGLDATLNOX;
-sfr at 0xC0 SCON1;
+__sfr __at 0xC0 SCON1;
/* SCON1 */
- sbit at 0xC0+0 RI1;
- sbit at 0xC0+1 TI1;
- sbit at 0xC0+2 RB81;
- sbit at 0xC0+3 TB81;
- sbit at 0xC0+4 REN1;
- sbit at 0xC0+5 SM21;
- sbit at 0xC0+6 SM11;
- sbit at 0xC0+7 SM01;
-sfr at 0xC1 SBUF1;
-sfr at 0xC8 T2CON;
+ __sbit __at 0xC0+0 RI1;
+ __sbit __at 0xC0+1 TI1;
+ __sbit __at 0xC0+2 RB81;
+ __sbit __at 0xC0+3 TB81;
+ __sbit __at 0xC0+4 REN1;
+ __sbit __at 0xC0+5 SM21;
+ __sbit __at 0xC0+6 SM11;
+ __sbit __at 0xC0+7 SM01;
+__sfr __at 0xC1 SBUF1;
+__sfr __at 0xC8 T2CON;
/* T2CON */
- sbit at 0xC8+0 CP_RL2;
- sbit at 0xC8+1 C_T2;
- sbit at 0xC8+2 TR2;
- sbit at 0xC8+3 EXEN2;
- sbit at 0xC8+4 TCLK;
- sbit at 0xC8+5 RCLK;
- sbit at 0xC8+6 EXF2;
- sbit at 0xC8+7 TF2;
-sfr at 0xCA RCAP2L;
-sfr at 0xCB RCAP2H;
-sfr at 0xCC TL2;
-sfr at 0xCD TH2;
-sfr at 0xD0 PSW;
+ __sbit __at 0xC8+0 CP_RL2;
+ __sbit __at 0xC8+1 C_T2;
+ __sbit __at 0xC8+2 TR2;
+ __sbit __at 0xC8+3 EXEN2;
+ __sbit __at 0xC8+4 TCLK;
+ __sbit __at 0xC8+5 RCLK;
+ __sbit __at 0xC8+6 EXF2;
+ __sbit __at 0xC8+7 TF2;
+__sfr __at 0xCA RCAP2L;
+__sfr __at 0xCB RCAP2H;
+__sfr __at 0xCC TL2;
+__sfr __at 0xCD TH2;
+__sfr __at 0xD0 PSW;
/* PSW */
- sbit at 0xD0+0 P;
- sbit at 0xD0+1 FL;
- sbit at 0xD0+2 OV;
- sbit at 0xD0+3 RS0;
- sbit at 0xD0+4 RS1;
- sbit at 0xD0+5 F0;
- sbit at 0xD0+6 AC;
- sbit at 0xD0+7 CY;
-sfr at 0xD8 EICON; // Was WDCON in DS80C320 EICON; Bit Values differ from Reg320
+ __sbit __at 0xD0+0 P;
+ __sbit __at 0xD0+1 FL;
+ __sbit __at 0xD0+2 OV;
+ __sbit __at 0xD0+3 RS0;
+ __sbit __at 0xD0+4 RS1;
+ __sbit __at 0xD0+5 F0;
+ __sbit __at 0xD0+6 AC;
+ __sbit __at 0xD0+7 CY;
+__sfr __at 0xD8 EICON; // Was WDCON in DS80C320 EICON; Bit Values differ from Reg320
/* EICON */
- sbit at 0xD8+3 INT6;
- sbit at 0xD8+4 RESI;
- sbit at 0xD8+5 ERESI;
- sbit at 0xD8+7 SMOD1;
-sfr at 0xE0 ACC;
-sfr at 0xE8 EIE; // EIE Bit Values differ from Reg320
+ __sbit __at 0xD8+3 INT6;
+ __sbit __at 0xD8+4 RESI;
+ __sbit __at 0xD8+5 ERESI;
+ __sbit __at 0xD8+7 SMOD1;
+__sfr __at 0xE0 ACC;
+__sfr __at 0xE8 EIE; // EIE Bit Values differ from Reg320
/* EIE */
- sbit at 0xE8+0 EIUSB;
- sbit at 0xE8+1 EI2C;
- sbit at 0xE8+2 EIEX4;
- sbit at 0xE8+3 EIEX5;
- sbit at 0xE8+4 EIEX6;
-sfr at 0xF0 B;
-sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320
+ __sbit __at 0xE8+0 EIUSB;
+ __sbit __at 0xE8+1 EI2C;
+ __sbit __at 0xE8+2 EIEX4;
+ __sbit __at 0xE8+3 EIEX5;
+ __sbit __at 0xE8+4 EIEX6;
+__sfr __at 0xF0 B;
+__sfr __at 0xF8 EIP; // EIP Bit Values differ from Reg320
/* EIP */
- sbit at 0xF8+0 PUSB;
- sbit at 0xF8+1 PI2C;
- sbit at 0xF8+2 EIPX4;
- sbit at 0xF8+3 EIPX5;
- sbit at 0xF8+4 EIPX6;
+ __sbit __at 0xF8+0 PUSB;
+ __sbit __at 0xF8+1 PI2C;
+ __sbit __at 0xF8+2 EIPX4;
+ __sbit __at 0xF8+3 EIPX5;
+ __sbit __at 0xF8+4 EIPX6;
/*-----------------------------------------------------------------------------
Bit Masks
@@ -684,7 +684,7 @@
#define EP4FIFOEMPTY bmBIT5
/*
- * Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specific features
+ * Chip Revision Control Bits (REVCTL) - used to enable/disable revision specific features
*/
#define bmNOAUTOARM bmBIT1 // these don't match the docs
#define bmSKIPCOMMIT bmBIT0 // these don't match the docs

14
comms/usrp/files/patch-firmware_fx2_common_fx2utils.c
View File

@ -1,14 +0,0 @@
--- firmware/fx2/common/fx2utils.c.orig 2012-07-30 14:09:48.000000000 -0500
+++ firmware/fx2/common/fx2utils.c 2012-10-07 19:36:47.000000000 -0500
@@ -42,8 +42,9 @@
{
USBCS |= bmDISCON | bmRENUM;
- // mdelay (1500); // FIXME why 1.5 seconds?
- mdelay (250); // FIXME why 1.5 seconds?
+ mdelay (1500); // FIXME why 1.5 seconds?
+// Does not seem to settle fast enough on some USRPs -- db
+// mdelay (250); // FIXME why 1.5 seconds?
USBIRQ = 0xff; // clear any pending USB irqs...
EPIRQ = 0xff; // they're from before the renumeration

20
comms/usrp/files/patch-firmware_fx2_common_i2c.c
View File

@ -1,20 +0,0 @@
--- firmware/fx2/common/i2c.c.orig 2012-07-30 14:09:48.000000000 -0500
+++ firmware/fx2/common/i2c.c 2012-10-07 19:37:38.000000000 -0500
@@ -30,7 +30,7 @@
// returns non-zero if successful, else 0
unsigned char
-i2c_read (unsigned char addr, xdata unsigned char *buf, unsigned char len)
+i2c_read (unsigned char addr, __xdata unsigned char *buf, unsigned char len)
{
volatile unsigned char junk;
@@ -89,7 +89,7 @@
// returns non-zero if successful, else 0
unsigned char
-i2c_write (unsigned char addr, xdata const unsigned char *buf, unsigned char len)
+i2c_write (unsigned char addr, __xdata const unsigned char *buf, unsigned char len)
{
while (I2CS & bmSTOP) // wait for stop to clear
;

14
comms/usrp/files/patch-firmware_fx2_common_i2c.h
View File

@ -1,14 +0,0 @@
--- firmware/fx2/common/i2c.h.orig 2012-07-30 14:09:48.000000000 -0500
+++ firmware/fx2/common/i2c.h 2012-10-07 19:34:39.000000000 -0500
@@ -24,9 +24,9 @@
#define _I2C_H_
// returns non-zero if successful, else 0
-unsigned char i2c_read (unsigned char addr, xdata unsigned char *buf, unsigned char len);
+unsigned char i2c_read (unsigned char addr, __xdata unsigned char *buf, unsigned char len);
// returns non-zero if successful, else 0
-unsigned char i2c_write (unsigned char addr, xdata const unsigned char *buf, unsigned char len);
+unsigned char i2c_write (unsigned char addr, __xdata const unsigned char *buf, unsigned char len);
#endif /* _I2C_H_ */

42
comms/usrp/files/patch-firmware_fx2_common_isr.c
View File

@ -1,42 +0,0 @@
--- firmware/fx2/common/isr.c.orig 2012-07-30 14:09:48.000000000 -0500
+++ firmware/fx2/common/isr.c 2012-10-07 19:37:47.000000000 -0500
@@ -24,9 +24,9 @@
#include "fx2regs.h"
#include "syncdelay.h"
-extern xdata unsigned char _standard_interrupt_vector[];
-extern xdata unsigned char _usb_autovector[];
-extern xdata unsigned char _fifo_gpif_autovector[];
+extern __xdata unsigned char _standard_interrupt_vector[];
+extern __xdata unsigned char _usb_autovector[];
+extern __xdata unsigned char _fifo_gpif_autovector[];
#define LJMP_OPCODE 0x02
@@ -39,7 +39,7 @@
void
hook_sv (unsigned char vector_number, unsigned short addr)
{
- bit t;
+ __bit t;
// sanity checks
@@ -66,7 +66,7 @@
void
hook_uv (unsigned char vector_number, unsigned short addr)
{
- bit t;
+ __bit t;
// sanity checks
@@ -93,7 +93,7 @@
void
hook_fgv (unsigned char vector_number, unsigned short addr)
{
- bit t;
+ __bit t;
// sanity checks

69
comms/usrp/files/patch-firmware_fx2_common_spi.c
View File

@ -1,69 +0,0 @@
--- firmware/fx2/common/spi.c.orig 2012-07-30 14:09:48.000000000 -0500
+++ firmware/fx2/common/spi.c 2012-10-07 19:39:17.000000000 -0500
@@ -98,17 +98,17 @@
write_byte_msb (unsigned char v);
static void
-write_bytes_msb (const xdata unsigned char *buf, unsigned char len);
+write_bytes_msb (const __xdata unsigned char *buf, unsigned char len);
static void
-read_bytes_msb (xdata unsigned char *buf, unsigned char len);
+read_bytes_msb (__xdata unsigned char *buf, unsigned char len);
// returns non-zero if successful, else 0
unsigned char
spi_read (unsigned char header_hi, unsigned char header_lo,
unsigned char enables, unsigned char format,
- xdata unsigned char *buf, unsigned char len)
+ __xdata unsigned char *buf, unsigned char len)
{
if (count_bits8 (enables) > 1)
return 0; // error, too many enables set
@@ -165,7 +165,7 @@
unsigned char
spi_write (unsigned char header_hi, unsigned char header_lo,
unsigned char enables, unsigned char format,
- const xdata unsigned char *buf, unsigned char len)
+ const __xdata unsigned char *buf, unsigned char len)
{
setup_enables (enables);
@@ -261,7 +261,7 @@
}
static void
-write_bytes_msb (const xdata unsigned char *buf, unsigned char len)
+write_bytes_msb (const __xdata unsigned char *buf, unsigned char len)
{
while (len-- != 0){
write_byte_msb (*buf++);
@@ -320,9 +320,10 @@
}
#else
static unsigned char
-read_byte_msb (void) _naked
+read_byte_msb (void)
+// _naked
{
- _asm
+ __asm
clr a
setb _bitS_CLK
@@ -367,12 +368,12 @@
mov dpl,a
ret
- _endasm;
+ __endasm;
}
#endif
static void
-read_bytes_msb (xdata unsigned char *buf, unsigned char len)
+read_bytes_msb (__xdata unsigned char *buf, unsigned char len)
{
while (len-- != 0){
*buf++ = read_byte_msb ();

18
comms/usrp/files/patch-firmware_fx2_common_spi.h
View File

@ -1,18 +0,0 @@
--- firmware/fx2/common/spi.h.orig 2012-07-30 14:09:48.000000000 -0500
+++ firmware/fx2/common/spi.h 2012-10-07 19:39:16.000000000 -0500
@@ -31,13 +31,13 @@
unsigned char
spi_read (unsigned char header_hi, unsigned char header_lo,
unsigned char enables, unsigned char format,
- xdata unsigned char *buf, unsigned char len);
+ __xdata unsigned char *buf, unsigned char len);
// returns non-zero if successful, else 0
unsigned char
spi_write (unsigned char header_hi, unsigned char header_lo,
unsigned char enables, unsigned char format,
- const xdata unsigned char *buf, unsigned char len);
+ const __xdata unsigned char *buf, unsigned char len);
#endif /* INCLUDED_SPI_H */

22
comms/usrp/files/patch-firmware_fx2_common_syncdelay.h
View File

@ -1,22 +0,0 @@
--- firmware/fx2/common/syncdelay.h.orig 2012-07-30 14:09:48.000000000 -0500
+++ firmware/fx2/common/syncdelay.h 2012-10-10 13:21:36.000000000 -0500
@@ -23,7 +23,7 @@
#define _SYNCDELAY_H_
/*
- * Magic delay required between access to certain xdata registers (TRM page 15-106).
+ * Magic delay required between access to certain __xdata registers (TRM page 15-106).
* For our configuration, 48 MHz FX2 / 48 MHz IFCLK, we need three cycles. Each
* NOP is a single cycle....
*
@@ -58,8 +58,8 @@
/*
* FIXME ensure that the peep hole optimizer isn't screwing us
*/
-#define SYNCDELAY _asm nop; nop; nop; _endasm
-#define NOP _asm nop; _endasm
+#define SYNCDELAY __asm nop; nop; nop; __endasm
+#define NOP __asm nop; __endasm
#endif /* _SYNCDELAY_H_ */

85
comms/usrp/files/patch-firmware_fx2_common_usb_common.c
View File

@ -1,85 +0,0 @@
--- firmware/fx2/common/usb_common.c.orig 2012-07-30 14:09:48.000000000 -0500
+++ firmware/fx2/common/usb_common.c 2012-10-07 19:37:57.000000000 -0500
@@ -28,12 +28,12 @@
#include "usb_descriptors.h"
#include "usb_requests.h"
-extern xdata char str0[];
-extern xdata char str1[];
-extern xdata char str2[];
-extern xdata char str3[];
-extern xdata char str4[];
-extern xdata char str5[];
+extern __xdata char str0[];
+extern __xdata char str1[];
+extern __xdata char str2[];
+extern __xdata char str3[];
+extern __xdata char str4[];
+extern __xdata char str5[];
#define bRequestType SETUPDAT[0]
@@ -48,15 +48,15 @@
#define MSB(x) (((unsigned short) x) >> 8)
#define LSB(x) (((unsigned short) x) & 0xff)
-volatile bit _usb_got_SUDAV;
+volatile __bit _usb_got_SUDAV;
unsigned char _usb_config = 0;
unsigned char _usb_alt_setting = 0; // FIXME really 1/interface
-xdata unsigned char *current_device_descr;
-xdata unsigned char *current_devqual_descr;
-xdata unsigned char *current_config_descr;
-xdata unsigned char *other_config_descr;
+__xdata unsigned char *current_device_descr;
+__xdata unsigned char *current_devqual_descr;
+__xdata unsigned char *current_config_descr;
+__xdata unsigned char *other_config_descr;
static void
setup_descriptors (void)
@@ -81,21 +81,21 @@
}
static void
-isr_SUDAV (void) interrupt
+isr_SUDAV (void) __interrupt
{
clear_usb_irq ();
_usb_got_SUDAV = 1;
}
static void
-isr_USBRESET (void) interrupt
+isr_USBRESET (void) __interrupt
{
clear_usb_irq ();
setup_descriptors ();
}
static void
-isr_HIGHSPEED (void) interrupt
+isr_HIGHSPEED (void) __interrupt
{
clear_usb_irq ();
setup_descriptors ();
@@ -133,7 +133,7 @@
// return pointer to control and status register for endpoint.
// only called with plausible_endpoints
-xdata volatile unsigned char *
+__xdata volatile unsigned char *
epcs (unsigned char ep)
{
if (ep == 0x01) // ep1 has different in and out CS regs
@@ -234,7 +234,7 @@
if (wValueL >= nstring_descriptors)
fx2_stall_ep0 ();
else {
- xdata char *p = string_descriptors[wValueL];
+ __xdata char *p = string_descriptors[wValueL];
SUDPTRH = MSB (p);
SUDPTRL = LSB (p);
}

11
comms/usrp/files/patch-firmware_fx2_common_usb_common.h
View File

@ -1,11 +0,0 @@
--- firmware/fx2/common/usb_common.h.orig 2012-07-30 14:09:48.000000000 -0500
+++ firmware/fx2/common/usb_common.h 2012-10-07 19:36:05.000000000 -0500
@@ -23,7 +23,7 @@
#ifndef _USB_COMMON_H_
#define _USB_COMMON_H_
-extern volatile bit _usb_got_SUDAV;
+extern volatile __bit _usb_got_SUDAV;
// Provided by user application to handle VENDOR commands.
// returns non-zero if it handled the command.

36
comms/usrp/files/patch-firmware_fx2_common_usb_descriptors.h
View File

@ -1,36 +0,0 @@
--- firmware/fx2/common/usb_descriptors.h.orig 2012-07-30 14:09:48.000000000 -0500
+++ firmware/fx2/common/usb_descriptors.h 2012-10-07 19:36:22.000000000 -0500
@@ -20,21 +20,21 @@
* Boston, MA 02110-1301, USA.
*/
-extern xdata const char high_speed_device_descr[];
-extern xdata const char high_speed_devqual_descr[];
-extern xdata const char high_speed_config_descr[];
+extern __xdata const char high_speed_device_descr[];
+extern __xdata const char high_speed_devqual_descr[];
+extern __xdata const char high_speed_config_descr[];
-extern xdata const char full_speed_device_descr[];
-extern xdata const char full_speed_devqual_descr[];
-extern xdata const char full_speed_config_descr[];
+extern __xdata const char full_speed_device_descr[];
+extern __xdata const char full_speed_devqual_descr[];
+extern __xdata const char full_speed_config_descr[];
-extern xdata unsigned char nstring_descriptors;
-extern xdata char * xdata string_descriptors[];
+extern __xdata unsigned char nstring_descriptors;
+extern __xdata char * __xdata string_descriptors[];
/*
* We patch these locations with info read from the usrp config eeprom
*/
-extern xdata char usb_desc_hw_rev_binary_patch_location_0[];
-extern xdata char usb_desc_hw_rev_binary_patch_location_1[];
-extern xdata char usb_desc_hw_rev_ascii_patch_location_0[];
-extern xdata char usb_desc_serial_number_ascii[];
+extern __xdata char usb_desc_hw_rev_binary_patch_location_0[];
+extern __xdata char usb_desc_hw_rev_binary_patch_location_1[];
+extern __xdata char usb_desc_hw_rev_ascii_patch_location_0[];
+extern __xdata char usb_desc_serial_number_ascii[];

11
comms/usrp/files/patch-firmware_fx2_config_CMakeDetermineASM_SDCCCompiler.cmake
View File

@ -1,11 +0,0 @@
--- firmware/fx2/config/CMakeDetermineASM_SDCCCompiler.cmake.orig 2012-10-06 17:31:51.000000000 -0500
+++ firmware/fx2/config/CMakeDetermineASM_SDCCCompiler.cmake 2012-10-09 07:09:09.000000000 -0500
@@ -16,7 +16,6 @@
SET(ASM_DIALECT "_SDCC")
-SET(CMAKE_ASM${ASM_DIALECT}_COMPILER_INIT asx8051)
+SET(CMAKE_ASM${ASM_DIALECT}_COMPILER_INIT mcs51)
INCLUDE(CMakeDetermineASMCompiler)
-SET(ASM_DIALECT)

17
comms/usrp/files/patch-firmware_fx2_config_Toolchain-sdcc.cmake
View File

@ -1,17 +0,0 @@
--- firmware/fx2/config/Toolchain-sdcc.cmake.orig 2012-07-30 14:09:48.000000000 -0500
+++ firmware/fx2/config/Toolchain-sdcc.cmake 2012-10-10 16:22:15.000000000 -0500
@@ -19,9 +19,13 @@
SET(CMAKE_SYSTEM_NAME Generic)
# which compilers to use for C and C++
SET(CMAKE_C_COMPILER sdcc)
+#SET(CMAKE_ASM_SDCC_COMPILER asm)
+SET(CMAKE_ASM_SDCC_COMPILER sdas8051)
+#SET CMAKE_ASM_SDCC_COMPILER
+#SET(CMAKE_ASM_COMPILER sdcc)
# here is where the target environment is located
-SET(CMAKE_FIND_ROOT_PATH /usr/bin /usr/share/sdcc)
+SET(CMAKE_FIND_ROOT_PATH /usr/local/bin /usr/local/share/sdcc)
# adjust the default behaviour of the FIND_XXX() commands:
# search headers and libraries in the target environment, search

11
comms/usrp/files/patch-firmware_fx2_usrp1_board_specific.c
View File

@ -1,11 +0,0 @@
--- firmware/fx2/usrp1/board_specific.c.orig 2012-10-10 13:25:42.000000000 -0500
+++ firmware/fx2/usrp1/board_specific.c 2012-10-10 13:25:51.000000000 -0500
@@ -64,7 +64,7 @@
// NOP on usrp1
}
-static xdata unsigned char xbuf[1];
+static __xdata unsigned char xbuf[1];
void
write_9862 (unsigned char which, unsigned char regno, unsigned char value)

29
comms/usrp/files/patch-firmware_fx2_usrp1_eeprom_io.c
View File

@ -1,29 +0,0 @@
--- firmware/fx2/usrp1/eeprom_io.c.orig 2012-10-10 13:22:48.000000000 -0500
+++ firmware/fx2/usrp1/eeprom_io.c 2012-10-10 13:23:15.000000000 -0500
@@ -27,12 +27,12 @@
// returns non-zero if successful, else 0
unsigned char
eeprom_read (unsigned char i2c_addr, unsigned char eeprom_offset,
- xdata unsigned char *buf, unsigned char len)
+ __xdata unsigned char *buf, unsigned char len)
{
// We setup a random read by first doing a "zero byte write".
// Writes carry an address. Reads use an implicit address.
- static xdata unsigned char cmd[1];
+ static __xdata unsigned char cmd[1];
cmd[0] = eeprom_offset;
if (!i2c_write(i2c_addr, cmd, 1))
return 0;
@@ -46,9 +46,9 @@
// returns non-zero if successful, else 0
unsigned char
eeprom_write (unsigned char i2c_addr, unsigned char eeprom_offset,
- const xdata unsigned char *buf, unsigned char len)
+ const __xdata unsigned char *buf, unsigned char len)
{
- static xdata unsigned char cmd[2];
+ static __xdata unsigned char cmd[2];
unsigned char ok;
while (len-- > 0){

17
comms/usrp/files/patch-firmware_fx2_usrp1_eeprom_io.h
View File

@ -1,17 +0,0 @@
--- firmware/fx2/usrp1/eeprom_io.h.orig 2012-10-10 13:16:02.000000000 -0500
+++ firmware/fx2/usrp1/eeprom_io.h 2012-10-10 13:16:27.000000000 -0500
@@ -27,12 +27,12 @@
// returns non-zero if successful, else 0
unsigned char
eeprom_read (unsigned char i2c_addr, unsigned char eeprom_offset,
- xdata unsigned char *buf, unsigned char len);
+ __xdata unsigned char *buf, unsigned char len);
// returns non-zero if successful, else 0
unsigned char
eeprom_write (unsigned char i2c_addr, unsigned char eeprom_offset,
- const xdata unsigned char *buf, unsigned char len);
+ const __xdata unsigned char *buf, unsigned char len);
#endif /* INCLUDED_EEPROM_IO_H */

40
comms/usrp/files/patch-firmware_fx2_usrp1_fpga_load.c
View File

@ -1,40 +0,0 @@
--- firmware/fx2/usrp1/fpga_load.c.orig 2012-10-10 13:23:35.000000000 -0500
+++ firmware/fx2/usrp1/fpga_load.c 2012-10-10 16:28:26.000000000 -0500
@@ -89,9 +89,9 @@
#else
static void
-clock_out_config_byte (unsigned char bits) _naked
+clock_out_config_byte (unsigned char bits) __naked
{
- _asm
+ __asm
mov a, dpl
rrc a
@@ -136,14 +136,14 @@
ret
- _endasm;
+ __endasm;
}
#endif
static void
clock_out_bytes (unsigned char bytecount,
- unsigned char xdata *p)
+ unsigned char __xdata *p)
{
while (bytecount-- > 0)
clock_out_config_byte (*p++);
@@ -163,7 +163,7 @@
* ALTERA_NSTATUS = 1 (input)
*/
unsigned char
-fpga_load_xfer (xdata unsigned char *p, unsigned char bytecount)
+fpga_load_xfer (__xdata unsigned char *p, unsigned char bytecount)
{
clock_out_bytes (bytecount, p);
return 1;

20
comms/usrp/files/patch-firmware_fx2_usrp1_fpga_rev2.c
View File

@ -1,20 +0,0 @@
--- firmware/fx2/usrp1/fpga_rev2.c.orig 2012-10-10 13:24:09.000000000 -0500
+++ firmware/fx2/usrp1/fpga_rev2.c 2012-10-10 13:24:24.000000000 -0500
@@ -30,7 +30,7 @@
unsigned char g_rx_reset = 0;
void
-fpga_write_reg (unsigned char regno, const xdata unsigned char *regval)
+fpga_write_reg (unsigned char regno, const __xdata unsigned char *regval)
{
spi_write (0, 0x00 | (regno & 0x7f),
SPI_ENABLE_FPGA,
@@ -39,7 +39,7 @@
}
-static xdata unsigned char regval[4] = {0, 0, 0, 0};
+static __xdata unsigned char regval[4] = {0, 0, 0, 0};
static void
write_fpga_master_ctrl (void)

29
comms/usrp/files/patch-firmware_fx2_usrp1_gpif.c
View File

@ -1,29 +0,0 @@
--- firmware/fx2/usrp1/gpif.c.orig 2014-07-04 14:55:38.716872326 -0400
+++ firmware/fx2/usrp1/gpif.c 2014-07-05 19:13:33.863851247 -0400
@@ -156,7 +156,7 @@
// END DO NOT EDIT
// DO NOT EDIT ...
-const char xdata WaveData[128] =
+const char WaveData[128] =
{
// Wave 0
/* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
@@ -182,7 +182,7 @@
// END DO NOT EDIT
// DO NOT EDIT ...
-const char xdata FlowStates[36] =
+const char __xdata FlowStates[36] =
{
/* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
@@ -192,7 +192,7 @@
// END DO NOT EDIT
// DO NOT EDIT ...
-const char xdata InitData[7] =
+const char InitData[7] =
{
/* Regs */ 0xA0,0x00,0x00,0x00,0xEE,0x4E,0x00
};

31
comms/usrp/files/patch-firmware_fx2_usrp1_usrp_main.c
View File

@ -1,31 +0,0 @@
--- firmware/fx2/usrp1/usrp_main.c.orig 2012-10-10 13:25:13.000000000 -0500
+++ firmware/fx2/usrp1/usrp_main.c 2012-10-10 16:30:10.000000000 -0500
@@ -63,7 +63,7 @@
* into hash1.
*/
#define USRP_HASH_SIZE 16
-xdata at USRP_HASH_SLOT_1_ADDR unsigned char hash1[USRP_HASH_SIZE];
+__xdata __at USRP_HASH_SLOT_1_ADDR unsigned char hash1[USRP_HASH_SIZE];
static void
get_ep0_data (void)
@@ -305,7 +305,7 @@
* Toggle led 0
*/
void
-isr_tick (void) interrupt
+isr_tick (void) __interrupt
{
static unsigned char count = 1;
@@ -324,8 +324,8 @@
void
patch_usb_descriptors(void)
{
- static xdata unsigned char hw_rev;
- static xdata unsigned char serial_no[8];
+ static __xdata unsigned char hw_rev;
+ static __xdata unsigned char serial_no[8];
unsigned char i;
eeprom_read(I2C_ADDR_BOOT, HW_REV_OFFSET, &hw_rev, 1); // LSB of device id

26
comms/usrp/files/patch-firmware_fx2_usrp1_usrp_regs.h
View File

@ -1,26 +0,0 @@
--- firmware/fx2/usrp1/usrp_regs.h.orig 2012-10-07 20:07:53.000000000 -0500
+++ firmware/fx2/usrp1/usrp_regs.h 2012-10-07 20:08:24.000000000 -0500
@@ -47,9 +47,9 @@
#define bmPA_TX_UNDERRUN bmBIT7 // misc pin to FPGA (underflow)
-sbit at 0x80+0 bitS_CLK; // 0x80 is the bit address of PORT A
-sbit at 0x80+1 bitS_OUT; // out from FX2 point of view
-sbit at 0x80+2 bitS_IN; // in from FX2 point of view
+__sbit __at 0x80+0 bitS_CLK; // 0x80 is the bit address of PORT A
+__sbit __at 0x80+1 bitS_OUT; // out from FX2 point of view
+__sbit __at 0x80+2 bitS_IN; // in from FX2 point of view
/* all outputs except S_DATA_FROM_PERIPH, FX2_2, FX2_3 */
@@ -85,8 +85,8 @@
#define bmPC_LED0 bmBIT6 // active low
#define bmPC_LED1 bmBIT7 // active low
-sbit at 0xA0+1 bitALTERA_DATA0; // 0xA0 is the bit address of PORT C
-sbit at 0xA0+3 bitALTERA_DCLK;
+__sbit __at 0xA0+1 bitALTERA_DATA0; // 0xA0 is the bit address of PORT C
+__sbit __at 0xA0+3 bitALTERA_DCLK;
#define bmALTERA_BITS (bmALTERA_DATA0 \

11
comms/usrp/files/patch-host_CMakeLists.txt
View File

@ -1,11 +0,0 @@
--- host/CMakeLists.txt.orig 2014-07-10 00:22:32.824756011 -0400
+++ host/CMakeLists.txt 2014-07-10 00:24:10.487748148 -0400
@@ -256,7 +256,7 @@
INSTALL(
FILES ${CMAKE_CURRENT_BINARY_DIR}/uhd.pc
- DESTINATION ${LIBRARY_DIR}/pkgconfig
+ DESTINATION libdata/pkgconfig
COMPONENT libraries
)

10
comms/usrp/files/patch-host_examples_CMakeLists.txt
View File

@ -1,10 +0,0 @@
--- host/examples/CMakeLists.txt.orig
+++ host/examples/CMakeLists.txt
@@ -41,6 +41,7 @@
TARGET_LINK_LIBRARIES(${example_name} uhd)
INSTALL(TARGETS ${example_name} RUNTIME DESTINATION ${PKG_LIB_DIR}/examples COMPONENT examples)
ENDFOREACH(example_source)
+TARGET_LINK_LIBRARIES(network_relay -pthread)
########################################################################
# ASCII Art DFT - requires curses, so this part is optional

16
comms/usrp/files/patch-host_lib_usrp_dboard_id.cpp
View File

@ -1,16 +0,0 @@
--- host/lib/usrp/dboard_id.cpp.orig 2014-04-01 21:48:39.542370984 -0400
+++ host/lib/usrp/dboard_id.cpp 2014-04-01 21:50:22.617363414 -0400
@@ -51,9 +51,11 @@
dboard_id_t dboard_id_t::from_string(const std::string &string){
if (string.substr(0, 2) == "0x"){
- return dboard_id_t::from_uint16(boost::lexical_cast<to_hex<boost::uint16_t> >(string));
+ std::stringstream interpreter(string);
+ to_hex<boost::uint16_t> hh;
+ interpreter >>hh;
+ return dboard_id_t::from_uint16(hh);
}
- return dboard_id_t::from_uint16(boost::lexical_cast<boost::uint16_t>(string));
}
std::string dboard_id_t::to_string(void) const{

198
comms/usrp/files/patch-images_Makefile
View File

@ -1,198 +0,0 @@
--- images/Makefile.orig 2013-12-22 13:39:06.675009366 -0500
+++ images/Makefile 2013-12-25 16:43:43.362707751 -0500
@@ -29,6 +29,8 @@
##filled in below
IMAGES_LIST =
+USRP1_LIST =
+USRP2_LIST =
##little rule to make the images directory
$(BUILT_IMAGES_DIR):
@@ -61,12 +63,13 @@
_usrp1_fw_ihx = $(BUILT_IMAGES_DIR)/usrp1_fw.ihx
_usrp_b100_fw_ihx = $(BUILT_IMAGES_DIR)/usrp_b100_fw.ihx
IMAGES_LIST += $(_usrp1_fw_ihx) $(_usrp_b100_fw_ihx)
+USRP1_LIST += $(_usrp1_fw_ihx) $(_usrp_b100_fw_ihx)
$(_usrp1_fw_ihx): $(GLOBAL_DEPS)
cd $(_usrp1_fw_dir) && rm -rf build
cd $(_usrp1_fw_dir) && mkdir build
cd $(_usrp1_fw_dir)/build && cmake ../
- cd $(_usrp1_fw_dir)/build && make
+ cd $(_usrp1_fw_dir)/build && gmake
cp $(_usrp1_fw_dir)/build/usrp1/usrp1_fw.ihx $@
$(_usrp_b100_fw_ihx): $(_usrp1_fw_ihx)
@@ -81,6 +84,7 @@
_usrp1_fpga_rbf = $(BUILT_IMAGES_DIR)/usrp1_fpga.rbf
_usrp1_fpga_4rx_rbf = $(BUILT_IMAGES_DIR)/usrp1_fpga_4rx.rbf
IMAGES_LIST += $(_usrp1_fpga_rbf) $(_usrp1_fpga_4rx_rbf)
+USRP1_LIST += $(_usrp1_fpga_rbf) $(_usrp1_fpga_4rx_rbf)
$(_usrp1_fpga_rbf): $(GLOBAL_DEPS)
cp $(_usrp1_fpga_dir)/std_2rxhb_2tx.rbf $@
@@ -96,10 +100,11 @@
_usrp_b100_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/B100
_usrp_b100_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_b100_fpga.bin
IMAGES_LIST += $(_usrp_b100_fpga_bin)
+USRP1_LIST += $(_usrp_b100_fpga_bin)
$(_usrp_b100_fpga_bin): $(GLOBAL_DEPS)
- cd $(_usrp_b100_fpga_dir) && make -f Makefile.B100 clean
- cd $(_usrp_b100_fpga_dir) && make -f Makefile.B100 bin
+ cd $(_usrp_b100_fpga_dir) && gmake -f Makefile.B100 clean
+ cd $(_usrp_b100_fpga_dir) && gmake -f Makefile.B100 bin
cp $(_usrp_b100_fpga_dir)/build-B100/B100.bin $@
endif
@@ -114,12 +119,13 @@
_usrp_n200_fw_bin = $(BUILT_IMAGES_DIR)/usrp_n200_fw.bin
_usrp_n210_fw_bin = $(BUILT_IMAGES_DIR)/usrp_n210_fw.bin
IMAGES_LIST += $(_usrp2_fw_bin) $(_usrp_n200_fw_bin) $(_usrp_n210_fw_bin)
+USRP2_LIST += $(_usrp2_fw_bin) $(_usrp_n200_fw_bin) $(_usrp_n210_fw_bin)
$(_usrp2_fw_bin): $(GLOBAL_DEPS)
cd $(_usrp2_fw_dir) && rm -rf build
cd $(_usrp2_fw_dir) && mkdir build
cd $(_usrp2_fw_dir)/build && cmake ../
- cd $(_usrp2_fw_dir)/build && make
+ cd $(_usrp2_fw_dir)/build && gmake
cp $(_usrp2_fw_dir)/build/usrp2/usrp2_txrx_uhd.bin $@
$(_usrp_n200_fw_bin): $(_usrp2_fw_bin)
@@ -138,10 +144,11 @@
_usrp2_fpga_dir = $(TOP_FPGA_DIR)/usrp2/top/USRP2
_usrp2_fpga_bin = $(BUILT_IMAGES_DIR)/usrp2_fpga.bin
IMAGES_LIST += $(_usrp2_fpga_bin)
+USRP2_LIST += $(_usrp2_fpga_bin)
$(_usrp2_fpga_bin): $(GLOBAL_DEPS)
- cd $(_usrp2_fpga_dir) && make clean
- cd $(_usrp2_fpga_dir) && make bin
+ cd $(_usrp2_fpga_dir) && gmake clean
+ cd $(_usrp2_fpga_dir) && gmake bin
cp $(_usrp2_fpga_dir)/build/u2_rev3.bin $@
endif
@@ -155,18 +162,20 @@
_usrp_n200_r3_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_n200_r3_fpga.bin
_usrp_n200_r3_fpga_bit = $(BUILT_IMAGES_DIR)/bit/usrp_n200_r3_fpga.bit
IMAGES_LIST += $(_usrp_n200_r3_fpga_bin) $(_usrp_n200_r3_fpga_bit)
+USRP2_LIST += $(_usrp_n200_r3_fpga_bin) $(_usrp_n200_r3_fpga_bit)
$(_usrp_n200_r3_fpga_bin): $(GLOBAL_DEPS)
- cd $(_usrp_n200_r3_fpga_dir) && make -f Makefile.N200R3 clean
- cd $(_usrp_n200_r3_fpga_dir) && make -f Makefile.N200R3 bin
+ cd $(_usrp_n200_r3_fpga_dir) && gmake -f Makefile.N200R3 clean
+ cd $(_usrp_n200_r3_fpga_dir) && gmake -f Makefile.N200R3 bin
cp $(_usrp_n200_r3_fpga_dir)/build-N200R3/u2plus.bin $@
$(_usrp_n200_r3_fpga_bit): $(_usrp_n200_r3_fpga_bin)
cp $(_usrp_n200_r3_fpga_dir)/build-N200R3/u2plus.bit $@
-#its called r2 on the silkscreen, so make an r2
+#its called r2 on the silkscreen, so gmake an r2
_usrp_n200_r2_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_n200_r2_fpga.bin
IMAGES_LIST += $(_usrp_n200_r2_fpga_bin)
+USRP2_LIST += $(_usrp_n200_r2_fpga_bin)
$(_usrp_n200_r2_fpga_bin): $(_usrp_n200_r3_fpga_bin)
cp $< $@
@@ -181,18 +190,20 @@
_usrp_n210_r3_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_n210_r3_fpga.bin
_usrp_n210_r3_fpga_bit = $(BUILT_IMAGES_DIR)/bit/usrp_n210_r3_fpga.bit
IMAGES_LIST += $(_usrp_n210_r3_fpga_bin) $(_usrp_n210_r3_fpga_bit)
+USRP2_LIST += $(_usrp_n210_r3_fpga_bin) $(_usrp_n210_r3_fpga_bit)
$(_usrp_n210_r3_fpga_bin): $(GLOBAL_DEPS)
- cd $(_usrp_n210_r3_fpga_dir) && make -f Makefile.N210R3 clean
- cd $(_usrp_n210_r3_fpga_dir) && make -f Makefile.N210R3 bin
+ cd $(_usrp_n210_r3_fpga_dir) && gmake -f Makefile.N210R3 clean
+ cd $(_usrp_n210_r3_fpga_dir) && gmake -f Makefile.N210R3 bin
cp $(_usrp_n210_r3_fpga_dir)/build-N210R3/u2plus.bin $@
$(_usrp_n210_r3_fpga_bit): $(_usrp_n210_r3_fpga_bin)
cp $(_usrp_n210_r3_fpga_dir)/build-N210R3/u2plus.bit $@
-#its called r2 on the silkscreen, so make an r2
+#its called r2 on the silkscreen, so gmake an r2
_usrp_n210_r2_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_n210_r2_fpga.bin
IMAGES_LIST += $(_usrp_n210_r2_fpga_bin)
+USRP2_LIST += $(_usrp_n210_r2_fpga_bin)
$(_usrp_n210_r2_fpga_bin): $(_usrp_n210_r3_fpga_bin)
cp $< $@
@@ -207,10 +218,11 @@
_usrp_n200_r4_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_n200_r4_fpga.bin
_usrp_n200_r4_fpga_bit = $(BUILT_IMAGES_DIR)/bit/usrp_n200_r4_fpga.bit
IMAGES_LIST += $(_usrp_n200_r4_fpga_bin) $(_usrp_n200_r4_fpga_bit)
+USRP2_LIST += $(_usrp_n200_r4_fpga_bin) $(_usrp_n200_r4_fpga_bit)
$(_usrp_n200_r4_fpga_bin): $(GLOBAL_DEPS)
- cd $(_usrp_n200_r4_fpga_dir) && make -f Makefile.N200R4 clean
- cd $(_usrp_n200_r4_fpga_dir) && make -f Makefile.N200R4 bin
+ cd $(_usrp_n200_r4_fpga_dir) && gmake -f Makefile.N200R4 clean
+ cd $(_usrp_n200_r4_fpga_dir) && gmake -f Makefile.N200R4 bin
cp $(_usrp_n200_r4_fpga_dir)/build-N200R4/u2plus.bin $@
$(_usrp_n200_r4_fpga_bit): $(_usrp_n200_r4_fpga_bin)
@@ -227,10 +239,11 @@
_usrp_n210_r4_fpga_bin = $(BUILT_IMAGES_DIR)/usrp_n210_r4_fpga.bin
_usrp_n210_r4_fpga_bit = $(BUILT_IMAGES_DIR)/bit/usrp_n210_r4_fpga.bit
IMAGES_LIST += $(_usrp_n210_r4_fpga_bin) $(_usrp_n210_r4_fpga_bit)
+USRP2_LIST += $(_usrp_n210_r4_fpga_bin) $(_usrp_n210_r4_fpga_bit)
$(_usrp_n210_r4_fpga_bin): $(GLOBAL_DEPS)
- cd $(_usrp_n210_r4_fpga_dir) && make -f Makefile.N210R4 clean
- cd $(_usrp_n210_r4_fpga_dir) && make -f Makefile.N210R4 bin
+ cd $(_usrp_n210_r4_fpga_dir) && gmake -f Makefile.N210R4 clean
+ cd $(_usrp_n210_r4_fpga_dir) && gmake -f Makefile.N210R4 bin
cp $(_usrp_n210_r4_fpga_dir)/build-N210R4/u2plus.bin $@
$(_usrp_n210_r4_fpga_bit): $(_usrp_n210_r4_fpga_bin)
@@ -248,8 +261,8 @@
IMAGES_LIST += $(_usrp_e100_fpga_bin)
$(_usrp_e100_fpga_bin): $(GLOBAL_DEPS)
- cd $(_usrp_e100_fpga_dir) && make -f Makefile.E100 clean
- cd $(_usrp_e100_fpga_dir) && make -f Makefile.E100 bin
+ cd $(_usrp_e100_fpga_dir) && gmake -f Makefile.E100 clean
+ cd $(_usrp_e100_fpga_dir) && gmake -f Makefile.E100 bin
cp $(_usrp_e100_fpga_dir)/build-E100/u1e.bin $@
endif
@@ -264,8 +277,8 @@
IMAGES_LIST += $(_usrp_e110_fpga_bin)
$(_usrp_e110_fpga_bin): $(GLOBAL_DEPS)
- cd $(_usrp_e110_fpga_dir) && make -f Makefile.E110 clean
- cd $(_usrp_e110_fpga_dir) && make -f Makefile.E110 bin
+ cd $(_usrp_e110_fpga_dir) && gmake -f Makefile.E110 clean
+ cd $(_usrp_e110_fpga_dir) && gmake -f Makefile.E110 bin
cp $(_usrp_e110_fpga_dir)/build-E110/u1e.bin $@
endif
@@ -275,13 +288,19 @@
########################################################################
images: $(IMAGES_LIST)
find $(BUILT_IMAGES_DIR) -type f | xargs chmod -x
- find $(TOP_FPGA_DIR) -name "*.twr" | xargs grep constraint | grep met
+# find $(TOP_FPGA_DIR) -name "*.twr" | xargs grep constraint | grep met
+
+images_usrp1: $(USRP1_LIST)
+ find $(BUILT_IMAGES_DIR) -type f | xargs chmod -x
+
+images_usrp2: $(USRP2_LIST)
+ find $(BUILT_IMAGES_DIR) -type f | xargs chmod -x
package:
mkdir -p $(CMAKE_BUILD_DIR)
cd $(CMAKE_BUILD_DIR) && cmake -DUHD_RELEASE_MODE=OFF ..
- cd $(CMAKE_BUILD_DIR) && cmake -DCPACK_GENERATOR=TGZ .. && make package
- cd $(CMAKE_BUILD_DIR) && cmake -DCPACK_GENERATOR=ZIP .. && make package
+ cd $(CMAKE_BUILD_DIR) && cmake -DCPACK_GENERATOR=TGZ .. && gmake package
+ cd $(CMAKE_BUILD_DIR) && cmake -DCPACK_GENERATOR=ZIP .. && gmake package
clean:
$(RM) -rf $(BUILT_IMAGES_DIR)

15
comms/usrp/pkg-descr
View File

@ -1,15 +0,0 @@
UHD is the "Universal Software Radio Peripheral" (USRP) Hardware Driver. It
works on all major platforms (Linux, Windows, and Mac); and can be built with
GCC, Clang, and MSVC compilers.
The goal of UHD is to provide a host driver and API for current and
future Ettus Research products. Users will be able to use the UHD driver
standalone or with third-party applications such as:
GNU Radio
LabVIEW
Simulink
OpenBTS
WWW: http://ettus-apps.sourcerepo.com/redmine/ettus/projects/uhd/wiki

882
comms/usrp/pkg-plist
View File

@ -1,882 +0,0 @@
bin/uhd_cal_rx_iq_balance
bin/uhd_cal_tx_dc_offset
bin/uhd_cal_tx_iq_balance
bin/uhd_find_devices
bin/uhd_usrp_probe
include/uhd/config.hpp
include/uhd/convert.hpp
include/uhd/deprecated.hpp
include/uhd/device.hpp
include/uhd/device_deprecated.ipp
include/uhd/exception.hpp
include/uhd/property_tree.hpp
include/uhd/property_tree.ipp
include/uhd/stream.hpp
include/uhd/transport/bounded_buffer.hpp
include/uhd/transport/bounded_buffer.ipp
include/uhd/transport/buffer_pool.hpp
include/uhd/transport/if_addrs.hpp
include/uhd/transport/udp_simple.hpp
include/uhd/transport/udp_zero_copy.hpp
include/uhd/transport/usb_control.hpp
include/uhd/transport/usb_device_handle.hpp
include/uhd/transport/usb_zero_copy.hpp
include/uhd/transport/vrt_if_packet.hpp
include/uhd/transport/zero_copy.hpp
include/uhd/types/clock_config.hpp
include/uhd/types/device_addr.hpp
include/uhd/types/dict.hpp
include/uhd/types/dict.ipp
include/uhd/types/io_type.hpp
include/uhd/types/mac_addr.hpp
include/uhd/types/metadata.hpp
include/uhd/types/otw_type.hpp
include/uhd/types/ranges.hpp
include/uhd/types/ref_vector.hpp
include/uhd/types/sensors.hpp
include/uhd/types/serial.hpp
include/uhd/types/stream_cmd.hpp
include/uhd/types/time_spec.hpp
include/uhd/types/tune_request.hpp
include/uhd/types/tune_result.hpp
include/uhd/usrp/dboard_base.hpp
include/uhd/usrp/dboard_eeprom.hpp
include/uhd/usrp/dboard_id.hpp
include/uhd/usrp/dboard_iface.hpp
include/uhd/usrp/dboard_manager.hpp
include/uhd/usrp/gps_ctrl.hpp
include/uhd/usrp/mboard_eeprom.hpp
include/uhd/usrp/multi_usrp.hpp
include/uhd/usrp/subdev_spec.hpp
include/uhd/utils/algorithm.hpp
include/uhd/utils/assert_has.hpp
include/uhd/utils/assert_has.ipp
include/uhd/utils/byteswap.hpp
include/uhd/utils/byteswap.ipp
include/uhd/utils/csv.hpp
include/uhd/utils/gain_group.hpp
include/uhd/utils/images.hpp
include/uhd/utils/log.hpp
include/uhd/utils/msg.hpp
include/uhd/utils/paths.hpp
include/uhd/utils/pimpl.hpp
include/uhd/utils/safe_call.hpp
include/uhd/utils/safe_main.hpp
include/uhd/utils/static.hpp
include/uhd/utils/tasks.hpp
include/uhd/utils/thread_priority.hpp
include/uhd/version.hpp
lib/libuhd.so
lib/libuhd.so.003
lib/libuhd.so.003.004
libdata/pkgconfig/uhd.pc
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share/uhd/examples/benchmark_rate
share/uhd/examples/latency_test
share/uhd/examples/network_relay
share/uhd/examples/rx_ascii_art_dft
share/uhd/examples/rx_multi_samples
share/uhd/examples/rx_samples_to_file
share/uhd/examples/rx_samples_to_udp
share/uhd/examples/rx_timed_samples
share/uhd/examples/test_messages
share/uhd/examples/test_pps_input
share/uhd/examples/tx_bursts
share/uhd/examples/tx_samples_from_file
share/uhd/examples/tx_timed_samples
share/uhd/examples/tx_waveforms
share/uhd/tests/addr_test
share/uhd/tests/buffer_test
share/uhd/tests/byteswap_test
share/uhd/tests/convert_test
share/uhd/tests/dict_test
share/uhd/tests/error_test
share/uhd/tests/gain_group_test
share/uhd/tests/msg_test
share/uhd/tests/property_test
share/uhd/tests/ranges_test
share/uhd/tests/sph_recv_test
share/uhd/tests/sph_send_test
share/uhd/tests/subdev_spec_test
share/uhd/tests/time_spec_test
share/uhd/tests/vrt_test
share/uhd/utils/fx2_init_eeprom
share/uhd/utils/usrp2_card_burner.py
share/uhd/utils/usrp2_card_burner_gui.py
share/uhd/utils/usrp2_recovery.py
share/uhd/utils/usrp_burn_db_eeprom
share/uhd/utils/usrp_burn_mb_eeprom
share/uhd/utils/usrp_n2xx_net_burner.py
share/uhd/utils/usrp_n2xx_net_burner_gui.py
%%USRP1%%share/uhd/fpga/usrp1/rev2/inband_1rxhb_1tx.rbf
%%USRP1%%share/uhd/fpga/usrp1/rev2/inband_2rxhb_2tx.rbf
%%USRP1%%share/uhd/fpga/usrp1/rev2/multi_2rxhb_2tx.rbf
%%USRP1%%share/uhd/fpga/usrp1/rev2/multi_4rx_0tx.rbf
%%USRP1%%share/uhd/fpga/usrp1/rev2/std_2rxhb_2tx.rbf
%%USRP1%%share/uhd/fpga/usrp1/rev2/std_4rx_0tx.rbf
%%USRP1%%share/uhd/fpga/usrp1/rev4/inband_1rxhb_1tx.rbf
%%USRP1%%share/uhd/fpga/usrp1/rev4/inband_2rxhb_2tx.rbf
%%USRP1%%share/uhd/fpga/usrp1/rev4/multi_2rxhb_2tx.rbf
%%USRP1%%share/uhd/fpga/usrp1/rev4/multi_4rx_0tx.rbf
%%USRP1%%share/uhd/fpga/usrp1/rev4/std_2rxhb_2tx.rbf
%%USRP1%%share/uhd/fpga/usrp1/rev4/std_4rx_0tx.rbf
%%USRP1%%share/uhd/images/usrp1_fw.ihx
%%USRP2%%share/uhd/images/usrp_n200_fw.bin
%%USRP1%%share/uhd/images/usrp1_fpga.rbf
%%USRP2%%share/uhd/images/usrp2_fw.bin
%%USRP2%%share/uhd/images/usrp_n210_fw.bin
%%USRP1%%share/uhd/images/usrp1_fpga_4rx.rbf
%%USRP1%%share/uhd/images/usrp_b100_fw.ihx