add chipvault 200211

A project organizer for VHDL and Verilog RTL hardware designs

cad/Makefile

@@ -4,6 +4,7 @@
     SUBDIR += atlc
     SUBDIR += cascade
     SUBDIR += chipmunk
+    SUBDIR += chipvault
     SUBDIR += cider
     SUBDIR += electric
     SUBDIR += felt

cad/chipvault/Makefile

@@ -0,0 +1,28 @@
+# ex:ts=8
+# Ports collection makefile for:	chipvault
+# Date created:			Jan 29, 2003
+# Whom:				ijliao
+#
+# $FreeBSD$
+#
+
+PORTNAME=	chipvault
+PORTVERSION=	200211
+CATEGORIES=	cad
+MASTER_SITES=	http://chipvault.sourceforge.net/
+DISTNAME=	cv.pl
+EXTRACT_SUFX=	.gz
+
+MAINTAINER=	ports@FreeBSD.org
+
+NO_WRKSUBDIR=	yes
+EXTRACT_CMD=	${GZCAT}
+EXTRACT_BEFORE_ARGS=	# empty
+EXTRACT_AFTER_ARGS=	> ${DISTNAME}
+NO_BUILD=	yes
+USE_PERL5_RUN=	yes
+
+do-install:
+	${INSTALL_SCRIPT} ${WRKSRC}/cv.pl ${PREFIX}/bin/cv
+
+.include <bsd.port.mk>

cad/chipvault/distinfo

@@ -0,0 +1 @@
+MD5 (cv.pl.gz) = 1b740c4eb63f8e23b233c429f60b56e7

cad/chipvault/pkg-comment

@@ -0,0 +1 @@
+A project organizer for VHDL and Verilog RTL hardware designs

cad/chipvault/pkg-descr

@@ -0,0 +1,14 @@
+ChipVault is a VHDL and Verilog Chip Design Organization tool which improves
+design efficiency by:
+   - Providing the ability to Navigate and Edit files Hierarchically.
+   - Automatically generating Schematic Component Port views of VHDL and
+     Verilog RTL files.
+   - Automating RTL instantiation and template generation.
+   - Providing Revision Control (designed for HW, not SW development).
+   - Supporting External Tool Hooks (bottom-up vcoms,etc).
+   - Providing an Issue Tracking Log with sorting.
+   - Providing Netlist sorting and hierarchy viewing.
+   - Supporting web-sharing of RTL files (both encrypted and clear).
+   - Fast and Nimble.
+
+WWW: http://chipvault.sourceforge.net/

cad/chipvault/pkg-plist

@@ -0,0 +1 @@
+bin/cv