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add iverilog, a Verilog simulation and synthesis tool

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This commit is contained in:
Ying-Chieh Liao 2001-02-13 11:02:15 +00:00
parent 65d8850cd8
commit 7bf8e1d6ec
Notes: svn2git 2021-03-31 03:12:20 +00:00 
svn path=/head/; revision=38298
6 changed files with 60 additions and 0 deletions
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1
cad/Makefile
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@ -8,6 +8,7 @@
SUBDIR += felt
SUBDIR += geda
SUBDIR += irsim
SUBDIR += iverilog
SUBDIR += kaskade
SUBDIR += magic
SUBDIR += mars

23
cad/iverilog/Makefile Normal file
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# ex:ts=8
# New ports collection makefile for: iverilog
# Date created: Feb 13, 2001
# Whom: Ying-Chieh Liao <ijliao@FreeBSD.org>
#
# $FreeBSD$
#
PORTNAME= iverilog
PORTVERSION= 0.4
CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION}/
DISTNAME= verilog-${PORTVERSION}
MAINTAINER= ijliao@FreeBSD.org
GNU_CONFIGURE= yes
USE_GMAKE= yes
MAN1= iverilog.1
.include <bsd.port.mk>

1
cad/iverilog/distinfo Normal file
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@ -0,0 +1 @@
MD5 (verilog-0.4.tar.gz) = d2b0c7c1480ffb2ad1b440bded97e419

1
cad/iverilog/pkg-comment Normal file
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Icarus Verilog is a Verilog simulation and synthesis tool

15
cad/iverilog/pkg-descr Normal file
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Icarus Verilog is a Verilog simulation and synthesis tool. It
operates as a compiler, compiling source code writen in Verilog
(IEEE-1364) into some target format. For batch simulation, the
compiler can generate C++ code that is compiled and linked with
a run time library (called "vvm") then executed as a command to
run the simulation. For synthesis, the compiler generates netlists
in the desired format.
The compiler proper is intended to parse and elaborate design
descriptions written to the IEEE standard IEEE Std 1364-2000. The
standard proper is due to be release towards the middle of the
year 2000. This is a fairly large and complex standard, so it will
take some time for it to get there, but that's the goal.
WWW: http://www.icarus.com/eda/verilog/

19
cad/iverilog/pkg-plist Normal file
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bin/iverilog
include/ivl_target.h
include/vvm.h
include/vpi_priv.h
include/vvm_func.h
include/vvm_gates.h
include/vvm_nexus.h
include/vvm_signal.h
include/vvm_thread.h
include/vvm_calltf.h
include/vpi_user.h
lib/ivl/ivl
lib/ivl/iverilog.conf
lib/ivl/system.vpi
lib/ivl/ivlpp
lib/ivl/null.tgt
lib/libvvm.a
lib/libvpip.a
@dirrm lib/ivl