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cad/yosys-systemverilog: Add PORTSCOUT tag

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This commit is contained in:
Yuri Victorovich 2023-06-18 14:35:36 -07:00
parent 2675080acc
commit 8914ed49e5
1 changed files with 2 additions and 0 deletions
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cad/yosys-systemverilog/Makefile
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@ -52,6 +52,8 @@ OPTIONS_DEFAULT= TCMALLOC # should be the same TCMALLOC default as in cad/yosys,
TCMALLOC_LDFLAGS= `pkg-config --libs libtcmalloc`
TCMALLOC_LIB_DEPENDS= libtcmalloc.so:devel/google-perftools
PORTSCOUT= ignore:1 # until https://github.com/antmicro/yosys-systemverilog/issues/1798 is resolved
post-extract:
@${CP} ${WRKSRC_yosys}/passes/pmgen/pmgen.py ${WRKSRC}/yosys-f4pga-plugins