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cad/verilator: Add the SystemC dependency

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Also:
* Remove unnecessary patch that has been already applied upstream
* Fix BINARY_ALIAS added for testing
This commit is contained in:
Yuri Victorovich 2020-09-01 03:14:17 +00:00
parent a11b61092f
commit a28dea55f5
Notes: svn2git 2021-03-31 03:12:20 +00:00 
svn path=/head/; revision=547235
2 changed files with 5 additions and 7 deletions
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8
cad/verilator/Makefile
View File

@ -2,19 +2,19 @@
PORTNAME= verilator
DISTVERSION= 4.040
PORTREVISION= 1
CATEGORIES= cad
MASTER_SITES= https://www.veripool.org/ftp/
PATCH_SITES= https://github.com/${PORTNAME}/${PORTNAME}/commit/
PATCHFILES+= 39f16fb155b9e909f919a9d4ae06890395987b16.patch:-p1 # https://github.com/verilator/verilator/pull/2353
MAINTAINER= yuri@FreeBSD.org
COMMENT= Synthesizable Verilog to C++ compiler
LICENSE= GPLv3
LICENSE_FILE= ${WRKSRC}/LICENSE
USES= bison compiler:c++14-lang gmake pathfix perl5 python:test tar:tgz
LIB_DEPENDS= libsystemc.so:devel/systemc
USES= bison compiler:c++14-lang gmake localbase:ldflags pathfix perl5 python:build,test tar:tgz
GNU_CONFIGURE= yes
CONFIGURE_ENV= INSTALL_PROGRAM="${INSTALL_SCRIPT}"

4
cad/verilator/distinfo
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@ -1,5 +1,3 @@
TIMESTAMP = 1597706592
TIMESTAMP = 1598925644
SHA256 (verilator-4.040.tgz) = 6e1574924083922a4eb80ff22eedc866f4ce54e5fd6a34101b6af7aa29e5c0e3
SIZE (verilator-4.040.tgz) = 2720606
SHA256 (39f16fb155b9e909f919a9d4ae06890395987b16.patch) = 266c63d54bc00d4a67163b701a10cf238faf9c21f04e0c8192bd5495ff000b80
SIZE (39f16fb155b9e909f919a9d4ae06890395987b16.patch) = 590