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Code Issues Releases Activity

cad/yosys: update 0.43 → 0.44

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Reported by:	portscout
This commit is contained in:
Yuri Victorovich 2024-08-07 09:57:21 -07:00
parent d4a4ba3070
commit a6386b2152
3 changed files with 14 additions and 4 deletions
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2
cad/yosys/Makefile
View File

@ -1,6 +1,6 @@
PORTNAME= yosys
DISTVERSIONPREFIX= yosys-
DISTVERSION= 0.43
DISTVERSION= 0.44
CATEGORIES= cad
MAINTAINER= yuri@FreeBSD.org

6
cad/yosys/distinfo
View File

@ -1,3 +1,3 @@
TIMESTAMP = 1720600290
SHA256 (YosysHQ-yosys-yosys-0.43_GH0.tar.gz) = e341d7c3712f58787554c28c12c9f4cb5e102f9ff154f5a5e49238c1adfb309f
SIZE (YosysHQ-yosys-yosys-0.43_GH0.tar.gz) = 2808745
TIMESTAMP = 1723002938
SHA256 (YosysHQ-yosys-yosys-0.44_GH0.tar.gz) = 3394b1fdb1c67c362513518d6049ef7db72ba45cca629af22bd52bf46b405ed2
SIZE (YosysHQ-yosys-yosys-0.44_GH0.tar.gz) = 2840442

10
cad/yosys/pkg-plist
View File

@ -109,6 +109,7 @@ bin/yosys-witness
%%DATADIR%%/include/frontends/ast/ast_binding.h
%%DATADIR%%/include/frontends/blif/blifparse.h
%%DATADIR%%/include/kernel/binding.h
%%DATADIR%%/include/kernel/bitpattern.h
%%DATADIR%%/include/kernel/cellaigs.h
%%DATADIR%%/include/kernel/celledges.h
%%DATADIR%%/include/kernel/celltypes.h
@ -197,6 +198,15 @@ bin/yosys-witness
%%DATADIR%%/lattice/latches_map.v
%%DATADIR%%/lattice/lutrams.txt
%%DATADIR%%/lattice/lutrams_map.v
%%DATADIR%%/microchip/LSRAM.txt
%%DATADIR%%/microchip/LSRAM_map.v
%%DATADIR%%/microchip/arith_map.v
%%DATADIR%%/microchip/brams_defs.vh
%%DATADIR%%/microchip/cells_map.v
%%DATADIR%%/microchip/cells_sim.v
%%DATADIR%%/microchip/polarfire_dsp_map.v
%%DATADIR%%/microchip/uSRAM.txt
%%DATADIR%%/microchip/uSRAM_map.v
%%DATADIR%%/mul2dsp.v
%%DATADIR%%/nexus/arith_map.v
%%DATADIR%%/nexus/brams.txt