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Update to 10.2
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parent
67f82eef26
commit
add110fef2
Notes:
svn2git
2021-03-31 03:12:20 +00:00
svn path=/head/; revision=452817
@ -2,9 +2,9 @@
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# $FreeBSD$
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PORTNAME= iverilog
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PORTVERSION= 10.1.1
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PORTVERSION= 10.2
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CATEGORIES= cad
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MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]\.[0-9]$,,}/
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MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v10/
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DISTNAME= verilog-${PORTVERSION}
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MAINTAINER= zeising@FreeBSD.org
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@ -14,8 +14,7 @@ LICENSE= GPLv2
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GNU_CONFIGURE= yes
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CONFIGURE_ARGS= --disable-suffix
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USES= bison gmake
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MAKE_JOBS_UNSAFE= yes
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USES= bison gmake readline
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.include <bsd.port.mk>
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@ -1,3 +1,3 @@
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TIMESTAMP = 1464367614
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SHA256 (verilog-10.1.1.tar.gz) = fdaa75dfe7c58cbc471fc12710ee49b3f32fd6cc055d9181b5190cbcbbd6cada
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SIZE (verilog-10.1.1.tar.gz) = 1684925
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TIMESTAMP = 1508676832
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SHA256 (verilog-10.2.tar.gz) = 96dedbddb12d375edb45a144a926a3ba1e3e138d6598b18e7d79f2ae6de9e500
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SIZE (verilog-10.2.tar.gz) = 1695227
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@ -1,10 +0,0 @@
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--- load_module.cc.orig 2015-08-23 21:41:41 UTC
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+++ load_module.cc
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@@ -21,6 +21,7 @@
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# include "util.h"
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# include "parse_api.h"
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# include "compiler.h"
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+# include <assert.h>
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# include <iostream>
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# include <map>
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# include <cstdlib>
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