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Code Issues Releases Activity

Update to 10.2

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This commit is contained in:
Niclas Zeising 2017-10-24 21:01:15 +00:00
parent 67f82eef26
commit add110fef2
Notes: svn2git 2021-03-31 03:12:20 +00:00 
svn path=/head/; revision=452817
3 changed files with 6 additions and 17 deletions
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7
cad/iverilog/Makefile
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@ -2,9 +2,9 @@
# $FreeBSD$ # $FreeBSD$
PORTNAME= iverilog PORTNAME= iverilog
PORTVERSION= 10.1.1 PORTVERSION= 10.2
CATEGORIES= cad CATEGORIES= cad
MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION:C,\.[0-9]\.[0-9]$,,}/ MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v10/
DISTNAME= verilog-${PORTVERSION} DISTNAME= verilog-${PORTVERSION}
MAINTAINER= zeising@FreeBSD.org MAINTAINER= zeising@FreeBSD.org
@ -14,8 +14,7 @@ LICENSE= GPLv2
GNU_CONFIGURE= yes GNU_CONFIGURE= yes
CONFIGURE_ARGS= --disable-suffix CONFIGURE_ARGS= --disable-suffix
USES= bison gmake
MAKE_JOBS_UNSAFE= yes USES= bison gmake readline
.include <bsd.port.mk> .include <bsd.port.mk>

6
cad/iverilog/distinfo
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@ -1,3 +1,3 @@
TIMESTAMP = 1464367614 TIMESTAMP = 1508676832
SHA256 (verilog-10.1.1.tar.gz) = fdaa75dfe7c58cbc471fc12710ee49b3f32fd6cc055d9181b5190cbcbbd6cada SHA256 (verilog-10.2.tar.gz) = 96dedbddb12d375edb45a144a926a3ba1e3e138d6598b18e7d79f2ae6de9e500
SIZE (verilog-10.1.1.tar.gz) = 1684925 SIZE (verilog-10.2.tar.gz) = 1695227

10
cad/iverilog/files/patch-load_module.cc
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@ -1,10 +0,0 @@
--- load_module.cc.orig 2015-08-23 21:41:41 UTC
+++ load_module.cc
@@ -21,6 +21,7 @@
# include "util.h"
# include "parse_api.h"
# include "compiler.h"
+# include <assert.h>
# include <iostream>
# include <map>
# include <cstdlib>