mirror of
https://git.FreeBSD.org/ports.git
synced 2024-11-19 00:13:33 +00:00
lang/silq: update to latest development version
This commit is contained in:
Stefan Eßer
parent
2f3e4d0460
commit
c1c94249f5
@ -1,6 +1,5 @@
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PORTNAME= silq
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PORTVERSION= 20220224
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PORTREVISION= 2
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PORTVERSION= 20230412
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CATEGORIES= lang math science
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DIST_SUBDIR= silq
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@ -19,9 +18,9 @@ BUILD_DEPENDS= ldmd2:lang/ldc \
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USE_GITHUB= yes
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GH_TUPLE= eth-sri:silq:afaf865 \
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tgehr:ast:d2f25fb:ast/ast \
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tgehr:util:7e9f0ce:util/util
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GH_TUPLE= eth-sri:silq:e9750cb \
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tgehr:ast:072796e:ast/ast \
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tgehr:util:a4532a4:util/util
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OPTIONS_DEFINE= EXAMPLES
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@ -1,7 +1,7 @@
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TIMESTAMP = 1650392986
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SHA256 (silq/eth-sri-silq-20220224-afaf865_GH0.tar.gz) = 37e8ad58f4ac0b60f510af188cc167e4e8ef767f949b60f66fd7c4b339d6dc8c
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SIZE (silq/eth-sri-silq-20220224-afaf865_GH0.tar.gz) = 167609
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SHA256 (silq/tgehr-ast-d2f25fb_GH0.tar.gz) = bfec0dd622f726fd4a8d0e05967bcbb7578468c33d1295aa4d82bf540f459c83
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SIZE (silq/tgehr-ast-d2f25fb_GH0.tar.gz) = 75363
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SHA256 (silq/tgehr-util-7e9f0ce_GH0.tar.gz) = f73af612a6aa14c966cc46f392394d8c43b90ecf8c0be0c44b509cc07a7e949f
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SIZE (silq/tgehr-util-7e9f0ce_GH0.tar.gz) = 9455
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TIMESTAMP = 1681284932
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SHA256 (silq/eth-sri-silq-20230412-e9750cb_GH0.tar.gz) = f6e201f4fb1e639f7d8df9e018dbf79bda6e8a55f431801385abf6070f37e01e
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SIZE (silq/eth-sri-silq-20230412-e9750cb_GH0.tar.gz) = 187476
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SHA256 (silq/tgehr-ast-072796e_GH0.tar.gz) = ea5a472d6b2f7defbce624879abc9d5d87f3b3fb3ce5634172567e29b132567a
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SIZE (silq/tgehr-ast-072796e_GH0.tar.gz) = 87630
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SHA256 (silq/tgehr-util-a4532a4_GH0.tar.gz) = 667a992d464e88a1aec85efc5718bf309786b62f2e120d02f3f5f20088e1d1ad
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SIZE (silq/tgehr-util-a4532a4_GH0.tar.gz) = 9975
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@ -1,18 +1,26 @@
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bin/silq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/argMatchSubtyping1.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/argMatchSubtyping2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/arrayAddAssign.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/arrayConcatReassign.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/arrayConsumeIndexReplace.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/arrayElements.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/arrayEntryDup.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/asinQ.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/asinQ2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/assertTypeError.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/assignError.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/assignFromArray.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/assignQcontrol.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/assignQuantumArray.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/badControlUncomp.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/badForget.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/badForget2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/badIndexReplacement.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/badIndexReplacement2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/badProdType.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/badReverse.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/badSliceReplacement.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/badSliceReplacement2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/badTypes.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/bernsteinVazirani.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/bernsteinVazirani2.slq
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@ -20,9 +28,25 @@ bin/silq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/bug.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/builtInToPrelude.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureConst.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureConsumes.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureIndexReplacement.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureIndexReplacement2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureIndexReplacement3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureIndexReplacement4.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureIndexReplacement5.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureIndexReplacement6.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureIndexReplacement7.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureShadow.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/captureTwice.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalArrayAliasing.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalAssign.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalForget1.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalForget2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalForget3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalForget3_1.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalForget4.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalForget5.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalForgetBad.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalHadamard.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalQfree1.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/classicalQfree2.slq
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@ -91,8 +115,11 @@ bin/silq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/c2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/c3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/c3_2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/c3_3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/d1.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/d2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/d2_bad.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/d2_todo.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/d3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/d4.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/contest/d5.slq
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@ -104,18 +131,28 @@ bin/silq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/warmup/u2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/codeforces/winter19/warmup/u3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceAssign.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceBoolToInt.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceFunction.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceInt.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceIntLengthMismatch.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceIntToNat.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceIntToVecLengthMismatch.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceNegativeNatural.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceReal.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceTupleLengthMismatch.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceVecToIntLengthMismatch.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceVector.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/coerceVectorLengthMismatch.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/communicationGame.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/concatJoin.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/condTwoAssertFalse.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/conditionalMeasurement.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/conditionalMeasurement2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/constBlockAssign.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/constBlockCapture.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/consumeAssign.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/consumeDepTypeVar.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/consumingSquare.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/consumingVector.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/conv.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/convertForget.slq
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@ -125,13 +162,31 @@ bin/silq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/convertNatToInt.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/convertTuple.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/convertVectors.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depCond1.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depCond2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depCond3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depCond4.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depConsume1.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depConsume2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depConsume3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depIndexReplace.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depIndexReplace2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest4.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest5.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest5_1.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest5_2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest5_3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest5_4.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depTest6.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depType.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depType2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depType2_1.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depType3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/depType4.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/dependencyLoop1.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/dependencyLoop2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/detectZero.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/distinguish0H0.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/distinguish0H0_2.slq
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@ -164,6 +219,16 @@ bin/silq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/extendTruncateError.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/fib.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/fib2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor1.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor10.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor4.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor5.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor6.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor7.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor8.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/firstClassTypeConstructor9.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/flipAll.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/for.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/forStep.slq
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@ -193,10 +258,12 @@ bin/silq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/functionBodyParseError.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/genericAddition.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/genericReverse.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/genericSubtyping1.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/grover.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/grover2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/groverDiffusion.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/hIndex.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/hideAssign.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/hidingIndexReplacement.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ifError.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ifFalseReassign.slq
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@ -205,7 +272,15 @@ bin/silq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ifSuperposition3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/implicitDup.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/implicitDupLifted.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/inOwnType.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/incompatibleFunDef.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexAssignDep.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds10.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds11.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds12.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds13.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds14.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds4.slq
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@ -214,7 +289,20 @@ bin/silq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds7.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds8.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexOutOfBounds9.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplace1.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplace2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplace3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplace4.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplace5.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplace6.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplaceAlias1.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplaceConstAccess.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplaceConsume.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplaceError2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplaceErrorRhs.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplaceId.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexReplaceIfFunctionCall.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/indexRewriteContext.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/innerProduct.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/innerProduct2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/intUintBoolConversion.slq
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@ -226,27 +314,49 @@ bin/silq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ite2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ite3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ite4.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ite5.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ite6.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/iteLhs.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/iteLhs2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/iverson.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/lambdaEq.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/lambdaLhs.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/lengthConstFold.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/lengthMismatch.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/liftedAssign.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/liftedConstArg.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/localVariableInFunctionReturnTypeError.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/logicShortCircuit.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/loopFixedPoint1.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/loopFixedPoint2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/loopFixedPoint3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/loopFixedPoint4.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/loopFixedPoint5.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/loopFixedPoint6.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/majorityOracle.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/makeWPower2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/map1.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/map2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/map3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/mapH.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/mapH2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/mapH3.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/matchCoerce.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/measureArray.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/measureFun.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/measureFun2.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/measureHadamard.slq
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%%PORTEXAMPLES%%%%EXAMPLESDIR%%/measureReversePhase.slq
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||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/measureUint.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/measureVector.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/mergeImplicitForget.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/mfreeImplicitForget.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/mixed.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/mixed2.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/mixed3.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/mixed4.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/mixed5.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiDimReplace.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiForget.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiIndex1.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiIndex2.slq
|
||||
@ -254,12 +364,18 @@ bin/silq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiReplace.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/multiResultIndexReplace.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/mustConsumeNonLifted.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestInf.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestedCapture.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestedClosure.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestedGlobal.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestedIndexReplace.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestedMeasure.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestedReplace.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/nestedTupleMatch.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/newForLoopRangeSyntax.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/noImplicitForget.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/noLengthAssign.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/noQnumericJoin.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/opAssignReverse.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/paramNotConsumedError.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/parameterizedSimulation.slq
|
||||
@ -287,9 +403,16 @@ bin/silq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/print.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/qft.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/qftPretty.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/qnumeric1.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/qnumericError1.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/qnumericError2.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/qnumericError3.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/quantumBitNotMinus.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/quantumControlClassicalAssignment.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/quantumIfClassicalUpdate.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/quantumIfClassicalUpdate1.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/quantumIfClassicalUpdate2.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/quantumIfClassicalUpdate3.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/quantumReplace.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/quid-updates.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/rationalPhase.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reassignArrayLength.slq
|
||||
@ -302,6 +425,7 @@ bin/silq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/repeat.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/repeat100.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/repeatUntil.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceClassical.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndex.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti0.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti1.slq
|
||||
@ -311,13 +435,16 @@ bin/silq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti5.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti6.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti7.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/replaceIndexMulti8.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/ret2.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/retClosure.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/retPi.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reuseCapturedName.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseArithmetic.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseDependent.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseEarlyReturn.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseFlatten.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseGeneric.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseH.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseH0.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseH2.slq
|
||||
@ -335,9 +462,15 @@ bin/silq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseRotX.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseRotY.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseRotZ.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSingletonArg.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare1.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare2.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare3.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare4.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare5.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare6.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSquare7.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseSubtype.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseToW.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/reverseX.slq
|
||||
@ -346,8 +479,18 @@ bin/silq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/shor.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/sinQ.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/singletonVectorHadamard.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/sliceReplacement.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/specialReverseTypeChecking.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/splitArrayConst.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/squareFunctionLhs.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/squareFunctionLhsConst.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/squareFunctionLhsConst2.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/squareFunctionLhsConst3.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/squareFunctionReplace.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/strongUpdates1.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/strongUpdates2.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/subAssign1.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/subAssign2.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/subtyping.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/sumArray.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/sumIota.slq
|
||||
@ -355,10 +498,12 @@ bin/silq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapArray2.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapArray3.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapArray4.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapArray5.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapClosures.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapDiffArrays.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapEmptyIf.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapInt.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapNoSwap.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapVarWithComponent.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/swapVarWithComponent2.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/teleportation.slq
|
||||
@ -393,20 +538,29 @@ bin/silq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/testUnsafeCaptureConst2.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/testUnsafeCaptureConst3.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/testUnsafeCaptureConst4.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/tf.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/tf_orig.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/thirds.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/transpose.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/tupleArray.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/tupleComp.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/tupleConversion.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeAlias.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeConstBlockCapture.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeConstBlockForget.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeError.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeError2.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeFunCall.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/typeFunCallCoerce.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/uncomputeOnArrayAssignment.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/undefLhs.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/unicodeLoc.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/unitParamClosureArray.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/unitRedefinition.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/unrealizableError.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/vectorConv.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/vectorLength.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/vectorReverse.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/vectorToArray.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/warning.slq
|
||||
%%PORTEXAMPLES%%%%EXAMPLESDIR%%/while.slq
|
||||
|
||||
Loading…
Reference in New Issue
Block a user