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This commit is contained in:
Antoine Brodin 2014-01-20 20:30:18 +00:00
parent df7f31d156
commit d507da2f32
Notes: svn2git 2021-03-31 03:12:20 +00:00 
svn path=/head/; revision=340465
1 changed files with 4 additions and 4 deletions
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8
cad/chipvault/Makefile
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@ -9,7 +9,7 @@ DISTNAME= cv.pl
EXTRACT_SUFX= .gz
MAINTAINER= ports@FreeBSD.org
COMMENT= A project organizer for VHDL and Verilog RTL hardware designs
COMMENT= Project organizer for VHDL and Verilog RTL hardware designs
NO_WRKSUBDIR= yes
EXTRACT_CMD= ${GZCAT}
@ -17,11 +17,11 @@ EXTRACT_BEFORE_ARGS= # empty
EXTRACT_AFTER_ARGS= > ${DISTNAME}
NO_BUILD= yes
PLIST_FILES= bin/cv
USES= perl5
USES= perl5 shebangfix
USE_PERL5= run
SHEBANG_FILES= cv.pl
NO_STAGE= yes
do-install:
${INSTALL_SCRIPT} ${WRKSRC}/cv.pl ${PREFIX}/bin/cv
${INSTALL_SCRIPT} ${WRKSRC}/cv.pl ${STAGEDIR}${PREFIX}/bin/cv
.include <bsd.port.mk>