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https://git.FreeBSD.org/ports.git
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security/nss: update to 3.46
Changes: https://developer.mozilla.org/docs/Mozilla/Projects/NSS/NSS_3.46_release_notes Changes: https://hg.mozilla.org/projects/nss/shortlog/NSS_3_46_RTM ABI: https://abi-laboratory.pro/tracker/timeline/nss/
This commit is contained in:
Jan Beich
parent
6361a74fa5
commit
d7b9bf2b8b
Notes:
svn2git
2021-03-31 03:12:20 +00:00
svn path=/head/; revision=510302
@ -32,7 +32,7 @@ PLIST_SUB+= CERTDIR=${CERTDIR}
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# !!! Please DO NOT submit patches for new version until it has !!!
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# !!! been committed there first. !!!
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# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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VERSION_NSS= 3.45
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VERSION_NSS= 3.46
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#NSS_SUFFIX= -with-ckbi-1.98
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CERTDATA_TXT_PATH= nss-${VERSION_NSS}/nss/lib/ckfw/builtins/certdata.txt
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BUNDLE_PROCESSOR= MAca-bundle.pl
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@ -1,3 +1,3 @@
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TIMESTAMP = 1562342551
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SHA256 (nss-3.45.tar.gz) = 112f05223d1fde902c170966bfc6f011b24a838be16969b110ecf2bb7bc24e8b
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SIZE (nss-3.45.tar.gz) = 76017462
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TIMESTAMP = 1567179992
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SHA256 (nss-3.46.tar.gz) = 6b699649d285602ba258a4b0957cb841eafc94eff5735a9da8da0adbb9a10cef
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SIZE (nss-3.46.tar.gz) = 76417155
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@ -2,8 +2,7 @@
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# $FreeBSD$
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PORTNAME= nss
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PORTVERSION= 3.45
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PORTREVISION= 2
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PORTVERSION= 3.46
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CATEGORIES= security
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MASTER_SITES= MOZILLA/security/${PORTNAME}/releases/${DISTNAME:tu:C/[-.]/_/g}_RTM/src
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@ -1,3 +1,3 @@
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TIMESTAMP = 1562342551
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SHA256 (nss-3.45.tar.gz) = 112f05223d1fde902c170966bfc6f011b24a838be16969b110ecf2bb7bc24e8b
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SIZE (nss-3.45.tar.gz) = 76017462
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TIMESTAMP = 1567179992
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SHA256 (nss-3.46.tar.gz) = 6b699649d285602ba258a4b0957cb841eafc94eff5735a9da8da0adbb9a10cef
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SIZE (nss-3.46.tar.gz) = 76417155
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@ -2,7 +2,7 @@ Detect ARM CPU features on FreeBSD.
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elf_aux_info is similar to getauxval but is nop on aarch64.
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--- lib/freebl/blinit.c.orig 2019-07-05 16:02:31 UTC
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--- lib/freebl/blinit.c.orig 2019-08-30 15:46:32 UTC
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+++ lib/freebl/blinit.c
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@@ -96,8 +96,8 @@ CheckX86CPUSupport()
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#ifndef __has_include
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@ -36,15 +36,15 @@ elf_aux_info is similar to getauxval but is nop on aarch64.
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// Defines from hwcap.h in Linux kernel - ARM64
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#ifndef HWCAP_AES
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#define HWCAP_AES (1 << 3)
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@@ -137,6 +144,7 @@ CheckARMSupport()
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{
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@@ -138,6 +145,7 @@ CheckARMSupport()
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char *disable_arm_neon = PR_GetEnvSecure("NSS_DISABLE_ARM_NEON");
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char *disable_hw_aes = PR_GetEnvSecure("NSS_DISABLE_HW_AES");
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char *disable_pmull = PR_GetEnvSecure("NSS_DISABLE_PMULL");
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+#if defined(__linux__)
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if (getauxval) {
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long hwcaps = getauxval(AT_HWCAP);
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arm_aes_support_ = hwcaps & HWCAP_AES && disable_hw_aes == NULL;
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@@ -144,6 +152,14 @@ CheckARMSupport()
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@@ -145,6 +153,14 @@ CheckARMSupport()
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arm_sha1_support_ = hwcaps & HWCAP_SHA1;
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arm_sha2_support_ = hwcaps & HWCAP_SHA2;
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}
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@ -52,14 +52,14 @@ elf_aux_info is similar to getauxval but is nop on aarch64.
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+ uint64_t id_aa64isar0;
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+ id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
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+ arm_aes_support_ = ID_AA64ISAR0_AES(id_aa64isar0) >= ID_AA64ISAR0_AES_BASE && disable_hw_aes == NULL;
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+ arm_pmull_support_ = ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL;
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+ arm_pmull_support_ = ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL && disable_pmull == NULL;
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+ arm_sha1_support_ = ID_AA64ISAR0_SHA1(id_aa64isar0) == ID_AA64ISAR0_SHA1_BASE;
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+ arm_sha2_support_ = ID_AA64ISAR0_SHA2(id_aa64isar0) >= ID_AA64ISAR0_SHA2_BASE;
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+#endif /* defined(__linux__) */
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/* aarch64 must support NEON. */
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arm_neon_support_ = disable_arm_neon == NULL;
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}
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@@ -186,7 +202,7 @@ GetNeonSupport()
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@@ -187,7 +203,7 @@ GetNeonSupport()
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// If no getauxval, compiler generate NEON instruction by default,
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// we should allow NOEN support.
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return PR_TRUE;
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@ -68,7 +68,7 @@ elf_aux_info is similar to getauxval but is nop on aarch64.
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// Android's cpu-features.c detects features by the following logic
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//
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// - Call getauxval(AT_HWCAP)
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@@ -200,6 +216,10 @@ GetNeonSupport()
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@@ -201,6 +217,10 @@ GetNeonSupport()
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if (getauxval) {
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return (getauxval(AT_HWCAP) & HWCAP_NEON);
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}
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@ -79,7 +79,7 @@ elf_aux_info is similar to getauxval but is nop on aarch64.
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#endif /* defined(__ARM_NEON) || defined(__ARM_NEON__) */
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return PR_FALSE;
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}
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@@ -208,6 +228,7 @@ void
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@@ -249,6 +269,7 @@ void
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CheckARMSupport()
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{
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char *disable_hw_aes = PR_GetEnvSecure("NSS_DISABLE_HW_AES");
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@ -87,10 +87,17 @@ elf_aux_info is similar to getauxval but is nop on aarch64.
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if (getauxval) {
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// Android's cpu-features.c uses AT_HWCAP2 for newer features.
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// AT_HWCAP2 is implemented on newer devices / kernel, so we can trust
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@@ -216,6 +237,14 @@ CheckARMSupport()
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@@ -257,13 +278,19 @@ CheckARMSupport()
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// AT_HWCAP2 isn't supported by glibc or Linux kernel, getauxval will
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// returns 0.
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long hwcaps = getauxval(AT_HWCAP2);
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-#ifdef __linux__
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if (!hwcaps) {
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// Some ARMv8 devices may not implement AT_HWCAP2. So we also
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// read /proc/cpuinfo if AT_HWCAP2 is 0.
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hwcaps = ReadCPUInfoForHWCAP2();
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}
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-#endif
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+#elif defined(__FreeBSD__) && defined(HAVE_ELF_AUX_INFO)
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+ unsigned long hwcaps = 0;
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+ elf_aux_info(AT_HWCAP2, &hwcaps, sizeof(hwcaps));
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@ -8,6 +8,6 @@
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DEFINES += -UDEBUG -DNDEBUG
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else
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- OPTIMIZER += -g
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USERNAME := $(shell whoami)
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USERNAME := $(subst -,_,$(USERNAME))
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DEFINES += -DDEBUG -UNDEBUG -DDEBUG_$(USERNAME)
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DEFINES += -DDEBUG -UNDEBUG
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endif
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@ -2,23 +2,23 @@ qemu:handle_cpu_signal received signal outside vCPU context
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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=240037
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--- lib/freebl/blinit.c.orig 2019-07-05 16:02:31 UTC
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--- lib/freebl/blinit.c.orig 2019-08-30 15:46:32 UTC
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+++ lib/freebl/blinit.c
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@@ -153,12 +153,14 @@ CheckARMSupport()
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@@ -154,12 +154,14 @@ CheckARMSupport()
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arm_sha2_support_ = hwcaps & HWCAP_SHA2;
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}
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#elif defined(__FreeBSD__)
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- uint64_t id_aa64isar0;
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- id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
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- arm_aes_support_ = ID_AA64ISAR0_AES(id_aa64isar0) >= ID_AA64ISAR0_AES_BASE && disable_hw_aes == NULL;
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- arm_pmull_support_ = ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL;
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- arm_pmull_support_ = ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL && disable_pmull == NULL;
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- arm_sha1_support_ = ID_AA64ISAR0_SHA1(id_aa64isar0) == ID_AA64ISAR0_SHA1_BASE;
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- arm_sha2_support_ = ID_AA64ISAR0_SHA2(id_aa64isar0) >= ID_AA64ISAR0_SHA2_BASE;
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+ if (!PR_GetEnvSecure("QEMU_EMULATING")) {
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+ uint64_t id_aa64isar0;
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+ id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
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+ arm_aes_support_ = ID_AA64ISAR0_AES(id_aa64isar0) >= ID_AA64ISAR0_AES_BASE && disable_hw_aes == NULL;
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+ arm_pmull_support_ = ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL;
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+ arm_pmull_support_ = ID_AA64ISAR0_AES(id_aa64isar0) == ID_AA64ISAR0_AES_PMULL && disable_pmull == NULL;
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+ arm_sha1_support_ = ID_AA64ISAR0_SHA1(id_aa64isar0) == ID_AA64ISAR0_SHA1_BASE;
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+ arm_sha2_support_ = ID_AA64ISAR0_SHA2(id_aa64isar0) >= ID_AA64ISAR0_SHA2_BASE;
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+ }
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