mirror of
https://git.FreeBSD.org/ports.git
synced 2024-10-18 19:49:40 +00:00
New port: cad/abc: System for sequential synthesis and verification
PR: 227254 Submitted by: Christian Krämer <uddka@student.kit.edu>
This commit is contained in:
parent
3c6b0e968b
commit
e715def410
Notes:
svn2git
2021-03-31 03:12:20 +00:00
svn path=/head/; revision=468187
@ -4,6 +4,7 @@
|
||||
COMMENT = CAD tools
|
||||
|
||||
SUBDIR += NASTRAN-95
|
||||
SUBDIR += abc
|
||||
SUBDIR += admesh
|
||||
SUBDIR += adms
|
||||
SUBDIR += alliance
|
||||
|
48
cad/abc/Makefile
Normal file
48
cad/abc/Makefile
Normal file
@ -0,0 +1,48 @@
|
||||
# $FreeBSD$
|
||||
|
||||
PORTNAME= abc
|
||||
DISTVERSION= g20180420
|
||||
CATEGORIES= cad
|
||||
|
||||
MAINTAINER= uddka@student.kit.edu
|
||||
COMMENT= System for sequential synthesis and verification
|
||||
|
||||
LICENSE= MIT
|
||||
LICENSE_FILE= ${WRKSRC}/copyright.txt
|
||||
|
||||
USES= gmake localbase:ldflags
|
||||
USE_GITHUB= yes
|
||||
GH_ACCOUNT= berkeley-abc
|
||||
GH_TAGNAME= 0e15e4d
|
||||
USE_LDCONFIG= yes
|
||||
|
||||
MAKE_ENV= ABC_USE_STDINT_H=1 ABC_MAKE_VERBOSE=1
|
||||
CFLAGS+= -fPIC
|
||||
CXXFLAGS+= -fPIC
|
||||
|
||||
PLIST_FILES= bin/${PORTNAME} lib/lib${PORTNAME}.so
|
||||
|
||||
OPTIONS_DEFINE= DEBUG DOCS READLINE THREADS
|
||||
OPTIONS_DEFAULT= READLINE THREADS
|
||||
|
||||
READLINE_USES= readline
|
||||
READLINE_MAKE_ENV= ABC_READLINE_LIBRARIES="-L${LOCALBASE}/lib -lreadline"
|
||||
READLINE_MAKE_ENV_OFF= ABC_USE_NO_READLINE=1
|
||||
|
||||
THREADS_MAKE_ENV_OFF= ABC_USE_NO_PTHREADS=1
|
||||
|
||||
PORTDOCS= README.md readmeaig
|
||||
|
||||
post-build:
|
||||
cd ${WRKSRC} && ${SETENV} ${MAKE_ENV} ${MAKE_CMD} ${MAKE_ARGS} ABC_USE_PIC=1 lib${PORTNAME}.so
|
||||
|
||||
do-install:
|
||||
${INSTALL_PROGRAM} ${WRKSRC}/${PORTNAME} ${STAGEDIR}${PREFIX}/bin
|
||||
${INSTALL_PROGRAM} ${WRKSRC}/lib${PORTNAME}.so ${STAGEDIR}${PREFIX}/lib
|
||||
|
||||
do-install-DOCS-on:
|
||||
@${MKDIR} ${STAGEDIR}${DOCSDIR}
|
||||
${INSTALL_DATA} ${WRKSRC}/README.md ${STAGEDIR}${DOCSDIR}
|
||||
${INSTALL_DATA} ${WRKSRC}/readmeaig ${STAGEDIR}${DOCSDIR}
|
||||
|
||||
.include <bsd.port.mk>
|
3
cad/abc/distinfo
Normal file
3
cad/abc/distinfo
Normal file
@ -0,0 +1,3 @@
|
||||
TIMESTAMP = 1524554306
|
||||
SHA256 (berkeley-abc-abc-g20180420-0e15e4d_GH0.tar.gz) = ec291913390100d8b91264cba754fdf00274516d5f81d8b6ae2838d4489d0384
|
||||
SIZE (berkeley-abc-abc-g20180420-0e15e4d_GH0.tar.gz) = 5591634
|
18
cad/abc/files/patch-Makefile
Normal file
18
cad/abc/files/patch-Makefile
Normal file
@ -0,0 +1,18 @@
|
||||
--- Makefile.orig 2018-03-30 08:04:05 UTC
|
||||
+++ Makefile
|
||||
@@ -1,6 +1,4 @@
|
||||
|
||||
-CC := gcc
|
||||
-CXX := g++
|
||||
LD := $(CXX)
|
||||
|
||||
MSG_PREFIX ?=
|
||||
@@ -52,8 +50,6 @@ endif
|
||||
|
||||
ARCHFLAGS := $(ARCHFLAGS)
|
||||
|
||||
-OPTFLAGS ?= -g -O
|
||||
-
|
||||
CFLAGS += -Wall -Wno-unused-function -Wno-write-strings -Wno-sign-compare $(ARCHFLAGS)
|
||||
ifneq ($(findstring arm,$(shell uname -m)),)
|
||||
CFLAGS += -DABC_MEMALIGN=4
|
18
cad/abc/files/patch-src_misc_util_abc__global.h
Normal file
18
cad/abc/files/patch-src_misc_util_abc__global.h
Normal file
@ -0,0 +1,18 @@
|
||||
--- src/misc/util/abc_global.h.orig 2018-04-10 14:33:45 UTC
|
||||
+++ src/misc/util/abc_global.h
|
||||
@@ -97,6 +97,15 @@ ABC_NAMESPACE_HEADER_START
|
||||
////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifdef ABC_USE_STDINT_H
|
||||
+
|
||||
+#ifndef __STDC_LIMIT_MACROS
|
||||
+ #define __STDC_LIMIT_MACROS
|
||||
+#endif
|
||||
+
|
||||
+#ifndef __STDC_CONSTANT_MACROS
|
||||
+ #define __STDC_CONSTANT_MACROS
|
||||
+#endif
|
||||
+
|
||||
// If there is stdint.h, assume this is a reasonably-modern platform that
|
||||
// would also have stddef.h and limits.h
|
||||
#include <limits.h>
|
13
cad/abc/pkg-descr
Normal file
13
cad/abc/pkg-descr
Normal file
@ -0,0 +1,13 @@
|
||||
ABC is a growing software system for synthesis and verification of binary
|
||||
sequential logic circuits appearing in synchronous hardware designs. ABC
|
||||
combines scalable logic optimization based on And-Inverter Graphs (AIGs),
|
||||
optimal-delay DAG-based technology mapping for look-up tables and standard
|
||||
cells, and innovative algorithms for sequential synthesis and verification.
|
||||
|
||||
ABC provides an experimental implementation of these algorithms and a
|
||||
programming environment for building similar applications. Future development
|
||||
will focus on improving the algorithms and making most of the packages
|
||||
stand-alone. This will allow the user to customize ABC for their needs as if
|
||||
it were a tool-box rather than a complete tool.
|
||||
|
||||
WWW: https://people.eecs.berkeley.edu/~alanmi/abc/
|
Loading…
Reference in New Issue
Block a user