4 Commits

Author	SHA1	Message	Date
Mark Linimon	0d3b4868e7	Fix build on gcc-based architectures: ... configure: error: the c++ compiler appears to not support C++11. Approved by: portmgr (tier-2 blanket)	2019-03-13 05:24:21 +00:00
Steve Wills	250d86f4fc	cad/verilator: remove unnecessary BUILD_DEPENDS ... PR: 235053 Submitted by: John Hein <jcfyecrayz@liamekaens.com> Approved by: Kevin Zheng <kevinz5000@gmail.com> (maintainer)	2019-01-27 12:34:34 +00:00
Steve Wills	1418f410db	cad/verilator: update to 4.008 ... PR: 235228 Approved by: kevinz5000@gmail.com (maintainer)	2019-01-27 12:25:31 +00:00
Steve Wills	5eee19a826	cad/verilator: create port ... Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. WWW: https://www.veripool.org/projects/verilator/wiki/Intro PR: 230761 Submitted by: Kevin Zheng <kevinz5000@gmail.com>	2019-01-17 23:27:11 +00:00