Michael Zhilin
9784fb237c
cad/libbgcode: new port
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It is required by PrusaSlicer 2.7+. This port provides library and
binary to work with g-code (read/write/convert)
Reported by: Teodor Sigaev <teodorsigaev@gmail.com>
Reviewed by: lwhsu (mentor)
Sponsored by: Postgres Professional
Differential Revision: https://reviews.freebsd.org/D44257
2024-03-28 22:31:42 +03:00
Yuri Victorovich
45581a7943
cad/symbiyosys: New port: SymbiYosys (sby): Front-end for Yosys-based formal verification flows
2024-01-10 21:09:39 -08:00
Yuri Victorovich
88ab25bebe
cad/apio: New port: Open source ecosystem for open FPGA boards
2024-01-06 00:06:40 -08:00
Muhammad Moinur Rahman
af349ed901
cad/jspice3: Remove expired port
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2023-12-31 cad/jspice3: BROKEN for more than 2 years on all supported versions after the EOL of 12
2023-12-31 01:06:12 +01:00
Thierry Thomas
fd8e54173e
cad/freehdl: resurrect
2023-11-21 21:09:59 +01:00
Rene Ladan
000390a6e4
cad/freehdl: Remove expired port
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2023-11-21 cad/freehdl: Upstream vaporized and SF site do not have dists anymore
2023-11-21 15:09:12 +01:00
Nico Sonack
7e4f2be406
cad/yosys-ghdl-plugin: Add new port
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This allows performing synthesis of VHDL using ghdl with yosys.
Signed-off-by: Nico Sonack <nsonack@herrhotzenplotz.de>
PR: 274243
2023-10-19 03:07:29 -04:00
Muhammad Moinur Rahman
7678c45899
cad/py-ocp: Remove expired port
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2023-03-21 cad/py-ocp: Broken since 2021
2023-09-11 08:17:01 +02:00
Muhammad Moinur Rahman
5d3f3b6f3a
cad/py-cadquery: Remove expired port
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2023-06-21 cad/py-cadquery: Depends on exppired cad/py-ocp
2023-09-01 19:16:16 +02:00
Muhammad Moinur Rahman
7e176bb56d
cad/py-cq-editor: Remove expired port
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2023-06-21 cad/py-cq-editor: Depends on expiring cad/py-cadquery
2023-09-01 19:16:16 +02:00
Yuri Victorovich
8784bcc975
cad/py-gdstk: New port: Library for creation and manipulation of GDSII and OASIS files
2023-08-28 09:53:22 -07:00
Yuri Victorovich
a0b1e485fa
cad/gdstk: New port: C++ library for creation and manipulation of GDSII and OASIS files
2023-08-28 01:47:12 -07:00
Yuri Victorovich
9c44a991eb
cad/py-amaranth: New port: Amaranth hardware definition language
2023-07-28 00:45:19 -07:00
Yuri Victorovich
467da2633e
cad/py-pyvcd: New port: Python VCD file support
2023-07-27 23:03:50 -07:00
Thomas Zander
4dd0155e8e
cad/qspeakers: Add new port
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QSpeakers is an open source DIY (do it yourself) speakers enclosure
design software written in C++ with Qt for the UI. This program
simulates common acoustical enclosures behaviour in the mean to help
users to design their own loudspeaker systems.
2023-06-21 10:04:29 +02:00
Yuri Victorovich
2fde22d5d0
cad/yosys-systemverilog: New port: SystemVerilog support for Yosys
2023-06-06 14:10:58 -07:00
Muhammad Moinur Rahman
6394edf1f9
cad/NASTRAN-95: Remove expired port:
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2023-03-20 cad/NASTRAN-95: Broken since 2020
2023-03-19 18:51:42 -05:00
Yuri Victorovich
b676735c11
cad/gdscpp: New port: C++ library to create and read GDSII file
2023-03-02 15:19:12 -08:00
Yuri Victorovich
30997c2f49
cad/ghdl: Re-add port: GNU VHDL simulator
2023-02-23 12:45:51 -08:00
Yuri Victorovich
f94ead8bc8
cad/hs-verismith: New port: Verilog fuzzer
2023-02-17 01:11:28 -08:00
Yuri Victorovich
0ad876d5fd
cad/py-cocotb: New port: Coroutine based cosimulation library for writing VHDL and Verilog
2023-02-03 22:58:53 -08:00
Yuri Victorovich
cdfc8f759d
cad/antimony: New port: CAD from a parallel universe
2023-01-16 13:07:26 -08:00
Yuri Victorovich
d726e22a21
cad/silice: New port: Language that simplifies prototyping and writing algorithms for FPGAs
2023-01-08 01:40:50 -08:00
Yuri Victorovich
f8bbe9d10a
cad/py-edalize: New port: Library for interfacing EDA tools
2023-01-08 01:40:50 -08:00
Yuri Victorovich
019de3fad3
cad/py-vunit-hdl: New pert: Open source unit testing framework for VHDL/SystemVerilog
2023-01-08 01:40:50 -08:00
Yuri Victorovich
2a67d46b21
cad/veryl: New port: Veryl: A modern Hardware Description Language (HDL)
2023-01-05 23:17:54 -08:00
Yuri Victorovich
6949aaa8e7
cad/svls: New port: SystemVerilog language server
2023-01-05 23:17:53 -08:00
Yuri Victorovich
310dfe867f
cad/svlint: New port: SystemVerilog linter
2023-01-02 16:37:15 -08:00
Muhammad Moinur Rahman
06039e52c8
cad/basicdsp: Cleanup EXPIRED ports
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Approved by: portmgr
2022-12-31 03:03:07 +01:00
Rene Ladan
2e1bdcb11a
cleanup: Remove expired ports:
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2022-12-31 cad/linux-eagle5: Deprecated upstream, superseded by Autodesk EAGLE 9
2022-12-31 02:34:28 +01:00
Yuri Victorovich
33e01a0d93
cad/py-pygmsh: New port: Python frontend for Gmsh (on top of Gmsh's own binding)
2022-12-20 00:13:24 -08:00
Yuri Victorovich
941a325490
cad/py-gmsh: New port: Automatic 3D finite element mesh generator (gmsh's own binding)
2022-12-19 20:18:55 -08:00
Yuri Victorovich
8e7be7293a
cad/libgdsii: New port: C++ library and command-line utility for reading GDSII geometry files
2022-11-19 22:22:40 -08:00
Yuri Victorovich
7cae277828
cad/qucsator: New port: Circuit simulator of the Qucs project
2022-07-09 11:52:24 -07:00
Yuri Victorovich
50ea5005f3
cad/xyce: New port: Xyce electronic simulator
2022-07-08 22:46:57 -07:00
Yuri Victorovich
7609fce6eb
cad/qucs-s: New port: Quite Universal Circuit Simulator: GUI for circuit simulation kernels
2022-07-08 00:42:28 -07:00
Robert Clausecker
5831e0c7d9
Add cad/pcb-rnd: Flexible, modular Printed Circuit Board editor
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PR: 264289
2022-06-05 23:26:25 +08:00
Robert Clausecker
0ce9a5d60b
Add cad/pcb-rnd: Flexible, modular Printed Circuit Board editor
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PR: 264289
2022-06-05 23:19:51 +08:00
Thierry Thomas
3a63bbd85b
cad/camotics: adding CAMotics, Simulation & Computer Aided Machining
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The latest stable release, v1.2.0, is for Python-2.7, this is why I
ported this -RC1, but it is somewhat buggy. Do not hesitate to report
any problem!
PR: 262763
Requested by: luzpaz (at) pm.me
2022-05-21 10:56:42 +02:00
Rene Ladan
8e2a89b541
cleanup: Remove ports depending on expired lang/gcc6-aux
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Keep ports-mgmt/synth and dependencies (including lang/gcc6-aux itself)
for now as synth is the only Ada port still maintained and might be
somewhat high-profile.
Removed ports:
archivers/zip-ada
cad/ghdl
databases/adabase
databases/apq
databases/apq-mysql
databases/apq-odbc
databases/apq-pgsql
devel/ada-util
devel/adabooch
devel/adaid
devel/ahven
devel/alog
devel/aunit
devel/florist-gpl
devel/gprbuild
devel/libspark2012
devel/matreshka
devel/pcsc-ada
devel/pragmarcs
devel/sdl_gnat
dns/ironsides
graphics/generic_image_decoder
lang/adacontrol
lang/asis
lang/gnat_util
lang/lua-ada
math/plplot-ada
misc/excel-writer
net/adasockets
net/anet
security/libadacrypt
textproc/adabrowse
textproc/templates_parser
textproc/words
textproc/xmlada
x11-toolkits/gtkada
x11-toolkits/gtkada3
2022-02-28 22:34:25 +01:00
Yuri Victorovich
18da1ab515
cad/opencascade740: Resurrect cad/opencascade @ version 7.4.0
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This is needed for science/chrono.
2022-01-29 22:01:48 -08:00
Yuri Victorovich
43ad336cc5
cad/padring: New port: Padring generator for ASICs
2021-12-29 22:15:37 -08:00
Yuri Victorovich
e1f76ec54d
cad/cvc: New port: Circuit Validity Checker
2021-12-28 23:37:20 -08:00
Yuri Victorovich
7792fd3b7d
cad/uhdm: New port: Universal Hardware Data Model
2021-12-27 09:29:43 -08:00
Yuri Victorovich
d7ee1b9f2e
cad/surelog: New port: SystemVerilog 2017 Pre-processor, Parser, Elaborator, etc
2021-12-27 09:09:30 -08:00
Yuri Victorovich
0f5b6cdfcf
cad/py-pymtl: New port: Python-based hardware generation, simulation, verification framework
2021-12-26 18:31:33 -08:00
Yuri Victorovich
3d127a91e2
cad/gds3d: New port: Application for rendering IC (chip) layouts in 3D
2021-10-04 00:09:03 -07:00
Yuri Victorovich
2983be6402
cad/opentimer: New port: High-performance timing analysis tool for VLSI systems
2021-09-12 16:29:32 -07:00
Yuri Victorovich
2432d929bc
cad/appcsxcad: New port: Minimal GUI Application using the QCSXCAD library
2021-08-19 01:46:12 -07:00
Yuri Victorovich
b95416f60a
cad/qcsxcad: New port: Qt-GUI for CSXCAD
2021-08-19 01:46:11 -07:00
