a graphical waveform viewer and a source level debugger. It also aims at
VHDL-93 compliancy. The project is at a very early development stage.
WWW: http://www.freehdl.seul.org/
PR: ports/104634
Submitted by: lon_kamikaze at gmx.de
many forms of circuit design, including:
- Custom IC layout (ASICs)
- Schematic drawing
- Hardware description language specifications
Author: Static Free Software & Sun Microsystems, Inc.
WWW: http://www.staticfreesoft.com/
PR: ports/100355
Submitted by: me (stas)
Approved by: sem (mentor)
simulation engines: GNU-Cap and Ng-Spice.
Current features:
Import gschem schematic files using gentlist.
Load and parse circuit description (net list) files.
Provides a GUI interface for GNU-Cap OP, DC, AC and Transient
analyses and generates appropriate simulator commands
based on user input.
Provides a GUI interface for Ng-Spice DC, AC and Transient
analyses and generates appropriate simulator commands
based on user input.
The raw output may be viewed for any processes initiated by gspiceui.
Formatting of simulator output so that it may be plotted using gwave.
WWW: http://www.geda.seul.org/tools/gspiceui/index.html
PR: ports/99357
Submitted by: Stanislav Sedov <ssedov at mbsd.msk.ru>
specified in high-level description language into ready-to-compile c code for
the API of spice simulators.
WWW: http://mot-adms.sourceforge.net/
PR: ports/101014
Submitted by: Stanislav Sedov <ssedov at mbsd.msk.ru>
working with superconducting Josephson junction circuits, yet the program
has the flexibility and power to meet the needs of other technologies.
Jspice3 is an adaptation of the Berkeley Spice3f4 program, with added
features. One added feature is a built-in graphical input front end for
schematic capture. While displayed, simulations can be run and data
plotted through this graphical interface.
While not as powerful or as pretty as the Xic graphical interface, it
holds its own in functionality.
A significantly enhanced output plotting capability is provided, and
Jspice3 has enhanced script interpretation capability.
WWW: http://www.wrcad.com/jspice3.html
PR: ports/93958
Submitted by: Pedro F. Giffuni
Pedro can't maintain this port anymore and Stanislav Sedov agree to maintiant it.
1) gTAG - USB to JTAG interface
2) lightning_detector - a lightning detector
3) RF_Amp - schematics and associated materials for a SPICE model
4) TwoStageAmp - a two stage amplifier SPICE playpen
WWW: http://www.geda.seul.org
PR: ports/99564
Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru>
the Tcl/Tk scripting language. The project is open-source (BSD license)
and based upon the NG-Spice source code base with many improvements
Features and Improvements
- Fully Tcl scriptable - installs with 'package require spice' statement
- Hspice syntax (SpicePP).
- GUI interfaces, various (Tk).
- SpiceWish (BLT graph widget)
- BLT (tcl compatible) vectors for storage, manipulation and arithmetic
upon Spice waveforms.
- Xspice additions (Georgia Tech).
- Trigger upon waveform events.
- Spice 'simulator state' save and restore for rapid 'what-if' simulations
(no longer need to re-simulate from the beginning each time a
device value is changed).
Author: Stefan Jones <stefan.jones@multigig.com>
WWW: http://tclspice.sourceforge.net/
PR: ports/99399
Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru>
This is a FEA program used in a classic FEM book. A complete (commercial)
version is available here:
<http://www.ce.berkeley.edu/~rlt/feap/>
The "personal version" is very limited, but it keeps the same format as
the complete (commercial) version and cad/netgen can produce files for it.
PR: ports/95210
Submitted by: Pedro F. Giffuni <giffunip (at) asme.org>
partitioning, static mapping, and sparse matrix block ordering.
Its purpose of Scotch is to apply graph theory, with a divide and conquer
approach, to scientific computing problems such as graph and mesh partitioning,
static mapping, and sparse matrix ordering, in application domains ranging from
structural mechanics to operating systems or bio-chemistry.
Note: there is an older tarball included in Aster's distfile, but I prefer
a separate distfile from the official site.
GPL Cver is a full 1995 P1364 Verilog standard HDL simulator.
It also implements some of the 2001 P1364 standard features
including all three PLI interfaces (tf_, acc_ and vpi_) as
defined in the 2001 Language Reference Manual (LRM).
Verilog is the name for both a language for describing
electronic hardware called a hardware description language
(HDL) and the name of the program that simulates HDL circuit
descriptions to verify that described circuits will function
correctly when the are constructed. Verilog is used only
for describing digital logic circuits. Other HDLs such as
Spice are used for describing analog circuits. There is an
IEEE standard named P1364 that standardizes the Verilog HDL
and the behavior of Verilog simulators. Verilog is officially
defined in the IEEE P1364 Language Reference Manual (LRM)
that can be purchased from IEEE. There are many good books
for learning that teach the Verilog HDL and/or that teach
digital circuit design using Verilog.
WWW: http://www.pragmatic-c.com/gpl-cver/
PR: ports/80968
Submitted by: Ying-Chieh Liao <ijliao@csie.nctu.edu.tw>
diagrams and printed circuit board artwork.
Kicad is a set of four softwares and a project manager:
* Eeschema: Schematic entry.
* Pcbnew: Board editor.
* Gerbview: GERBER viewer (photoplotter documents).
* Cvpcb: footprint selector for components used in the circuit design.
* Kicad: project manager.
portable libraries for VLSI design. It includes a VHDL compiler
and simulator, logic synthesis tools, automatic place and route
tools, and portable CMOS libraries.
Approved by: linimon (mentor)
tochnog is a free finite element program with many features which is
distributed under GPL. TOCHNOG accepts free format input.
Boundary conditions can be imposed at geometrical entities,
as well as nodes and elements.
PR: 52088
Submitted by: Pedro F. Giffuni <giffunip@yahoo.com>
A free CAD system and high level development tool for
Engineering. It's a very interesting port for some branches
of engineering.
PR: ports/52202
Submitted by: Pedro F. Giffuni <giffunip@yahoo.com>
