language. It includes:
* Verilog::Getopt which parses command line options similar to C++ and VCS.
* Verilog::Language which knows the language keywords and parses numbers.
* Verilog::Netlist which builds netlists out of Verilog files. This allows
easy scripts to determine things such as the hierarchy of modules.
* Verilog::Parser invokes callbacks for language tokens.
* Verilog::Preproc preprocesses the language, and allows reading
post-processed files right from Perl without temporary files.
* vpassert inserts PLIish warnings and assertions for any simulator.
* vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language.
* vrename renames and cross-references Verilog symbols. Vrename creates Verilog
cross references and makes it easy to rename signal and module names across
multiple files. Vrename uses a simple and efficient three step process.
First, you run vrename to create a list of signals in the design. You then
edit this list, changing as many symbols as you wish. Vrename is then run a
second time to apply the changes.
WWW: http://www.veripool.org/wiki/verilog-perl
PR: ports/134124
Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto at ee.ufcg.edu.br>
Digital Signal Processing algorithms for audio signals. The input can either
be taken from the sound card, or be a locally generated sine wave, white noise
or impulse signal. The output is fed to the sound card, as well as to a virtual
oscilloscope and spectrum analyzer.
The 3.x train of GTKWave has significantly more new featured and bugfixes,
but would require introducing PORTEPOCH to replace cad/gtkwave.
[Timeout on feedback from cad/gtkwave maintainer.]
It features some key concepts like macro recording, workbenches, ability to run
as a server and dynamically loadable application extensions and it is designed
to be platform independent.
Warning: FreeCAD is still in ALPHA state and not in shape for end user usage!
<http://juergen-riegel.net/FreeCAD/Docu/>
Suggested by: Pedro F. Giffuni <giffunip (at) yahoo.com>
---When you have a large number of or big layout/schematic/TeX files which
have possibly many top cells made by other people, how can you manage
those layout/schematic/TeXs? FH is written for that. It can be useful
up to your imagination or shell programming skill. FH analyses the
hidden hierarchies of those cells and shows you the hierarchy information.
open source. It includes components for 3D surface and solid modeling,
visualization, data exchange and rapid application development.
Open CASCADE Technology can be best applied in development of numerical
simulation software including CAD/CAM/CAE, AEC and GIS, as well as PDM
applications.
BUGS: the module WOK does not work, but the other modules (the most
interesting parts) are OK.
a graphical waveform viewer and a source level debugger. It also aims at
VHDL-93 compliancy. The project is at a very early development stage.
WWW: http://www.freehdl.seul.org/
PR: ports/104634
Submitted by: lon_kamikaze at gmx.de
many forms of circuit design, including:
- Custom IC layout (ASICs)
- Schematic drawing
- Hardware description language specifications
Author: Static Free Software & Sun Microsystems, Inc.
WWW: http://www.staticfreesoft.com/
PR: ports/100355
Submitted by: me (stas)
Approved by: sem (mentor)
simulation engines: GNU-Cap and Ng-Spice.
Current features:
Import gschem schematic files using gentlist.
Load and parse circuit description (net list) files.
Provides a GUI interface for GNU-Cap OP, DC, AC and Transient
analyses and generates appropriate simulator commands
based on user input.
Provides a GUI interface for Ng-Spice DC, AC and Transient
analyses and generates appropriate simulator commands
based on user input.
The raw output may be viewed for any processes initiated by gspiceui.
Formatting of simulator output so that it may be plotted using gwave.
WWW: http://www.geda.seul.org/tools/gspiceui/index.html
PR: ports/99357
Submitted by: Stanislav Sedov <ssedov at mbsd.msk.ru>
specified in high-level description language into ready-to-compile c code for
the API of spice simulators.
WWW: http://mot-adms.sourceforge.net/
PR: ports/101014
Submitted by: Stanislav Sedov <ssedov at mbsd.msk.ru>
working with superconducting Josephson junction circuits, yet the program
has the flexibility and power to meet the needs of other technologies.
Jspice3 is an adaptation of the Berkeley Spice3f4 program, with added
features. One added feature is a built-in graphical input front end for
schematic capture. While displayed, simulations can be run and data
plotted through this graphical interface.
While not as powerful or as pretty as the Xic graphical interface, it
holds its own in functionality.
A significantly enhanced output plotting capability is provided, and
Jspice3 has enhanced script interpretation capability.
WWW: http://www.wrcad.com/jspice3.html
PR: ports/93958
Submitted by: Pedro F. Giffuni
Pedro can't maintain this port anymore and Stanislav Sedov agree to maintiant it.
1) gTAG - USB to JTAG interface
2) lightning_detector - a lightning detector
3) RF_Amp - schematics and associated materials for a SPICE model
4) TwoStageAmp - a two stage amplifier SPICE playpen
WWW: http://www.geda.seul.org
PR: ports/99564
Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru>
the Tcl/Tk scripting language. The project is open-source (BSD license)
and based upon the NG-Spice source code base with many improvements
Features and Improvements
- Fully Tcl scriptable - installs with 'package require spice' statement
- Hspice syntax (SpicePP).
- GUI interfaces, various (Tk).
- SpiceWish (BLT graph widget)
- BLT (tcl compatible) vectors for storage, manipulation and arithmetic
upon Spice waveforms.
- Xspice additions (Georgia Tech).
- Trigger upon waveform events.
- Spice 'simulator state' save and restore for rapid 'what-if' simulations
(no longer need to re-simulate from the beginning each time a
device value is changed).
Author: Stefan Jones <stefan.jones@multigig.com>
WWW: http://tclspice.sourceforge.net/
PR: ports/99399
Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru>
This is a FEA program used in a classic FEM book. A complete (commercial)
version is available here:
<http://www.ce.berkeley.edu/~rlt/feap/>
The "personal version" is very limited, but it keeps the same format as
the complete (commercial) version and cad/netgen can produce files for it.
PR: ports/95210
Submitted by: Pedro F. Giffuni <giffunip (at) asme.org>
partitioning, static mapping, and sparse matrix block ordering.
Its purpose of Scotch is to apply graph theory, with a divide and conquer
approach, to scientific computing problems such as graph and mesh partitioning,
static mapping, and sparse matrix ordering, in application domains ranging from
structural mechanics to operating systems or bio-chemistry.
Note: there is an older tarball included in Aster's distfile, but I prefer
a separate distfile from the official site.
GPL Cver is a full 1995 P1364 Verilog standard HDL simulator.
It also implements some of the 2001 P1364 standard features
including all three PLI interfaces (tf_, acc_ and vpi_) as
defined in the 2001 Language Reference Manual (LRM).
Verilog is the name for both a language for describing
electronic hardware called a hardware description language
(HDL) and the name of the program that simulates HDL circuit
descriptions to verify that described circuits will function
correctly when the are constructed. Verilog is used only
for describing digital logic circuits. Other HDLs such as
Spice are used for describing analog circuits. There is an
IEEE standard named P1364 that standardizes the Verilog HDL
and the behavior of Verilog simulators. Verilog is officially
defined in the IEEE P1364 Language Reference Manual (LRM)
that can be purchased from IEEE. There are many good books
for learning that teach the Verilog HDL and/or that teach
digital circuit design using Verilog.
WWW: http://www.pragmatic-c.com/gpl-cver/
PR: ports/80968
Submitted by: Ying-Chieh Liao <ijliao@csie.nctu.edu.tw>
diagrams and printed circuit board artwork.
Kicad is a set of four softwares and a project manager:
* Eeschema: Schematic entry.
* Pcbnew: Board editor.
* Gerbview: GERBER viewer (photoplotter documents).
* Cvpcb: footprint selector for components used in the circuit design.
* Kicad: project manager.
portable libraries for VLSI design. It includes a VHDL compiler
and simulator, logic synthesis tools, automatic place and route
tools, and portable CMOS libraries.
Approved by: linimon (mentor)
