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ae72ccaa56
PR: ports/171063 Approved by: otacilio.neto@ee.ufcg.edu.br (maintainer)
54 lines
1.4 KiB
Makefile
54 lines
1.4 KiB
Makefile
# New ports collection makefile for: Verilog-Perl
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# Date created: 11 Apr 2009
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# Whom: Otacilio de Araujo Ramos Neto <otacilio.neto@ee.ufcg.edu.br>
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#
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# $FreeBSD$
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#
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PORTNAME= Verilog-Perl
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PORTVERSION= 3.316
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CATEGORIES= cad perl5
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MASTER_SITES= CPAN
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PKGNAMEPREFIX= p5-
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MAINTAINER= otacilio.neto@ee.ufcg.edu.br
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COMMENT= Building point for Verilog support in the Perl language
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BUILD_DEPENDS= flex>=2.5.35:${PORTSDIR}/textproc/flex
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USE_GMAKE= yes
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USE_PERL5= yes
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USE_BISON= build
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PERL_CONFIGURE= yes
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MAN1= vhier.1 vpassert.1 vppreproc.1 vrename.1
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MAN3= Verilog::EditFiles.3 Verilog::Netlist::Logger.3 \
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Verilog::Parser.3 Verilog::Getopt.3 Verilog::Netlist::Module.3 \
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Verilog::Preproc.3 Verilog::Language.3 Verilog::Netlist::Net.3 \
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Verilog::SigParser.3 Verilog::Netlist.3 Verilog::Netlist::Pin.3 \
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Verilog::Netlist::Cell.3 Verilog::Netlist::Port.3 Verilog::Netlist::Defparam.3 \
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Verilog::Netlist::File.3 Verilog::Netlist::Subclass.3 \
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Verilog::Netlist::ContAssign.3 Verilog::Netlist::ModPort.3 \
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Verilog::Verilog-Perl.3 Verilog::Netlist::Interface.3 Verilog::Std.3
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.include <bsd.port.pre.mk>
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post-patch:
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@${REINPLACE_CMD} -e '/EXE_FILES/ s/ vsplitmodule//' \
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${WRKSRC}/Makefile.PL
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post-configure:
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.if ${OSVERSION} < 700042
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@${REINPLACE_CMD} -e 's|-O2|-O|g' ${WRKSRC}/Makefile
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.endif
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post-build:
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cd ${WRKSRC} && make test
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test:
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make post-build
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.include <bsd.port.post.mk>
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