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7d98596c5e
- Fix comment - Update pkg-desck - Use %%DOCSDIR%% and %%DATADIR%% macroses - Bump PORTREVISION - Mark BROKEN on 4.x - Rename directory from gnetlist to geda-netlist [2] PR: ports/100220, ports/100230 [2] Submitted by: maintainer
66 lines
1.6 KiB
Plaintext
66 lines
1.6 KiB
Plaintext
gnetlist is the netlist extraction/generation program which is part
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of gEDA (GPL Electronic Design Automation) toolset. This program takes a
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schematic for its input and outputs a netlist. gnetlist uses scheme to define
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the output format.
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Currently it supports the following backends:
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1) Allegro netlist format (-g allegro)
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2) BAE netlist format (-g bae)
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3) BOM / BOM2 - Bill of Materials (-g bom and -g bom2)
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4) Partslist1,2,3 - More Bill of Materials (-g partslist[1-3])
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5) DRC - Start of a design rule checker (-g drc)
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6) DRC2 - A second design rule checker (-g drc2)
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7) gEDA - native format, mainly used for testing (-g geda)
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8) Gossip netlist format (-g gossip)
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9) PADS netlist format (-g pads)
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10) PCB / PCBboard (-g PCB and -g PCBboard)
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11) gsch2pcb backend (-g gsch2pcb)
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12) ProtelII netlist format (-g protelII)
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13) Spice compatible netlist format (-g spice)
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14) Enhanced spice compatible netlist format (-g spice-sdb)
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15) Switcap netlist format (-g switcap)
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16) Tango netlist format (-g tango)
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17) Verilog code (-g verilog)
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18) VHDL code (-g vhdl)
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19) VIPEC netlist format (-g vipec)
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20) Bartels Autoengineer netlist format (-g bae)
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21) GOSSIP system simulation system netlist format (-g gossip)
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22) MAXASCII netlist format (-g maxascii)
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23) VHDL-AMS netlist format (-g vams)
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24) Futurenet2 netlist format (-g futurenet2 )
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25) SWITCAP switched capacitor simulator netlist format (-g switcap )
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26) RF Cascade netlist format (-g cascade )
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27) RACAL-REDAC netlist format (-g redac )
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28) PCB actions file for forward annotating pin/pad names from
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schematic to layout (-g pcbpins)
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WWW: http://www.geda.seul.org
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