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Project trellis document the bitstream for Lattice ECP5 FPGAs. Used with yosys and nextpnr it can create a full bitstream with only open source tools.
7 lines
263 B
Plaintext
7 lines
263 B
Plaintext
Project Trellis enables a fully open-source flow for ECP5 FPGAs
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using Yosys for Verilog synthesis and nextpnr for place and route.
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Project Trellis itself provides the device database and tools for
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bitstream creation.
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WWW: https://github.com/SymbiFlow/prjtrellis
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